PROBLEMS Circuit Basics As a review of the basics of circuit analysis and in order for the readers to gauge their preparedness for the study of electronic circuits, this section presents a number of relevant circuit analysis problems. For a summary of Th´evenin’s and Norton’s theorems, refer to Appendix D. The problems are grouped in appropriate categories.
Resistors and Ohm’s Law 1.1 Ohm’s law relates V , I, and R for a resistor. For each of the situations following, find the missing item: (a) (b) (c) (d)
R = 1 k0002, V = 5 V V = 5 V, I = 1 mA R = 10 k0002, I = 0.1 mA R = 100 0002, V = 1 V
Note: Volts, milliamps, and kilohms constitute a consistent set of units. 1.2 Measurements taken on various resistors are shown below. For each, calculate the power dissipated in the resistor and the power rating necessary for safe operation using standard components with power ratings of 1/8 W, 1/4 W, 1/2 W, 1 W, or 2 W: (a) (b) (c) (d) (e) (f)
1 k0002 conducting 20 mA 1 k0002 conducting 40 mA 100 k0002 conducting 1 mA 10 k0002 conducting 4 mA 1 k0002 dropping 20 V 1 k0002 dropping 11 V
1.3 Ohm’s law and the power law for a resistor relate V , I, R, and P, making only two variables independent. For each pair identified below, find the other two: (a) (b) (c) (d) (e)
R = 1 k0002, I = 5 mA V = 5 V, I = 1 mA V = 10 V, P = 100 mW I = 0.1 mA, P = 1 mW R = 1 k0002, P = 1 W
Combining Resistors 1.4 You are given three resistors whose values are 10 k0002, 20 k0002, and 40 k0002. How many different resistances can you create using series and parallel combinations of these three? List them in value order, lowest first. Be thorough and
organized. (Hint: In your search, first consider all parallel combinations, then consider series combinations, and then consider series-parallel combinations, of which there are two kinds.) 1.5 In the analysis and test of electronic circuits, it is often useful to connect one resistor in parallel with another to obtain a nonstandard value, one which is smaller than the smaller of the two resistors. Often, particularly during circuit testing, one resistor is already installed, in which case the second, when connected in parallel, is said to “shunt” the first. If the original resistor is 10 k0002, what is the value of the shunting resistor needed to reduce the combined value by 1%, 5%, 10%, and 50%? What is the result of shunting a 10-k0002 resistor by 1 M0002? By 100 k0002? By 10 k0002?
Voltage Dividers 1.6 Figure P1.6(a) shows a two-resistor voltage divider. Its function is to generate a voltage VO (smaller than the power-supply voltage VDD ) at its output node X. The circuit looking back at node X is equivalent to that shown in Fig. P1.6(b). Observe that this is the Th´evenin equivalent of the voltage-divider circuit. Find expressions for VO and RO .
VDD
R1 RO
X
X
VO R2
VO RO (a)
(b)
Figure P1.6
1.7 A two-resistor voltage divider employing a 2-k0002 and a 3-k0002 resistor is connected to a 5-V ground-referenced power supply to provide a 2-V voltage. Sketch the circuit. Assuming exact-valued resistors, what output voltage (measured to ground) and equivalent output resistance result? If the resistors used are not ideal but have a ±5% manufacturing tolerance, what are the extreme output voltages and resistances that can result?
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
D 1.8 You are given three resistors, each of 10 k0002, and a 9-V battery whose negative terminal is connected to ground. With a voltage divider using some or all of your resistors, how many positive-voltage sources of magnitude less than 9 V can you design? List them in order, smallest first. What is the output resistance (i.e., the Th´evenin resistance) of each?
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46 Chapter 1 Signals and Amplifiers
D *1.9 Two resistors, with nominal values of 4.7 k0002 and 10 k0002, are used in a voltage divider with a +15-V supply to create a nominal +5-V output. Assuming the resistor values to be exact, what is the actual output voltage produced? Which resistor must be shunted (paralleled) by what third resistor to create a voltage-divider output of 5.00 V? If an output resistance of exactly 3.33 k0002 is also required, what do you suggest?
D 1.13 A particular electronic signal source generates currents in the range 0 mA to 0.5 mA under the condition that its load voltage not exceed 1 V. For loads causing more than 1 V to appear across the generator, the output current is no longer assured but will be reduced by some unknown amount. This circuit limitation, occurring, for example, at the peak of a sine-wave signal, will lead to undesirable signal distortion that must be avoided. If a 10-k0002 load is to be connected, what must be done? What is the name of the circuit you must use? How many resistors are needed? What is (are) the(ir) value(s)? What is the range of current through the load?
Current Dividers
Thevenin ´ Equivalent Circuits
1.10 Current dividers play an important role in circuit design. Therefore it is important to develop a facility for dealing with current dividers in circuit analysis. Figure P1.10 shows a two-resistor current divider fed with an ideal current source I. Show that
1.14 For the circuit in Fig. P1.14, find the Th´evenin equivalent circuit between terminals (a) 1 and 2, (b) 2 and 3, and (c) 1 and 3.
I1 =
R2 I R1 + R2
I2 =
R1 I R1 + R2
this problem. What is the value of the resistor required in each case? What is the input resistance of the current divider in each case?
1 1 kΩ 1.5 V
2 1 kΩ
and find the voltage V that develops across the current divider.
3 I
I1
I2
0003
R1
R2
V 0002
Figure P1.10
D 1.11 Design a simple current divider that will reduce the current provided to a 10-k0002 load to one-third of that available from the source. D 1.12 A designer searches for a simple circuit to provide one-fifth of a signal current I to a load resistance R. Suggest a solution using one resistor. What must its value be? What is the input resistance of the resulting current divider? For a particular value R, the designer discovers that the otherwise-best-available resistor is 10% too high. Suggest two circuit topologies using one additional resistor that will solve
Figure P1.14
1.15 Through repeated application of Th´evenin’s theorem, find the Th´evenin equivalent of the circuit in Fig. P1.15 between node 4 and ground, and hence find the current that flows through a load resistance of 3 k0002 connected between node 4 and ground.
1 20 kΩ
10 V
20 kΩ
2 20 kΩ
20 kΩ
Figure P1.15
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
3
20 kΩ
20 kΩ
4
Problems 47
a much easier approach is possible: Find the Th´evenin equivalent of the circuit to the left of node 1 and the Th´evenin equivalent of the circuit to the right of node 2. Then solve the resulting simplified circuit.
1.16 For the circuit shown in Fig. P1.16, find the current in each of the three resistors and the voltage (with respect to ground) at their common node using two methods:
Which method do you prefer? Why?
000310 V
00035 V
X Req
R2 5 k0004
R1 10 k0004
R1 1 kV
R3 1 kV
R5 1 kV
R3 2 k0004
R2 1 kV
R4 1 kV
Figure P1.16 Figure P1.18
1.17 The circuit shown in Fig. P1.17 represents the equivalent circuit of an unbalanced bridge. It is required to calculate the current in the detector branch (R5 ) and the voltage across it. Although this can be done by using loop and node equations,
1.19 Derive an expression for vo /vs for the circuit shown in Fig. P1.19.
000310 V
R1
R3
1 k0004
9.1 k0004 1
R5
Rs
2
0003
2 k0004 R2 1.2 k0004
R4 11 k0004
vs
0003 0002
vp
0003 rp
gmvp
ro
0002 Figure P1.17
Figure P1.19
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
RL
vo 0002
PROBLEMS
*1.18 For the circuit in Fig. P1.18, find the equivalent resistance to ground, Req . To do this, apply a voltage Vx between terminal X and ground and find the current drawn from Vx . Note that you can use particular special properties of the circuit to get the result directly! Now, if R4 is raised to 1.2 k0002, what does Req become?
(a) Loop Equations: Define branch currents I1 and I2 in R1 and R2 , respectively; write two equations; and solve them. (b) Node Equation: Define the node voltage V at the common node; write a single equation; and solve it.
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Circuit Analysis
CHAPTER 1
PROBLEMS
48 Chapter 1 Signals and Amplifiers AC Circuits 1.20 The periodicity of recurrent waveforms, such as sine waves or square waves, can be completely specified using only one of three possible parameters: radian frequency, ω, in radians per second (rad/s); (conventional) frequency, f , in hertz (Hz); or period T , in seconds (s). As well, each of the parameters can be specified numerically in one of several ways: using letter prefixes associated with the basic units, using scientific notation, or using some combination of both. Thus, for example, a particular period −1 5 may be specified as 100 ns, 0.1 μs, 10 μs, 10 ps, or −7 1 × 10 s. (For the definition of the various prefixes used in electronics, see Appendix J.) For each of the measures listed below, express the trio of terms in scientific −7 notation associated with the basic unit (e.g., 10 s rather −1 than 10 μs). (a) (b) (c) (d) (e) (f) (g)
−4
T = 10 ms f = 1 GHz 2 ω = 6.28 × 10 rad/s T = 10 s f = 60 Hz ω = 1 krad/s f = 1900 MHz
1.21 Find the complex impedance, Z, of each of the following basic circuit elements at 60 Hz, 100 kHz, and 1 GHz: (a) (b) (c) (d) (e)
R = 1 k0002 C = 10 nF C = 10 pF L = 10 mH L = 1 μH
1.22 Find the complex impedance at 10 kHz of the following networks: (a) (b) (c) (d)
1 k0002 in series with 10 nF 10 k0002 in parallel with 0.01 μF 100 k0002 in parallel with 100 pF 100 0002 in series with 10 mH
Section 1.1: Signals 1.23 Any given signal source provides an open-circuit voltage, v oc , and a short-circuit current, isc . For the following
sources, calculate the internal resistance, Rs ; the Norton current, is ; and the Th´evenin voltage, v s : (a) v oc = 1 V, isc = 0.1 mA (b) v oc = 0.1 V, isc = 1 μA 1.24 A particular signal source produces an output of 40 mV when loaded by a 100-k0002 resistor and 10 mV when loaded by a 10-k0002 resistor. Calculate the Th´evenin voltage, Norton current, and source resistance. 1.25 A temperature sensor is specified to provide 2 mV/°C. When connected to a load resistance of 5 k0002, the output voltage was measured to change by 10 mV, corresponding to a change in temperature of 10°C. What is the source resistance of the sensor? 1.26 Refer to the Th´evenin and Norton representations of the signal source (Fig. 1.1). If the current supplied by the source is denoted io and the voltage appearing between the source output terminals is denoted v o , sketch and clearly label v o versus io for 0 ≤ io ≤ is . 1.27 The connection of a signal source to an associated signal processor or amplifier generally involves some degree of signal loss as measured at the processor or amplifier input. Considering the two signal-source representations shown in Fig. 1.1, provide two sketches showing each signal-source representation connected to the input terminals (and corresponding input resistance) of a signal processor. What signal-processor input resistance will result in 95% of the open-circuit voltage being delivered to the processor? What input resistance will result in 95% of the short-circuit signal current entering the processor?
Section 1.2: Frequency Spectrum of Signals 1.28 To familiarize yourself with typical values of angular frequency ω, conventional frequency f , and period T , complete the entries in the following table: Case
a b c d e f
ω (rad/s)
f (Hz)
T (s)
5 × 109 2 × 10
9
1 × 10−10 60
6.28 × 104
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
1 × 10−5
Problems 49
1.30 Give expressions for the sine-wave voltage signals having: (a) (b) (c) (d)
10-V peak amplitude and 1-kHz frequency 120-V rms and 60-Hz frequency 0.2-V peak-to-peak and 2000-rad/s frequency 100-mV peak and 1-ms period
1.31 Using the information provided by Eq. (1.2) in association with Fig. 1.5, characterize the signal represented by v(t) = 1/2 + 2/π(sin 2000π t + 13 sin 6000πt + 1 sin 10, 000πt + · · · ). Sketch the waveform. What is its 5 average value? Its peak-to-peak value? Its lowest value? Its highest value? Its frequency? Its period? 1.32 Measurements taken of a square-wave signal using a frequency-selective voltmeter (called a spectrum analyzer) show its spectrum to contain adjacent components (spectral lines) at 98 kHz and 126 kHz of amplitudes 63 mV and 49 mV, respectively. For this signal, what would direct measurement of the fundamental show its frequency and amplitude to be? What is the rms value of the fundamental? What are the peak-to-peak amplitude and period of the originating square wave? 1.33 Find the amplitude of a symmetrical square wave of period T that provides the same power as a sine wave of peak
Section 1.3: Analog and Digital Signals 1.34 Give the binary representation of the following decimal numbers: 0, 6, 11, 28, and 59. 1.35 Consider a 4-bit digital word b3 b2 b1 b0 in a format called signed-magnitude, in which the most significant bit, b3 , is interpreted as a sign bit—0 for positive and 1 for negative values. List the values that can be represented by this scheme. What is peculiar about the representation of zero? For a particular analog-to-digital converter (ADC), each change in b0 corresponds to a 0.5-V change in the analog input. What is the full range of the analog signal that can be represented? What signed-magnitude digital code results for an input of +2.5 V? For −3.0 V? For +2.7 V? For −2.8 V? 1.36 Consider an N-bit ADC whose analog input varies between 0 and VFS (where the subscript FS denotes “full scale”). (a) Show that the least significant bit (LSB) corresponds to N a change in the analog signal of VFS /(2 − 1). This is the resolution of the converter. (b) Convince yourself that the maximum error in the conversion (called the quantization error) is half the N resolution; that is, the quantization error = VFS /2(2 − 1). (c) For VFS = 5 V, how many bits are required to obtain a resolution of 2 mV or better? What is the actual resolution obtained? What is the resulting quantization error? 1.37 Figure P1.37 shows the circuit of an N-bit digital-to-analog converter (DAC). Each of the N bits of the digital word to be converted controls one of the switches.
Vref 2R
4R
b1 0
b2 1
0
2NR
8R b3
1
0
bN 1
0
1 iO
Figure P1.37
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
(a) 117 V rms, a household-power voltage in North America (b) 33.9 V peak, a somewhat common peak voltage in rectifier circuits (c) 220 V rms, a household-power voltage in parts of Europe (d) 220 kV rms, a high-voltage transmission-line voltage in North America
amplitude Vˆ and the same frequency. Does this result depend on equality of the frequencies of the two waveforms?
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1.29 For the following peak or rms values of some important sine waves, calculate the corresponding other value:
CHAPTER 1
PROBLEMS
50 Chapter 1 Signals and Amplifiers When the bit is 0, the switch is in the position labeled 0; when the bit is 1, the switch is in the position labeled 1. The analog output is the current iO .Vref is a constant reference voltage. (a) Show that
iO =
Vref R
0004
b1 b2 b + + · · · + NN 21 22 2
0005
(b) Which bit is the LSB? Which is the MSB? (c) For Vref = 10 V, R = 10 k0002, and N = 8, find the maximum value of iO obtained. What is the change in iO resulting from the LSB changing from 0 to 1? 1.38 In compact-disc (CD) audio technology, the audio signal is sampled at 44.1 kHz. Each sample is represented by 16 bits. What is the speed of this system in bits per second?
Section 1.4: Amplifiers 1.39 Various amplifier and load combinations are measured as listed below using rms values. For each, find the voltage, current, and power gains (Av , Ai , and Ap , respectively) both as ratios and in dB: (a) v I = 100 mV, iI = 100 μA, v O = 10 V, RL = 100 0002 (b) v I = 10 μV, iI = 100 nA, v O = 1 V, RL = 10 k0002 (c) v I = 1 V, iI = 1 mA, v O = 5 V, RL = 10 0002 1.40 An amplifier operating from ±3-V supplies provides a 2.2-V peak sine wave across a 100-0002 load when provided with a 0.2-V peak input from which 1.0 mA peak is drawn. The average current in each supply is measured to be 20 mA.Find the voltage gain, current gain, and power gain expressed as ratios and in decibels as well as the supply power, amplifier dissipation, and amplifier efficiency. 1.41 An amplifier using balanced power supplies is known to saturate for signals extending within 1.0 V of either supply. For linear operation, its gain is 200 V/V. What is the rms value of the largest undistorted sine-wave output available, and input needed, with ±5-V supplies? With ±10-V supplies? With ±15-V supplies?
1.42 Symmetrically saturating amplifiers, operating in the so-called clipping mode, can be used to convert sine waves to pseudo-square waves. For an amplifier with a small-signal gain of 1000 and clipping levels of ±10 V, what peak value of input sinusoid is needed to produce an output whose extremes are just at the edge of clipping? Clipped 90% of the time? Clipped 99% of the time?
Section 1.5: Circuit Models for Amplifiers 1.43 Consider the voltage-amplifier circuit model shown in Fig. 1.16(b), in which Av o = 100 V/V under the following conditions: (a) Ri = 10Rs , RL = 10Ro (b) Ri = Rs , RL = Ro (c) Ri = Rs /10, RL = Ro /10 Calculate the overall voltage gain v o /v s in each case, expressed both directly and in decibels. 1.44 An amplifier with 40 dB of small-signal, open-circuit voltage gain, an input resistance of 1 M0002, and an output resistance of 100 0002, drives a load of 500 0002. What voltage and power gains (expressed in dB) would you expect with the load connected? If the amplifier has a peak output-current limitation of 20 mA, what is the rms value of the largest sine-wave input for which an undistorted output is possible? What is the corresponding output power available? 1.45 A 10-mV signal source having an internal resistance of 100 k0002 is connected to an amplifier for which the input resistance is 10 k0002, the open-circuit voltage gain is 1000 V/V, and the output resistance is 1 k0002. The amplifier is connected in turn to a 100-0002 load. What overall voltage gain results as measured from the source internal voltage to the load? Where did all the gain go? What would the gain be if the source was connected directly to the load? What is the ratio of these two gains? This ratio is a useful measure of the benefit the amplifier brings. 1.46 A buffer amplifier with a gain of 1 V/V has an input resistance of 1 M0002 and an output resistance of 20 0002. It is connected between a 1-V, 200-k0002 source and a 100-0002
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 51
1.47 Consider the cascade amplifier of Example 1.3. Find the overall voltage gain v o /v s obtained when the first and second stages are interchanged. Compare this value with the result in Example 1.3, and comment.
(a) What is the required voltage gain from the source to the load? (b) If the peak current available from the source is 0.1 μA, what is the smallest input resistance allowed? For the design with this value of Ri , find the overall current gain and power gain. (c) If the amplifier power supply limits the peak value of the output open-circuit voltage to 3 V, what is the largest output resistance allowed? (d) For the design with Ri as in (b) and Ro as in (c), what0003 is the v 0003 , required value of open-circuit voltage gain, i.e., o 00030003 v i RL = ∞
D *1.49 A designer has available voltage amplifiers with an input resistance of 10 k0002, an output resistance of 1 k0002, and an open-circuit voltage gain of 10. The signal source has a 10-k0002 resistance and provides a 5-mV rms signal, and it is required to provide a signal of at least 3 V rms to a 200-0002 load. How many amplifier stages are required? What is the output voltage actually obtained? D *1.50 Design an amplifier that provides 0.5 W of signal power to a 100-0002 load resistance. The signal source provides a 30-mV rms signal and has a resistance of 0.5 M0002. Three types of voltage-amplifier stages are available: (a) A high-input-resistance type with Ri = 1 M0002, Av o = 10, and Ro = 10 k0002 (b) A high-gain type with Ri = 10 k0002, Av o = 100, and Ro = 1 k0002 (c) A low-output-resistance type with Ri = 10 k0002, Av o = 1, and Ro = 20 0002 Design a suitable amplifier using a combination of these stages. Your design should utilize the minimum number of stages and should ensure that the signal level is not reduced below 10 mV at any point in the amplifier chain. Find the load voltage and power output realized.
of the amplifier? (e) If, as a possible design option, you are able to increase Ri n to the nearest value of the form 1 × 10 0002 and to decrease m Ro to the nearest value of the form 1 × 10 0002, find (i) the input resistance achievable; (ii) the output resistance achievable; and (iii) the open-circuit voltage gain now required to meet the specifications. D 1.52 A voltage amplifier with an input resistance of 20 k0002, an output resistance of 100 0002, and a gain of 1000 V/V is connected between a 100-k0002 source with an open-circuit voltage of 10 mV and a 100-0002 load. For this situation: (a) What output voltage results? (b) What is the voltage gain from source to load? (c) What is the voltage gain from the amplifier input to the load? (d) If the output voltage across the load is twice that needed and there are signs of internal amplifier overload, suggest the location and value of a single resistor that would produce the desired output. Choose an arrangement that would cause minimum disruption to an operating circuit. (Hint: Use parallel rather than series connections.)
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
1.48 You are given two amplifiers, A and B, to connect in cascade between a 10-mV, 100-k0002 source and a 100-0002 load. The amplifiers have voltage gain, input resistance, and output resistance as follows: for A, 100 V/V, 100 k0002, 10 k0002, respectively; for B, 10 V/V, 10 k0002, 1 k0002, respectively. Your problem is to decide how the amplifiers should be connected. To proceed, evaluate the two possible connections between source S and load L, namely, SABL and SBAL. Find the voltage gain for each both as a ratio and in decibels. Which amplifier arrangement is best?
D *1.51 It is required to design a voltage amplifier to be driven from a signal source having a 5-mV peak amplitude and a source resistance of 10 k0002 to supply a peak output of 2 V across a 1-k0002 load.
CHAPTER 1
load. What load voltage results? What are the corresponding voltage, current, and power gains (in dB)?
PROBLEMS
1.53 A voltage amplifier delivers 200 mV across a load resistance of 1 k0002. It was found that the output voltage decreases by 5 mV when RL is decreased to 780 0002. What are the values of the open-circuit output voltage and the output resistance of the amplifier?
CHAPTER 1
52 Chapter 1 Signals and Amplifiers
1.54 A current amplifier supplies 1 mA to a load resistance of 1 k0002. When the load resistance is increased to 12 k0002, the output current decreases to 0.5 mA. What are the values of the short-circuit output current and the output resistance of the amplifier? 1.55 A current amplifier for which Ri = 100 0002, Ro = 10 k0002, and Ais = 100 A/A is to be connected between a 100-mV source with a resistance of 10 k0002 and a load of 1 k0002. What are the values of current gain io /ii , of voltage gain v o /v s , and of power gain expressed directly and in decibels? 1.56 A transconductance amplifier with Ri = 2 k0002, Gm = 60 mA/V, and Ro = 20 k0002 is fed with a voltage source having a source resistance of 1 k0002 and is loaded with a 1-k0002 resistance. Find the voltage gain realized. D **1.57 A designer is required to provide, across a 10-k0002 load, the weighted sum, v O = 10v 1 + 20v 2 , of input signals v 1 and v 2 , each having a source resistance of 10 k0002. She has a number of transconductance amplifiers for which the input and output resistances are both 10 k0002 and Gm = 20 mA/V, together with a selection of suitable resistors. Sketch an appropriate amplifier topology with additional resistors selected to provide the desired result. Your design should utilize the minimum number of amplifiers and resistors. (Hint: In your design, arrange to add currents.) 1.58 Figure P1.58 shows a transconductance amplifier whose output is fed back to its input. Find the input resistance Rin of the resulting one-port network. (Hint: Apply a test voltage v x between the two input terminals, and find the current ix drawn from the source. Then, Rin ≡ v x /ix .)
Rin Figure P1.58
D 1.59 It is required to design an amplifier to sense the open-circuit output voltage of a transducer and to provide a proportional voltage across a load resistor. The equivalent source resistance of the transducer is specified to vary in the range of 1 k0002 to 10 k0002. Also, the load resistance varies in the range of 1 k0002 to 10 k0002. The change in load voltage corresponding to the specified change in Rs should be 10% at most. Similarly, the change in load voltage corresponding to the specified change in RL should be limited to 10%. Also, corresponding to a 10-mV transducer open-circuit output voltage, the amplifier should provide a minimum of 1 V across the load. What type of amplifier is required? Sketch its circuit model, and specify the values of its parameters. Specify appropriate values for Ri and Ro of the form m 1 × 10 0002. D 1.60 It is required to design an amplifier to sense the short-circuit output current of a transducer and to provide a proportional current through a load resistor. The equivalent source resistance of the transducer is specified to vary in the range of 1 k0002 to 10 k0002. Similarly, the load resistance is known to vary over the range of 1 k0002 to 10 k0002. The change in load current corresponding to the specified change in Rs is required to be limited to 10%. Similarly, the change in load current corresponding to the specified change in RL
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 53
D 1.62 It is required to design an amplifier to sense the short-circuit output current of a transducer and to provide a proportional voltage across a load resistor. The equivalent source resistance of the transducer is specified to vary in the range of 1 k0002 to 10 k0002. Similarly, the load resistance is known to vary in the range of 1 k0002 to 10 k0002. The change in load voltage corresponding to the specified change in Rs should be 10% at most. Similarly, the change in load voltage corresponding to the specified change in RL is to be limited to 10%. Also, for a nominal transducer short-circuit output current of 10 μA, the amplifier is required to provide a minimum voltage across the load of 1 V. What type of amplifier is required? Sketch its circuit model, and specify the values of the model parameters. For Ri and Ro , specify m appropriate values in the form 1 × 10 0002.
1.63 For the circuit in Fig. P1.63, show that vc −βRL = vb rπ + (β + 1)RE and ve RE = vb RE + [rπ /(β + 1)]
B
C 0003
ib
ib
r vb
0003 0002
PROBLEMS
D 1.61 It is required to design an amplifier to sense the open-circuit output voltage of a transducer and to provide a proportional current through a load resistor. The equivalent source resistance of the transducer is specified to vary in the range of 1 k0002 to 10 k0002. Also, the load resistance is known to vary in the range of 1 k0002 to 10 k0002. The change in the current supplied to the load corresponding to the specified change in Rs is to be 10% at most. Similarly, the change in load current corresponding to the specified change in RL is to be 10% at most. Also, for a nominal transducer open-circuit output voltage of 10 mV, the amplifier is required to provide a minimum of 1 mA current through the load. What type of amplifier is required? Sketch the amplifier circuit model, and specify values for its parameters. For Ri and Ro , specify values m in the form 1 × 10 0002.
CHAPTER 1
should be 10% at most. Also, for a nominal short-circuit output current of the transducer of 10 μA, the amplifier is required to provide a minimum of 1 mA through the load. What type of amplifier is required? Sketch the circuit model of the amplifier, and specify values for its parameters. Select appropriate values for Ri and Ro in the form m 1 × 10 0002.
RL
E
vc
0003 RE
ve 0002
0002
Figure P1.63
1.64 An amplifier with an input resistance of 5 k0002, when driven by a current source of 1 μA and a source resistance of 200 k0002, has a short-circuit output current of 5 mA and an open-circuit output voltage of 10 V. If the amplifier is used to drive a 2-k0002 load, give the values of the voltage gain, current gain, and power gain expressed as ratios and in decibels. 1.65 Figure P1.65(a) shows two transconductance amplifiers connected in a special configuration. Find v o in terms of v 1 and v 2 . Let gm = 100 mA/V and R = 5 k0002. If v 1 = v 2 = 1 V, find the value of v o . Also, find v o for the case v 1 = 1.01 V and v 2 = 0.99 V. (Note: This circuit is called a differential amplifier and is given the symbol shown
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
in Fig. P1.65(b). A particular type of differential amplifier known as an operational amplifier will be studied in Chapter 2.)
CHAPTER 1
PROBLEMS
54 Chapter 1 Signals and Amplifiers to that of the voltage amplifier in Fig. 1.16(a), identify corresponding currents and voltages as well as the correspondence between the parameters of the amplifier equivalent circuit and the g parameters. Hence give the g parameter that corresponds to each of Ri , Av o , and Ro . Notice that there is an additional g parameter with no correspondence in the amplifier equivalent circuit. Which one? What does it signify? What assumption did we make about the amplifier that resulted in the absence of this particular g parameter from the equivalent circuit in Fig. 1.16(a)?
I1
g22
0003
I2 0003
1 g11
V1
g12 I2
0002
g21V1
0003 0002
V2 0002
Figure P1.66
(a)
+
vo
–
(b) Figure P1.65
1.66 Any linear two-port network including linear amplifiers can be represented by one of four possible parameter sets, given in Appendix C. For the voltage amplifier, the most convenient representation is in terms of the g parameters. If the amplifier input port is labeled as port 1 and the output port as port 2, its g-parameter representation is described by the two equations:
Section 1.6: Frequency Response of Amplifiers 1.67 Use the voltage-divider rule to derive the transfer functions T (s) ≡ Vo (s)/Vi (s) of the circuits shown in Fig. 1.22, and show that the transfer functions are of the form given at the top of Table 1.2. 1.68 Figure P1.68 shows a signal source connected to the input of an amplifier. Here Rs is the source resistance, and Ri and Ci are the input resistance and input capacitance, respectively, of the amplifier. Derive an expression for Vi (s)/Vs (s), and show that it is of the low-pass STC type. Find the 3-dB frequency for the case Rs = 10 k0002, Ri = 40 k0002, and Ci = 5 pF.
Rs
I1 = g11 V1 + g12 I2 V2 = g21 V1 + g22 I2 Figure P1.66 shows an equivalent circuit representation of these two equations. By comparing this equivalent circuit
Vs
0003 0002
Ri
Figure P1.68
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Ci
0003 Vi 0002
Problems 55
0003 0002
| T | (dB)
∠ T (◦ )
0 100 1000 104 105
40 40
0 0
37 20 0
−45
C 0003
Vi
f (Hz)
PROBLEMS
R1
1.71 Measurement of the frequency response of an amplifier yields the data in the following table:
R2
Vo 0002
Provide plausible approximate values for the missing entries. Also, sketch and clearly label the magnitude frequency response (i.e., provide a Bode plot) for this amplifier. 1.72 Measurement of the frequency response of an amplifier yields the data in the following table:
Figure P1.69 f (Hz) | T | (dB)
D 1.70 It is required to couple a voltage source Vs with a resistance Rs to a load RL via a capacitor C. Derive an expression for the transfer function from source to load (i.e., Vl /Vs ), and show that it is of the high-pass STC type. For Rs = 5 k0002 and RL = 20 k0002, find the smallest coupling capacitor that will result in a 3-dB frequency no greater than 100 Hz.
Vi
0
10
102
103
20
37
40
104
105
106
107
37
20
0
Provide approximate plausible values for the missing table entries. Also, sketch and clearly label the magnitude frequency response (Bode plot) of this amplifier. 1.73 The unity-gain voltage amplifiers in the circuit of Fig. P1.73 have infinite input resistances and zero output
Vo
Figure P1.73
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CHAPTER 1
1.69 For the circuit shown in Fig. P1.69, find the transfer function T (s) = Vo (s)/Vi (s), and arrange it in the appropriate standard form from Table 1.2. Is this a high-pass or a low-pass network? What is its transmission at very high frequencies? [Estimate this directly, as well as by letting s → ∞ in your expression for T (s).] What is the corner frequency ω0 ? For R1 = 10 k0002, R2 = 40 k0002, and C = 1 μF, find f0 . What is the value of |T ( jωo )|?
PROBLEMS
resistances and thus function as perfect buffers. Furthermore, assume that their gain is frequency independent. Convince yourself that the overall gain Vo /Vi will drop by 3 dB below the value at dc at the frequency for which the gain of each RC circuit is 1.0 dB down. What is that frequency in terms of CR?
CHAPTER 1
56 Chapter 1 Signals and Amplifiers
1.74 A manufacturing error causes an internal node of a high-frequency amplifier whose Th´evenin-equivalent node resistance is 100 k0002 to be accidentally shunted to ground by a capacitor (i.e., the node is connected to ground through a capacitor). If the measured 3-dB bandwidth of the amplifier is reduced from the expected 5 MHz to 100 kHz, estimate the value of the shunting capacitor. If the original cutoff frequency can be attributed to a small parasitic capacitor at the same internal node (i.e., between the node and ground), what would you estimate it to be? D *1.75 A designer wishing to lower the overall upper 3-dB frequency of a three-stage amplifier to 10 kHz considers shunting one of two nodes: Node A, between the output of the first stage and the input of the second stage, and Node B, between the output of the second stage and the input of the third stage, to ground with a small capacitor. While measuring the overall frequency response of the amplifier, she connects a capacitor of 1 nF, first to node A and then to node B, lowering the 3-dB frequency from 3 MHz to 200 kHz and 20 kHz, respectively. If she knows that each amplifier stage has an input resistance of 100 k0002, what output resistance must the driving stage have at node A? At node B? What capacitor value should she connect to which node to solve her design problem most economically?
D 1.76 An amplifier with an input resistance of 100 k0002 and an output resistance of 1 k0002 is to be capacitor-coupled to a 10-k0002 source and a 1-k0002 load. Available capacitors −n have values only of the form 1 × 10 F. What are the values of the smallest capacitors needed to ensure that the corner frequency associated with each is less than 100 Hz? What actual corner frequencies result? For the situation in which the basic amplifier has an open-circuit voltage gain (Av o ) of 100 V/V, find an expression for T (s) = Vo (s)/Vs (s). *1.77 A voltage amplifier has the transfer function 1000 00050007 2 f 10 1+j 5 1+ 10 jf
Av = 0004
Using the Bode plots for low-pass and high-pass STC networks (Figs. 1.23 and 1.24), sketch a Bode plot for |Av |. Give approximate values for the gain magnitude at f = 10 Hz, 2 3 4 5 6 7 8 10 Hz, 10 Hz, 10 Hz, 10 Hz, 10 Hz, 10 Hz, and 10 Hz. Find the bandwidth of the amplifier (defined as the frequency range over which the gain remains within 3 dB of the maximum value). *1.78 For the circuit shown in Fig. P1.78, first evaluate Ti (s) = Vi (s)/Vs (s) and the corresponding cutoff (corner) frequency. Second, evaluate To (s) = Vo (s)/Vi (s) and the corresponding cutoff frequency. Put each of the transfer functions in the standard form (see Table 1.2), and combine them to form the overall transfer function, T (s) = Ti (s) × To (s). Provide a Bode magnitude plot for |T ( jω)|. What is the bandwidth between 3-dB cutoff points?
C2 100 nF
R1 100 k0004
0003
0003 Vs
0003 0002
C1 10 pF
Vi 0002
GmVi
R2 100 k0004
R3 10 k0004
Vo 0002
Gm 0005 100 mA000bV Figure P1.78
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Problems 57
Show that these constraints can be met by selecting 0005 0004 100 − 1 Rs Ri ≥ x 1 Ro ≤ 2πf3 dB CL − (1/RL ) A /[1 − (x/100)] Gm ≥ 0 (RL Ro ) Find Ri , Ro , and Gm for Rs = 10 k0002, x = 10%, A0 = 100 V/V, RL = 10 k0002, CL = 20 pF, and f3 dB = 2 MHz. *1.80 Use the voltage-divider rule to find the transfer function Vo (s)/Vi (s) of the circuit in Fig. P1.80. Show that the transfer function can be made independent of frequency if the condition C1 R1 = C2 R2 applies. Under this condition
Vi
R1
C1
R2
0003 C2 Vo 0002
0003 0002
Figure P1.80
*1.81 An amplifier with a frequency response of the type shown in Fig. 1.21 is specified to have a phase shift of magnitude no greater than 5.7° over the amplifier bandwidth, which extends from 100 Hz to 1 kHz. It has been found that the gain falloff at the low-frequency end is determined by the response of a high-pass STC circuit and that at the high-frequency end it is determined by a low-pass STC circuit. What do you expect the corner frequencies of these two circuits to be? What is the drop in gain in decibels (relative to the maximum gain) at the two frequencies that define the amplifier bandwidth? What are the frequencies at which the drop in gain is 3 dB? (Hint: Refer to Figs. 1.23 and 1.24.)
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PROBLEMS
(a) At most, x% of the input signal is lost in coupling the signal source to the amplifier (i.e., Vi ≥ [1 − (x/100)]Vs ). (b) The 3-dB frequency of the amplifier is equal to or greater than a specified value f3 dB . (c) The dc gain Vo /Vs is equal to or greater than a specified value A0 .
the circuit is called a compensated attenuator and is frequently employed in the design of oscilloscope probes. Find the transmission of the compensated attenuator in terms of R1 and R2 .
CHAPTER 1
D **1.79 A transconductance amplifier having the equivalent circuit shown in Table 1.1 is fed with a voltage source Vs having a source resistance Rs , and its output is connected to a load consisting of a resistance RL in parallel with a capacitance CL . For given values of Rs , RL , and CL , it is required to specify the values of the amplifier parameters Ri , Gm , and Ro to meet the following design constraints:
116 Chapter 2 Operational Amplifiers input bias current, IB . In a closed-loop amplifier, IB gives rise to a dc offset voltage at the output of magnitude IB R2 . This voltage can be reduced to IOS R2 by connecting a resistance in series with the positive input terminal equal to the total dc resistance seen by the negative input terminal. IOS is the input offset current; that is, IOS = |IB1 − IB2 |.
follower, frequently employed as a buffer amplifier to connect a high-resistance source to a low-resistance load. 0002
The difference amplifier of Fig. 2.16 is designed with R4 /R3 = R2 /R1 , resulting in v O = (R2 /R1 )(v I2 − v I1 ).
0002
The instrumentation amplifier of Fig. 2.20(b) is a very popular circuit. It provides v O = (1 + R2 /R1 )(R4 /R3 ) (v I2 − v I1 ). It is usually designed with R3 = R4 , and R1 and R2 selected to provide the required gain. If an adjustable gain is needed, part of R1 can be made variable.
0002
The inverting Miller integrator of Fig. 2.24(a) is a popular circuit, frequently employed in analog signal-processing functions such as filters (Chapter 17) and oscillators (Chapter 18).
0002
The input offset voltage, VOS , is the magnitude of dc voltage that when applied between the op-amp input terminals, with appropriate polarity, reduces the dc offset voltage at the output to zero.
0002
The effect of VOS on performance can be evaluated by including in the analysis a dc source VOS in series with the op-amp positive input lead. For both the inverting and the noninverting configurations, VOS results in a dc offset voltage at the output of VOS (1 + R2 /R1 ).
0002
Capacitively coupling an op amp reduces the dc offset voltage at the output considerably.
0002
The average of the two dc currents, IB1 and IB2 , that flow in the input terminals of the op amp, is called the
0002
Connecting a large resistance in parallel with the capacitor of an op-amp inverting integrator prevents op-amp saturation (due to the effect of VOS and IB ).
0002
For most internally compensated op amps, the open-loop gain falls off with frequency at a rate of −20 dB/decade, reaching unity at a frequency ft (the unity-gain bandwidth). Frequency ft is also known as the gain–bandwidth product of the op amp: ft = A0 fb , where A0 is the dc gain, and fb is the 3-dB frequency of the open-loop gain. At any frequency f (f 0006 fb ), the op-amp gain |A| 0002 ft /f .
0002
For both the inverting and the noninverting closedloop configurations, the 3-dB frequency is equal to ft /(1 + R2 /R1 ).
0002
The maximum rate at which the op-amp output voltage can change is called the slew rate. The slew rate, SR, is usually specified in V/μs. Op-amp slewing can result in nonlinear distortion of output signal waveforms.
0002
The full-power bandwidth, fM , is the maximum frequency at which an output sinusoid with an amplitude equal to the op-amp rated output voltage (Vo max ) can be produced without distortion: fM = SR/2π Vo max .
PROBLEMS Computer Simulation Problems Problems identified by the Multisim/PSpice icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion. Instructions to assist in setting up PSPice and Multisim simulations for all the indicated problems can be found in the corresponding files on the website. Note that if a particular parameter value is not specified
in the problem statement, you are to make a reasonable assumption.
Section 2.1: The Ideal Op Amp 2.1 What is the minimum number of pins required for a so-called dual-op-amp IC package, one containing two op amps? What is the number of pins required for a so-called quad-op-amp package, one containing four op-amps?
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Problems 117
For equal transconductances Gm and a transresistance Rm , find an expression for the open-loop gain A. For Gm = 40 mA/V 6 and Rm = 1 × 10 0002, what value of A results?
2.7 Nonideal (i.e., real) operational amplifiers respond to both the differential and common-mode components of their input signals (refer to Fig. 2.4 for signal representation). Thus the output voltage of the op amp can be expressed as
Figure P2.2
2.3 Measurement of a circuit incorporating what is thought to be an ideal op amp shows the voltage at the op-amp output to be −2.000 V and that at the negative input to be −1.000 V. For the amplifier to be ideal, what would you expect the voltage at the positive input to be? If the measured voltage at the positive input is −1.005 V, what is likely to be the actual gain of the amplifier? 2.4 A set of experiments is run on an op amp that is ideal except for having a finite gain A. The results are tabulated below. Are the results consistent? If not, are they reasonable, in view of the possibility of experimental error? What do they show the gain to be? Using this value, predict values of the measurements that were accidentally omitted (the blank entries). Experiment #
v1
v2
vO
1 2 3 4 5 6 7
0.00 1.00
0.00 1.00 1.00 1.10 2.00 2.00
0.00 0.00 1.00 10.1 −0.99 1.00 −5.10
1.00 2.01 1.99 5.10
2.5 Refer to Exercise 2.3. This problem explores an alternative internal structure for the op amp. In particular, we wish to model the internal structure of a particular op amp using two transconductance amplifiers and one transresistance amplifier. Suggest an appropriate topology.
v O = Ad v Id + Acm v Icm where Ad is the differential gain (referred to simply as A in the text) and Acm is the common-mode gain (assumed to be zero in the text). The op amp’s effectiveness in rejecting common-mode signals is measured by its CMRR, defined as Ad CMRR = 20 log Acm Consider an op amp whose internal structure is of the type shown in Fig. E2.3 except for a mismatch 0006Gm between the transconductances of the two channels; that is, Gm1 = Gm − 21 0006Gm Gm2 = Gm + 21 0006Gm Find expressions for Ad , Acm , and CMRR. What is the maximum permitted percentage mismatch between the two Gm values if a minimum CMRR of 60 dB is required?
Section 2.2: The Inverting Configuration 2.8 Assuming ideal op amps, find the voltage gain v o /v i and input resistance Rin of each of the circuits in Fig. P2.8. 2.9 A particular inverting circuit uses an ideal op amp and two 10-k0002 resistors. What closed-loop gain would you expect? If a dc voltage of +1.00 V is applied at the input, what outputs result? If the 10-k0002 resistors are said to be “1% resistors,” having values somewhere in the range (1 ± 0.01) times the nominal value, what range of outputs would you expect to actually measure for an input of precisely 1.00 V?
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PROBLEMS
2.6 The two wires leading from the output terminals of a transducer pick up an interference signal that is a 60-Hz, 2-V sinusoid. The output signal of the transducer is sinusoidal of 5-mV amplitude and 1000-Hz frequency. Give expressions for v cm , v d , and the total signal between each wire and the system ground.
CHAPTER 2
2.2 The circuit of Fig. P2.2 uses an op amp that is ideal except for having a finite gain A. Measurements indicate v O = 4.0 V when v I = 1.0 V. What is the op-amp gain A?
PROBLEMS
118 Chapter 2 Operational Amplifiers
20 k0006
0002
20 k0006 0002
0003
0003
CHAPTER 2
20 k0006
(a)
20 k0006 0002 20 k0006
(b)
20 k0006 0002
0003
0003 20 k0006
(c)
(d)
Figure P2.8
2.10 You are provided with an ideal op amp and three 10-k0002 resistors. Using series and parallel resistor combinations, how many different inverting-amplifier circuit topologies are possible? What is the largest (noninfinite) available voltage gain magnitude? What is the smallest (nonzero) available gain magnitude? What are the input resistances in these two cases? 2.11 For ideal op amps operating with the following feedback networks in the inverting configuration, what closed-loop gain results? (a) (b) (c) (d) (e)
R1 = 10 k0002, R2 = 10 k0002 R1 = 10 k0002, R2 = 100 k0002 R1 = 10 k0002, R2 = 1 k0002 R1 = 100 k0002, R2 = 10 M0002 R1 = 100 k0002, R2 = 1 M0002
D 2.12 Given an ideal op amp, what are the values of the resistors R1 and R2 to be used to design amplifiers with the closed-loop gains listed below? In your designs, use at least one 10-k0002 resistor and another equal or larger resistor. (a) −1 V/V (b) −2 V/V
(c) −5 V/V (d) −100 V/V D 2.13 Design an inverting op-amp circuit for which the gain is −10 V/V and the total resistance used is 110 k0002. D 2.14 Using the circuit of Fig. 2.5 and assuming an ideal op amp, design an inverting amplifier with a gain of 46 dB having the largest possible input resistance under the constraint of having to use resistors no larger than 1 M0002. What is the input resistance of your design? 2.15 An ideal op amp is connected as shown in Fig. 2.5 with R1 = 10 k0002 and R2 = 100 k0002. A symmetrical square-wave signal with levels of 0 V and −1 V is applied at the input. Sketch and clearly label the waveform of the resulting output voltage. What is its average value? What is its highest value? What is its lowest value? 2.16 For the circuit in Fig. P2.16, assuming an ideal op amp, find the currents through all branches and the voltages at all nodes. Since the current supplied by the op amp is greater than the current drawn from the input signal source, where does the additional current come from?
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Problems 119
1 k0006 00021 V 0003 0002
0002
2.22 The circuit in Fig. P2.22 is frequently used to provide an output voltage v o proportional to an input signal current ii .
0003
CHAPTER 2
voltage ranges from −10 V to +10 V, what is the maximum voltage by which the “virtual ground node” departs from its ideal value?
10 k0006
2 k0006
2.17 An inverting op-amp circuit is fabricated with the resistors R1 and R2 having x% tolerance (i.e., the value of each resistance can deviate from the nominal value by as much as ±x%). What is the tolerance on the realized closed-loop gain? Assume the op amp to be ideal. If the nominal closed-loop gain is −100 V/V and x = 1, what is the range of gain values expected from such a circuit? 2.18 An ideal op amp with 5-k0002 and 15-k0002 resistors is used to create a +5-V supply from a −15-V reference. Sketch the circuit. What are the voltages at the ends of the 5-k0002 resistor? If these resistors are so-called 1% resistors, whose actual values are the range bounded by the nominal value ±1%, what are the limits of the output voltage produced? If the −15-V supply can also vary by ±1%, what is the range of the output voltages that might be found? 2.19 An inverting op-amp circuit for which the required gain is −50 V/V uses an op amp whose open-loop gain is only 500 V/V. If the larger resistor used is 100 k0002, to what must the smaller be adjusted? With what resistor must a 2-k0002 resistor connected to the input be shunted to achieve this goal? (Note that a resistor Ra is said to be shunted by resistor Rb when Rb is placed in parallel with Ra .) D 2.20 (a) Design an inverting amplifier with a closed-loop gain of −200 V/V and an input resistance of 1 k0002. (b) If the op amp is known to have an open-loop gain of 5000 V/V, what do you expect the closed-loop gain of your circuit to be (assuming the resistors have precise values)? (c) Give the value of a resistor you can place in parallel (shunt) with R1 to restore the closed-loop gain to its nominal value. Use the closest standard 1% resistor value (see Appendix J). 2.21 An op amp with an open-loop gain of 5000 V/V is used in the inverting configuration. If in this application the output
0003 vi 0002
PROBLEMS
Figure P2.16
vo
Figure P2.22
Derive expressions for the transresistance Rm ≡ v o /ii and the input resistance Ri ≡ v i /ii for the following cases: (a) A is infinite. (b) A is finite. 2.23 Show that for the inverting amplifier if the op-amp gain is A, the input resistance is given by Rin = R1 +
R2 A+1
2.24 For an inverting amplifier with nominal closed-loop gain R2 /R1 , find the minimum value that the op-amp open-loop gain A must have (in terms of R2 /R1 ) so that the gain error (due to the finite A) is limited to 0.1%, 1%, and 10%. In each case find the value of a resistor RIa such that when it is placed in shunt with R1 , the gain is restored to its nominal value. *2.25 Figure P2.25 shows an op amp that is ideal except for having a finite open-loop gain and is used to realize an inverting amplifier whose gain has a nominal magnitude G = R2 /R1 . To compensate for the gain reduction due to
Rc
R2 0002
Vi R1
0003
Figure P2.25
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Vo
PROBLEMS
the finite A, a resistor Rc is shunted across R1 . Show that perfect compensation is achieved when Rc is selected according to
D 2.29 An inverting op-amp circuit using an ideal op amp must be designed to have a gain of −500 V/V using resistors no larger than 100 k0002.
A−G Rc = R1 1+G
CHAPTER 2
120 Chapter 2 Operational Amplifiers
D *2.26 (a) Use Eq. (2.5) to obtain the amplifier open-loop gain A required to realize a specified closed-loop gain (Gnominal = −R2 /R1 ) within a specified gain error e, G − Gnominal e ≡ Gnominal
(a) For the simple two-resistor circuit, what input resistance would result? (b) If the circuit in Fig. 2.8 is used with three resistors of maximum value, what input resistance results? What is the value of the smallest resistor needed? 2.30 The inverting circuit with the T network in the feedback is redrawn in Fig. P2.30 in a way that emphasizes the observation that R2 and R3 in effect are in parallel (because the ideal op amp forces a virtual ground at the inverting input terminal). Use this observation to derive an expression for the gain (v O /v I ) by first finding (v X /v I ) and (v O /v X ). For the latter use the voltage-divider rule applied to R4 and (R2 R3 ).
(b) Design an inverting amplifer for a nominal closed-loop gain of −100, an input resistance of 1 k0002, and a gain error of ≤10%. Specify R1 , R2 , and the minimum A required. *2.27 (a) Use Eq. (2.5) to show that a reduction 0006A in the op-amp gain A gives rise to a reduction 0006|G| in the magnitude of the closed-loop gain G with 0006|G| and 0006A related by
R2
0006|G|/|G| 1 + R2 /R1 0002 0006A/A A 0003 0002 0006A R 0005 1. Assume that 1 + 2 0005 A and R1 A (b) If in a closed-loop amplifier with a nominal gain (i.e., R2 /R1 ) of 100, A decreases by 10%, what is the minimum nominal A required to limit the percentage change in | G | to 0.1%?
R4
R3
vI
iI 0002
0V
R1
2.28 Consider the circuit in Fig. 2.8 with R1 = R2 = R4 = 1 M0002, and assume the op amp to be ideal. Find values for R3 to obtain the following gains:
0003
vO
Figure P2.30
*2.31 The circuit in Fig. P2.31 can be considered to be an extension of the circuit in Fig. 2.8.
(a) −100 V/V (b) −10 V/V (c) −2 V/V
(a) Find the resistances looking into node 1, R1 ; node 2, R2 ; node 3, R3 ; and node 4, R4 .
R
I
R/2
1
R1
R I1
0V
vX
R/2
2
R2
R I2
R/2
3
R3
R I3
4
R4 I4
2 1 Ideal
Figure P2.31
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Problems 121
10 kV
iL
CHAPTER 2
(b) Find the currents I1 , I2 , I3 , and I4 , in terms of the input current I. (c) Find the voltages at nodes 1, 2, 3, and 4, that is, V1 , V2 , V3 , and V4 in terms of (IR).
RL
R iI 2
(a) Find I1 , I2 , I3 , IL , and Vx . (b) If VO is not to be lower than −13 V, find the maximum allowed value for RL . (c) If RL is varied in the range 100 0002 to 1 k0002, what is the corresponding change in IL and in VO ?
1
I2
10 kV
I3 I1
10 kV
RL
Figure P2.34
D 2.35 Design the circuit shown in Fig. P2.35 to have an input resistance of 100 k0002 and a gain that can be varied from −1 V/V to −100 V/V using the 100-k0002 potentiometer R4 . What voltage gain results when the potentiometer is set exactly at its middle value?
IL
100 V
2 1
1V
VX
vO
PROBLEMS
2.32 The circuit in Fig. P2.32 utilizes an ideal op amp.
R3
VO
R2
R4
Figure P2.32
D 2.33 Use the circuit in Fig. P2.32 as an inspiration to design a circuit that supplies a constant current IL of 3.1 mA to a variable resistance RL . Assume the availability of a 1.5-V battery and design so that the current drawn from the battery is 0.1 mA. For the smallest resistance in the circuit, use 500 0002. If the op amp saturates at ±10 V, what is the maximum value that RL can have while the current source supplying it operates properly? D 2.34 Assuming the op amp to be ideal, it is required to design the circuit shown in Fig. P2.34 to implement a current amplifier with gain iL /iI = 11 A/A. (a) Find the required value for R. (b) What are the input and the output resistance of this current amplifier? (c) If RL = 1 k0002 and the op amp operates in an ideal manner as long as v O is in the range ±12 V, what range of iI is possible? (d) If the amplifier is fed with a current source having a current of 0.2 mA and a source resistance of 10 k0002, find iL .
vI
R1
2 1
vO
Figure P2.35
2.36 A weighted summer circuit using an ideal op amp has three inputs using 10-k0002 resistors and a feedback resistor of 50 k0002. A signal v 1 is connected to two of the inputs while a signal v 2 is connected to the third. Express v O in terms of v 1 and v 2 . If v 1 = 1 V and v 2 = −1 V, what is v O ? D 2.37 Design an op-amp circuit to provide an output v O = −[2v 1 + (v 2 /2)]. Choose relatively low values of resistors but ones for which the input current (from each input signal source) does not exceed 50 μA for 1-V input signals. D 2.38 Use the scheme illustrated in Fig. 2.10 to design an op-amp circuit with inputs v 1 , v 2 , and v 3 , whose output is
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CHAPTER 2
PROBLEMS
122 Chapter 2 Operational Amplifiers v O = −(2v 1 + 4v 2 + 8v 3 ) using small resistors but no smaller than 1 k0002. D 2.39 An ideal op amp is connected in the weighted summer configuration of Fig. 2.10. The feedback resistor Rf = 100 k0002, and six 100-k0002 resistors are connected to the inverting input terminal of the op amp. Show, by sketching the various circuit configurations, how this basic circuit can be used to implement the following functions: (a) (b) (c) (d)
power supply. Show that v O is given by vO = −
Rf 0 1 2 3 [2 a0 + 2 a1 + 2 a2 + 2 a3 ] 16
where Rf is in kilohms. Find the value of Rf so that v O ranges from 0 to −12 volts.
v O = –(v 1 + 2v 2 + 3v 3 ) v O = –(v 1 + v 2 + 2v 3 + 2v 4 ) v O = –(v 1 + 5v 2 ) v O = –6v 1
In each case find the input resistance seen by each of the signal sources supplying v 1 , v 2 , v 3 , and v 4 . Suggest at least two additional summing functions that you can realize with this circuit. How would you realize a summing coefficient that is 0.5? D 2.40 Give a circuit, complete with component values, for a weighted summer that shifts the dc level of a sine-wave signal of 3 sin(ωt) V from zero to −3 V. Assume that in addition to the sine-wave signal you have a dc reference voltage of 1.5 V available. Sketch the output signal waveform. D 2.41 Use two ideal op amps and resistors to implement the summing function v O = v 1 + 2v 2 – 3v 3 – 5v 4 D 2.42 In an instrumentation system, there is a need to take the difference between two signals, one of v 1 = 2 sin(2π × 60t) + 0.01 sin(2π × 1000t) volts and another of v 2 = 2 sin(2π × 60t) − 0.01 sin(2π × 1000t) volts. Draw a circuit that finds the required difference using two op amps and mainly 100-k0002 resistors. Since it is desirable to amplify the 1000-Hz component in the process, arrange to provide an overall gain of 100 as well. The op amps available are ideal except that their output voltage swing is limited to ±10 V. *2.43 Figure P2.43 shows a circuit for a digital-to-analog converter (DAC). The circuit accepts a 4-bit input binary word a3 a2 a1 a0 , where a0 , a1 , a2 , and a3 take the values of 0 or 1, and it provides an analog output voltage v O proportional to the value of the digital input. Each of the bits of the input word controls the correspondingly numbered switch. For instance, if a2 is 0 then switch S2 connects the 20-k0002 resistor to ground, while if a2 is 1 then S2 connects the 20-k0002 resistor to the +5-V
Figure P2.43
Section 2.3: The Noninverting Configuration D 2.44 Given an ideal op amp to implement designs for the following closed-loop gains, what values of resistors (R1 , R2 ) should be used? Where possible, use at least one 10-k0002 resistor as the smallest resistor in your design. (a) (b) (c) (d)
+1 V/V +2 V/V +21 V/V +100 V/V
D 2.45 Design a circuit based on the topology of the noninverting amplifier to obtain a gain of +1.5 V/V, using only 10-k0002 resistors. Note that there are two possibilities. Which of these can be easily converted to have a gain of
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Problems 123
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either +1.0 V/V or +2.0 V/V simply by short-circuiting a single resistor in each case?
PROBLEMS
D 2.46 Figure P2.46 shows a circuit for an analog voltmeter of very high input resistance that uses an inexpensive moving-coil meter. The voltmeter measures the voltage V applied between the op amp’s positive-input terminal and ground. Assuming that the moving coil produces full-scale deflection when the current passing through it is 100 μA, find the value of R such that a full-scale reading is obtained when V is +10 V. Does the meter resistance shown affect the voltmeter calibration?
RP0
Figure P2.47
D *2.48 Design a circuit, using one ideal op amp, whose output is v O = v I1 + 2v I2 − 9v I3 + 4v I4 . (Hint: Use a structure similar to that shown in general form in Fig. P2.47.)
V
2.49 Derive an expression for the voltage gain, v O /v I , of the circuit in Fig. P2.49.
Figure P2.46
R2 R1
0002
D *2.47 (a) Use superposition to show that the output of the circuit in Fig. P2.47 is given by 0004
vO =
0005 Rf Rf Rf v N1 + v N2 + · · · + v Nn RN1 R RNn 00050004N2 0005 0004 Rf RP R RP v P1 + v P2 + · · · + P v Pn + 1+ RN RP1 RP2 RPn
where RN = RN1 RN2 · · · RNn , and RP = RP1 RP2 · · · RPn RP0 (b) Design a circuit to obtain v O = –4v N1 + v P1 + 3v P2 The smallest resistor used should be 10 k0002.
0003 vI
0003
R3 R4
0002
0003 vO 0002
Figure P2.49
2.50 For the circuit in Fig. P2.50, use superposition to find v O in terms of the input voltages v 1 and v 2 . Assume an ideal op amp. For v 1 = 10 sin(2π × 60t) − 0.1 sin(2π × 1000t), volts v 2 = 10 sin(2π × 60t) + 0.1 sin(2π × 1000t), volts find v O .
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PROBLEMS
124 Chapter 2 Operational Amplifiers
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10R
10R
In each case find the load current and the current supplied by the source. Where does the load current come from in case (b)? 2.54 Derive an expression for the gain of the voltage follower of Fig. 2.14, assuming the op amp to be ideal except for having a finite gain A. Calculate the value of the closed-loop gain for A = 1000, 100, and 10. In each case find the percentage error in gain magnitude from the nominal value of unity. 2.55 Complete the following table for feedback amplifiers created using one ideal op amp. Note that Rin signifies input resistance and R1 and R2 are feedback-network resistors as labeled in the inverting and noninverting configurations.
Figure P2.50
D 2.51 The circuit shown in Fig. P2.51 utilizes a 10-k0002 potentiometer to realize an adjustable-gain amplifier. Derive an expression for the gain as a function of the potentiometer setting x. Assume the op amp to be ideal. What is the range of gains obtained? Show how to add a fixed resistor so that the gain range can be 1 to 11 V/V. What should the resistor value be?
Case
Gain
Rin
a b c d e f g
−10 V/V −1 V/V −2 V/V +1 V/V +2 V/V +11 V/V −0.5 V/V
10 k0002
R1
R2
100 k0002 200 k0002 ∞ 100 k0002 100 k0002 20 k0002
D 2.56 A noninverting op-amp circuit with nominal gain of 10 V/V uses an op amp with open-loop gain of 100 V/V and a lowest-value resistor of 10 k0002. What closed-loop gain actually results? With what value resistor can which resistor be shunted to achieve the nominal gain? If in the manufacturing process, an op amp of gain 200 V/V were used, what closed-loop gain would result in each case (the uncompensated one, and the compensated one)? Figure P2.51
D 2.52 Given the availability of resistors of value 1 k0002 and 10 k0002 only, design a circuit based on the noninverting configuration to realize a gain of +10 V/V. What is the input resistance of your amplifier? 2.53 It is required to connect a 10-V source with a source resistance of 1 M0002 to a 1-k0002 load. Find the voltage that will appear across the load if: (a) The source is connected directly to the load. (b) A unity-gain op-amp buffer is inserted between the source and the load.
2.57 Use Eq. (2.11) to show that if the reduction in the closed-loop gain G from the nominal value G0 = 1 + R2 /R1 is to be kept less than x% of G0 , then the open-loop gain of the op amp must exceed G0 by at least a factor F = (100/x) − 1 0002 100/x. Find the required F for x = 0.01, 0.1, 1, and 10. Utilize these results to find for each value of x the minimum required open-loop gain to obtain closed-loop gains of 1, 10, 102 , 103 , and 104 V/V. 2.58 For each of the following combinations of op-amp open-loop gain A and nominal closed-loop gain G0 , calculate the actual closed-loop gain G that is achieved. Also, calculate the percentage by which |G| falls short of the nominal gain magnitude |G0 |.
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Problems 125
A (V/V)
a b c d e f g
−1 +1 −1 +10 −10 −10 +1
10 10 100 10 100 1000 2
(a) (b) (c) (d)
1 V/V 5 V/V 100 V/V 0.5 V/V
2.62 For the circuit shown in Fig. P2.62, express v O as a function of v 1 and v 2 . What is the input resistance seen by v 1 alone? By v 2 alone? By a source connected between the two input terminals? By a source connected to both input terminals simultaneously?
2.59 Figure P2.59 shows a circuit that provides an output voltage v O whose value can be varied by turning the wiper of the 100-k0002 potentiometer. Find the range over which v O can be varied. If the potentiometer is a “20-turn” device, find the change in v O corresponding to each turn of the pot.
25 Figure P2.62
2.63 Consider the difference amplifier of Fig. 2.16 with the two input terminals connected together to an input common-mode signal source. For R2 /R1 = R4 /R3 , show that the input common-mode resistance is (R3 + R4 ) (R1 + R2 ).
25
Figure P2.59
Section 2.4: Difference Amplifiers 2.60 Find the voltage gain v O /v Id for the difference amplifier of Fig. 2.16 for the case R1 = R3 = 5 k0002 and R2 = R4 = 100 k0002. What is the differential input resistance Rid ? If the two key resistance ratios (R2 /R1 ) and (R4 /R3 ) are different from each other by 1%, what do you expect the common-mode gain Acm to be? Also, find the CMRR in this case. Neglect the effect of the ratio mismatch on the value of Ad . D 2.61 Using the difference amplifier configuration of Fig. 2.16 and assuming an ideal op amp, design the circuit to provide the following differential gains. In each case, the differential input resistance should be 20 k0002.
2.64 Consider the circuit of Fig. 2.16, and let each of the v I1 and v I2 signal sources have a series resistance Rs . What condition must apply in addition to the condition in Eq. (2.15) in order for the amplifier to function as an ideal difference amplifier? *2.65 For the difference amplifier shown in Fig. P2.62, let all the resistors be 10 k0002 ± x%. Find an expression for the worst-case common-mode gain that results. Evaluate this for x = 0.1, 1, and 5. Also, evaluate the resulting CMRR in each case. Neglect the effect of resistor tolerances on Ad . 2.66 For the difference amplifier of Fig. 2.16, show that if each resistor has a tolerance of ±100 e% (i.e., for, say, a 5% resistor, e = 0.05) then the worst-case CMRR is given approximately by 0004 CMRR 0002 20 log
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K +1 4e
0005
PROBLEMS
G0 (V/V)
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Case
PROBLEMS
where K is the nominal (ideal) value of the ratios (R2 /R1 ) and (R4 /R3 ). Calculate the value of worst-case CMRR for an amplifier designed to have a differential gain of ideally 100 V/V, assuming that the op amp is ideal and that 1% resistors are used. What resistor tolerance is needed if a CMRR of 80 dB is required?
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126 Chapter 2 Operational Amplifiers
D *2.67 Design the difference amplifier circuit of Fig. 2.16 to realize a differential gain of 1000, a differential input resistance of 2 k0002, and a minimum CMRR of 88 dB. Assume the op amp to be ideal. Specify both the resistor values and their required tolerance (e.g., better than x%). *2.68 (a) Find Ad and Acm for the difference amplifier circuit shown in Fig. P2.68. (b) If the op amp is specified to operate properly as long as the common-mode voltage at its positive and negative inputs falls in the range ±2.5 V, what is the corresponding limitation on the range of the input common-mode signal v Icm ? (This is known as the common-mode range of the differential amplifier.) (c) The circuit is modified by connecting a 10-k0002 resistor between node A and ground, and another 10-k0002 resistor between node B and ground. What will now be the values of Ad , Acm , and the input common-mode range?
100 k0006
vI1
100 k0006
0002
A
vI2 100 k0006
B
0003
vO
β 0002 R6 |(R5 + R6 ). Show that the differential gain is given by Ad ≡
vO 1 = v Id 1−β
(Hint: Use superposition.) Design the circuit to obtain a differential gain of 10 V/V and differential input resistance of 2 M0002. Select values for R, R5 , and R6 , such that (R5 + R6 ) ≤ R/100.
v1
R
R
0002 0002
vId
vO
0003 v2
R5
0003
bvO R
R R6
Figure P2.69
*2.70 Figure P2.70 shows a modified version of the difference amplifier. The modified circuit includes a resistor RG , which can be used to vary the gain. Show that the differential voltage gain is given by 0004 0005 vO R R = −2 2 1 + 2 v Id R1 RG
100 k0006
(Hint: The virtual short circuit at the op-amp input causes the current through the R1 resistors to be v Id /2R1 ). Figure P2.68
D *2.69 To obtain a high-gain, high-input-resistance difference amplifier, the circuit in Fig. P2.69 employs positive feedback, in addition to the negative feedback provided by the resistor R connected from the output to the negative input of the op amp. Specifically, a voltage divider (R5 , R6 ) connected across the output feeds a fraction β of the output, that is, a voltage βv O , back to the positive-input terminal of the op amp through a resistor R. Assume that R5 and R6 are much smaller than R so that the current through R is much lower than the current in the voltage divider, with the result that
vId
Figure P2.70
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Problems 127
Avoid leaving a terminal open-circuited, for such a terminal may act as an “antenna,” picking up interference and noise through capacitive coupling. Rather, find a convenient node to connect such a terminal in a redundant way. When more than one circuit implementation is possible, comment on the relative merits of each, taking into account such considerations as dependence on component matching and input resistance.
25 k0006
25 k0006
A
C 0002 0003
*2.75 For an instrumentation amplifier of the type shown in Fig. 2.20(b), a designer proposes to make R2 = R3 = R4 = 100 k0002, and 2R1 = 10 k0002. For ideal components, what difference-mode gain, common-mode gain, and CMRR result? Reevaluate the worst-case values for these for the situation in which all resistors are specified as ±1% units. Repeat the latter analysis for the case in which 2R1 is reduced to 1 k0002. What do you conclude about the effect of the gain of the first stage on CMRR? (Hint: Eq. (2.19) can be used to evaluate Acm of the second stage.) D 2.76 Design the instrumentation-amplifier circuit of Fig. 2.20(b) to realize a differential gain, variable in the range 2 to 100, utilizing a 100-k0002 pot as variable resistor. *2.77 The circuit shown in Fig. P2.77 is intended to supply a voltage to floating loads (those for which both terminals are ungrounded) while making greatest possible use of the available power supply.
O 20 k0006 D
B 25 k0006
25 k0006
Figure P2.71
2.72 Consider the instrumentation amplifier of Fig. 2.20(b) with a common-mode input voltage of +3 V (dc) and a differential input signal of 100-mV peak sine wave. Let 2R1 = 2 k0002, R2 = 50 k0002, R3 = R4 = 10 k0002. Find the voltage at every node in the circuit. 2.73 (a) Consider the instrumentation amplifier circuit of Fig. 2.20(a). If the op amps are ideal except that their outputs saturate at ±12 V, in the manner shown in Fig. 1.14, find the maximum allowed input common-mode signal for the case R1 = 1 k0002 and R2 = 100 k0002. (b) Repeat (a) for the circuit in Fig. 2.20(b), and comment on the difference between the two circuits.
30 k0006
Figure P2.77
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PROBLEMS
(a) Show how the circuit can be used to implement a difference amplifier of unity gain. (b) Show how the circuit can be used to implement single-ended amplifiers with gains: (i) −1 V/V (ii) +1 V/V (iii) +2 V/V (iv) +1/2 V/V
2.74 (a) Expressing v I1 and v I2 in terms of differential and common-mode components, find v O1 and v O2 in the circuit in Fig. 2.20(a) and hence find their differential component v O2 − v O1 and their common-mode component 21 (v O1 + v O2 ). Now find the differential gain and the common-mode gain of the first stage of this instrumentation amplifier and hence the CMRR. (b) Repeat for the circuit in Fig. 2.20(b), and comment on the difference between the two circuits.
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D *2.71 The circuit shown in Fig. P2.71 is a representation of a versatile, commercially available IC, the INA105, manufactured by Burr-Brown and known as a differential amplifier module. It consists of an op amp and precision, laser-trimmed, metal-film resistors. The circuit can be configured for a variety of applications by the appropriate connection of terminals A, B, C, D, and O.
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PROBLEMS
128 Chapter 2 Operational Amplifiers (c) If the frequency is lowered by a factor of 10 from that found in (a), by what factor does the output voltage change, and in what direction (smaller or larger)? (d) What is the phase relation between the input and output in situation (c)?
(a) Assuming ideal op amps, sketch the voltage waveforms at nodes B and C for a 1-V peak-to-peak sine wave applied at A. Also sketch v O . (b) What is the voltage gain v O /v I ? (c) Assuming that the op amps operate from ±15-V power supplies and that their output saturates at ±14 V (in the manner shown in Fig. 1.14), what is the largest sine-wave output that can be accommodated? Specify both its peak-to-peak and rms values.
D 2.80 Design a Miller integrator with a time constant of 1 s and an input resistance of 100 k0002. A dc voltage of −1 volt is applied at the input at time 0, at which moment v O = −10 V. How long does it take the output to reach 0 V? +10 V?
*2.78 The two circuits in Fig. P2.78 are intended to function as voltage-to-current converters; that is, they supply the load impedance ZL with a current proportional to v I and independent of the value of ZL . Show that this is indeed the case, and find for each circuit iO as a function of v I . Comment on the differences between the two circuits.
2.81 An op-amp-based inverting integrator is measured at 10 kHz to have a voltage gain of −100 V/V. At what frequency is its gain reduced to −1 V/V? What is the integrator time constant?
2.79 A Miller integrator incorporates an ideal op amp, a resistor R of 10 k0002, and a capacitor C of 1 nF. A sine-wave signal is applied to its input.
D 2.82 Design a Miller integrator that has a unity-gain frequency of 10 krad/s and an input resistance of 100 k0002. Sketch the output you would expect for the situation in which, with output initially at 0 V, a 2-V, 100-μs pulse is applied to the input. Characterize the output that results when a sine 4 wave 2 sin 10 t is applied to the input.
(a) At what frequency (in Hz) are the input and output signals equal in amplitude? (b) At that frequency, how does the phase of the output sine wave relate to that of the input?
D 2.83 Design a Miller integrator whose input resistance is 10 k0002 and unity-gain frequency is 100 kHz. What components are needed? For long-term stability, a feedback resistor is introduced across the capacitor to limit the dc gain
Section 2.5: Integrators and Differentiators
R1 0003
0003
R1 0003
0002 ZL vI
iO
R
0002 0003
vI 0002
R R1
R1
0002 0003
0002 0003
0002
0002
0003
(a)
ZL
iO
(b)
Figure P2.78
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Problems 129
PROBLEMS
*2.84 A Miller integrator whose input and output voltages are initially zero and whose time constant is 1 ms is driven by the signal shown in Fig. P2.84. Sketch and label the output waveform that results. Indicate what happens if the input levels are ±2 V, with the time constant the same (1 ms) and with the time constant raised to 2 ms.
low-pass active filter. Derive the transfer function and show that the dc gain is (−R2 /R1 ) and the 3-dB frequency ω0 = 1/CR2 . Design the circuit to obtain an input resistance of 10 k0002, a dc gain of 40 dB, and a 3-dB frequency of 1 kHz. At what frequency does the magnitude of the transfer function reduce to unity?
Vo
Figure P2.86
Figure P2.84
2.85 Consider a Miller integrator having a time constant of 1 ms and an output that is initially zero, when fed with a string of pulses of 10-μs duration and 1-V amplitude rising from 0 V (see Fig. P2.85). Sketch and label the output waveform resulting. How many pulses are required for an output voltage change of 1 V?
*2.87 Show that a Miller integrator implemented with an op amp with open-loop gain A0 has a low-pass STC transfer function. What is the pole frequency of the STC function? How does this compare with the pole frequency of the ideal integrator? If an ideal Miller integrator is fed with a −1-V pulse signal with a width T = CR, what will the output voltage be at t = T ? Assume that at t = 0, v O = 0. Repeat for an integrator with an op amp having A0 = 1000. 2.88 A differentiator utilizes an ideal op amp, a 10-k0002 resistor, and a 1-nF capacitor. What is the frequency f0 (in Hz) at which its input and output sine-wave signals have equal magnitude? What is the output signal for a 1-V peak-to-peak sine-wave input with frequency equal to 10f0 ? 2.89 An op-amp differentiator with 1-ms time constant is driven by the rate-controlled step shown in Fig. P2.89. Assuming v O to be zero initially, sketch and label its waveform.
Figure P2.85
D 2.86 Figure P2.86 shows a circuit that performs a low-pass STC function. Such a circuit is known as a first-order,
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to 40 dB. What is its value? What is the associated lower 3-dB frequency? Sketch and label the output that results with a 10-μs, 1-V positive-input pulse (initially at 0 V) with (a) no dc stabilization (but with the output initially at 0 V) and (b) the feedback resistor connected.
0.2 Figure P2.89
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PROBLEMS
130 Chapter 2 Operational Amplifiers 2.90 An op-amp differentiator, employing the circuit shown in Fig. 2.27(a), has R = 20 k0002 and C = 0.1 μF. When a triangle wave of ±1-V peak amplitude at 1 kHz is applied to the input, what form of output results? What is its frequency? What is its peak amplitude? What is its average value? What value of R is needed to cause the output to have a 12-V peak amplitude?
for the transfer function in the following frequency regions: (a) ω 0005 ω1 (b) ω1 0005 ω 0005 ω2 (c) ω 0006 ω2
2.91 Use an ideal op amp to design a differentiation circuit −3 for which the time constant is 10 s using a 10-nF capacitor. What are the gains and phase shifts found for this circuit at one-tenth and 10 times the unity-gain frequency? A series input resistor is added to limit the gain magnitude at high frequencies to 100 V/V. What is the associated 3-dB frequency? What gain and phase shift result at 10 times the unity-gain frequency? D 2.92 Figure P2.92 shows a circuit that performs the high-pass, single-time-constant function. Such a circuit is known as a first-order high-pass active filter. Derive the transfer function and show that the high-frequency gain is (−R2 /R1 ) and the 3-dB frequency ω0 = 1/CR1 . Design the circuit to obtain a high-frequency input resistance of 1 k0002, a high-frequency gain of 40 dB, and a 3-dB frequency of 2 kHz. At what frequency does the magnitude of the transfer function reduce to unity?
Vo
Vo
Figure P2.93
Use these approximations to sketch a Bode plot for the magnitude response. Observe that the circuit performs as an amplifier whose gain rolls off at the low-frequency end in the manner of a high-pass STC network, and at the high-frequency end in the manner of a low-pass STC network. Design the circuit to provide a gain of 40 dB in the “middle-frequency range,” a low-frequency 3-dB point at 200 Hz, a high-frequency 3-dB point at 200 kHz, and an input resistance (at ω 0006 ω1 ) of 2 k0002.
Section 2.6: DC Imperfections 2.94 An op amp wired in the inverting configuration with the input grounded, having R2 = 100 k0002 and R1 = 2 k0002, has an output dc voltage of −0.2 V. If the input bias current is known to be very small, find the input offset voltage.
Figure P2.92
D **2.93 Derive the transfer function of the circuit in Fig. P2.93 (for an ideal op amp) and show that it can be written in the form
2.95 A noninverting amplifier with a gain of 100 uses an op amp having an input offset voltage of ±2 mV. Find the output when the input is 0.01 sin ωt, volts.
Vo −R2 /R1 = Vi [1 + (ω1 /jω)][1 + j(ω/ω2 )]
2.96 A noninverting amplifier with a closed-loop gain of 1000 is designed using an op amp having an input offset voltage of 3 mV and output saturation levels of ±12 V. What is the maximum amplitude of the sine wave that can be applied at the input without the output clipping? If the amplifier is
where ω1 = 1/C1 R1 and ω2 = 1/C2 R2 . Assuming that the circuit is designed such that ω2 0006 ω1 , find approximate expressions
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Problems 131
PROBLEMS
2.97 An op amp connected in a closed-loop inverting configuration having a gain of 1000 V/V and using relatively small-valued resistors is measured with input grounded to have a dc output voltage of −1.8 V. What is its input offset voltage? Prepare an offset-voltage-source sketch resembling that in Fig. 2.28. Be careful of polarities.
through a capacitor C? If, instead, a large capacitor is placed in series with a 1-k0002 resistor, what does the output offset become?
2.98 A particular inverting amplifier with nominal gain of −100 V/V uses an imperfect op amp in conjunction with 100-k0002 and 10-M0002 resistors. The output voltage is found to be +5.3 V when measured with the input open and +5 V with the input grounded. (a) What is the bias current of this amplifier? In what direction does it flow? (b) Estimate the value of the input offset voltage. (c) A 10-M0002 resistor is connected between the positive-input terminal and ground. With the input left floating (disconnected), the output dc voltage is measured to be −0.6 V. Estimate the input offset current. D *2.99 A noninverting amplifier with a gain of +10 V/V using 100 k0002 as the feedback resistor operates from a 5-k0002 source. For an amplifier offset voltage of 0 mV, but with a bias current of 2 μA and an offset current of 0.2 μA, what range of outputs would you expect? Indicate where you would add an additional resistor to compensate for the bias currents. What does the range of possible outputs then become? A designer wishes to use this amplifier with a 15-k0002 source. In order to compensate for the bias current in this case, what resistor would you use? And where? D 2.100 The circuit of Fig. 2.36 is used to create an ac-coupled noninverting amplifier with a gain of 100 V/V using resistors no larger than 100 k0002. What values of R1 , R2 , and R3 should be used? For a break frequency due to C1 at 100 Hz, and that due to C2 at 10 Hz, what values of C1 and C2 are needed? *2.101 Consider the difference amplifier circuit in Fig. 2.16. Let R1 = R3 = 10 k0002 and R2 = R4 = 1 M0002. If the op amp has VOS = 5 mV, IB = 1 μA, and IOS = 0.2 μA, find the worst-case (largest) dc offset voltage at the output. *2.102 The circuit shown in Fig. P2.102 uses an op amp having a ±3-mV offset. What is its output offset voltage? What does the output offset become with the input ac coupled
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capacitively coupled in the manner indicated in Fig. 2.36, what would the maximum possible amplitude be?
Figure P2.102
2.103 Using offset-nulling facilities provided for the op amp, a closed-loop amplifier with gain of +1000 is adjusted at 25°C to produce zero output with the input grounded. If the input offset-voltage drift is specified to be 20 μV/°C, what output would you expect at 0°C and at 100°C? While nothing can be said separately about the polarity of the output offset at either 0 or 75°C, what would you expect their relative polarities to be? 2.104 An op amp is connected in a closed loop with gain of +100 utilizing a feedback resistor of 1 M0002. (a) If the input bias current is 200 nA, what output voltage results with the input grounded? (b) If the input offset voltage is ±2 mV and the input bias current as in (a), what is the largest possible output that can be observed with the input grounded? (c) If bias-current compensation is used, what is the value of the required resistor? If the offset current is no more than one-tenth the bias current, what is the resulting output offset voltage (due to offset current alone)? (d) With bias-current compensation as in (c) in place, what is the largest dc voltage at the output due to the combined effect of offset voltage and offset current? *2.105 An op amp intended for operation with a closed-loop gain of –100 V/V uses resistors of 10 k0002 and 1 M0002 with a bias-current-compensation resistor R3 . What should the value of R3 be? With input grounded, the output offset voltage is found to be +0.30 V. Estimate the input offset current assuming zero input offset voltage. If the input offset voltage
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CHAPTER 2
PROBLEMS
132 Chapter 2 Operational Amplifiers can be as large as 1 mV of unknown polarity, what range of offset current is possible? 2.106 A Miller integrator with R = 10 k0002 and C = 10 nF is implemented by using an op amp with VOS = 2 mV, IB = 0.1 μA, and IOS = 20 nA. To provide a finite dc gain, a 1-M0002 resistor is connected across the capacitor. (a) To compensate for the effect of IB , a resistor is connected in series with the positive-input terminal of the op amp. What should its value be? (b) With the resistor of (a) in place, find the worst-case dc output voltage of the integrator when the input is grounded.
Section 2.7: Effect of Finite Open-Loop Gain and Bandwidth on Circuit Performance 2.107 The data in the following table apply to internally compensated op amps. Fill in the blank entries. A0
105 106
2 × 105
fb (Hz)
ft (Hz)
102 103 10−1 10
106 108 106
2.108 A measurement of the open-loop gain of an internally compensated op amp at very low frequencies shows it to be 98 dB; at 100 kHz, this shows it is 40 dB. Estimate values for A0 , fb , and ft . 2.109 Measurements of the open-loop gain of a compensated op amp intended for high-frequency operation indicate that the gain is 4 × 103 at 100 kHz and 20 × 103 at 10 kHz. Estimate its 3-dB frequency, its unity-gain frequency, and its dc gain. 2.110 Measurements made on the internally compensated amplifiers listed below provide the dc gain and the frequency at which the gain has dropped by 20 dB. For each, what are the 3 dB and unity-gain frequencies? (a) (b) (c) (d) (e)
2 × 105 V/V and 5 × 102 Hz 20 × 105 V/V and 10 Hz 1800 V/V and 0.1 MHz 100 V/V and 0.1 GHz 25 V/mV and 250 kHz
2.111 An inverting amplifier with nominal gain of −50 V/V employs an op amp having a dc gain of 104 and a unity-gain frequency of 106 Hz. What is the 3-dB frequency f3dB of the closed-loop amplifier? What is its gain at 0.1 f3dB and at 10 f3dB ? 2.112 A particular op amp, characterized by a gain–bandwidth product of 20 MHz, is operated with a closed-loop gain of +100 V/V. What 3-dB bandwidth results? At what frequency does the closed-loop amplifier exhibit a −6° phase shift? A −84° phase shift? 2.113 Find the ft required for internally compensated op amps to be used in the implementation of closed-loop amplifiers with the following nominal dc gains and 3-dB bandwidths: (a) (b) (c) (d) (e) (f) (g)
−50 V/V; 100 kHz +50 V/V; 100 kHz +2 V/V; 5 MHz −2 V/V; 5 MHz −1000 V/V; 10 kHz +1 V/V; 1 MHz −1 V/V; 1 MHz
2.114 A noninverting op-amp circuit with a gain of 96 V/V is found to have a 3-dB frequency of 8 kHz. For a particular system application, a bandwidth of 32 kHz is required. What is the highest gain available under these conditions? 2.115 Consider a unity-gain follower utilizing an internally compensated op amp with ft = 2 MHz. What is the 3-dB frequency of the follower? At what frequency is the gain of the follower 1% below its low-frequency magnitude? If the input to the follower is a 1-V step, find the 10% to 90% rise time of the output voltage. (Note: The step response of STC low-pass networks is discussed in Appendix E. Specifically, note that the 10%–90% rise time of a low-pass STC circuit with a time constant τ is 2.2τ .) D *2.116 It is required to design a noninverting amplifier with a dc gain of 10. When a step voltage of 100 mV is applied at the input, it is required that the output be within 1% of its final value of 1 V in at most 200 ns. What must the ft of the op amp be? (Note: The step response of STC low-pass networks is discussed in Appendix E.) D *2.117 This problem illustrates the use of cascaded closed-loop amplifiers to obtain an overall bandwidth greater than can be achieved using a single-stage amplifier with the same overall gain.
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Problems 133
D **2.118 A designer, wanting to achieve a stable gain of 100 V/V at 5 MHz, considers her choice of amplifier topologies. Whatunity-gainfrequencywouldasingleoperationalamplifier require to satisfy her need? Unfortunately, the best available amplifier has an ft of 40 MHz. How many such amplifiers connected in a cascade of identical noninverting stages would she need to achieve her goal? What is the 3-dB frequency of each stage she can use? What is the overall 3-dB frequency? 2.119 Consider the use of an op amp with a unity-gain frequency ft in the realization of: (a) An inverting amplifier with dc gain of magnitude K. (b) A noninverting amplifier with a dc gain of K. In each case find the 3-dB frequency and the gain–bandwidth product (GBP ≡ |Gain| × f3dB ). Comment on the results. *2.120 Consider an inverting summer with two inputs V1 and V2 and with Vo = −(V1 + 3V2 ). Find the 3-dB frequency of each of the gain functions Vo /V1 and Vo /V2 in terms of the op amp ft . (Hint: In each case, the other input to the summer can be set to zero—an application of superposition.)
Section 2.8: Large-Signal Operation of Op Amps 2.121 A particular op amp using ±15-V supplies operates linearly for outputs in the range −14 V to +14 V. If used in an inverting amplifier configuration of gain −100, what is the rms value of the largest possible sine wave that can be applied at the input without output clipping? 2.122 Consider an op amp connected in the inverting configuration to realize a closed-loop gain of −100 V/V utilizing resistors of 1 k0002 and 100 k0002. A load resistance RL
(a) For RL = 1 k0002, what is the maximum possible value of Vp while an undistorted output sinusoid is obtained? (b) Repeat (a) for RL = 200 0002. (c) If it is desired to obtain an output sinusoid of 10-V peak amplitude, what minimum value of RL is allowed? 2.123 An op amp having a slew rate of 10 V/μs is to be used in the unity-gain follower configuration, with input pulses that rise from 0 to 2 V. What is the shortest pulse that can be used while ensuring full-amplitude output? For such a pulse, describe the output resulting. 2.124 For operation with 10-V output pulses with the requirement that the sum of the rise and fall times represent only 20% of the pulse width (at half-amplitude), what is the slew-rate requirement for an op amp to handle pulses 2 μs wide? (Note: The rise and fall times of a pulse signal are usually measured between the 10%- and 90%-height points.) 2.125 What is the highest frequency of a triangle wave of 10-V peak-to-peak amplitude that can be reproduced by an op amp whose slew rate is 20 V/μs? For a sine wave of the same frequency, what is the maximum amplitude of output signal that remains undistorted? 2.126 For an amplifier having a slew rate of 40 V/μs, what is the highest frequency at which a 20-V peak-to-peak sine wave can be produced at the output? D *2.127 In designing with op amps one has to check the limitations on the voltage and frequency ranges of operation of the closed-loop amplifier, imposed by the op-amp finite bandwidth (ft ), slew rate (SR), and output saturation (Vo max ). This problem illustrates the point by considering the use of an op amp with ft = 20 MHz, SR = 10 V/μs, and Vo max = 10 V in the design of a noninverting amplifier with a nominal gain of 10. Assume a sine-wave input with peak amplitude Vi . (a) If Vi = 0.5 V, what is the maximum frequency before the output distorts? (b) If f = 200 kHz, what is the maximum value of Vi before the output distorts? (c) If Vi = 50 mV, what is the useful frequency range of operation? (d) If f = 50 kHz, what is the useful input voltage range?
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
(b) It is required to design a noninverting amplifier with a dc gain of 40 dB utilizing a single internally compensated op amp with ft = 2 MHz. What is the 3-dB frequency obtained? (c) Redesign the amplifier of (b) by cascading two identical noninverting amplifiers each with a dc gain of 20 dB. What is the 3-dB frequency of the overall amplifier? Compare this to the value obtained in (b) above.
is connected from the output to ground, and a low-frequency sine-wave signal of peak amplitude Vp is applied to the input. Let the op amp be ideal except that its output voltage saturates at ±10 V and its output current is limited to the range ±20 mA.
CHAPTER 2
(a) Show that cascading two identical amplifier stages, each having a low-pass STC frequency response with a 3-dB frequency f1 , results in an overall amplifier with a 3-dB frequency given by √ f3dB = 2–1 f1
PROBLEMS If in the following problems the need arises for the values of particular parameters or physical constants that are not stated, please consult Table 3.1.
Section 3.1: Intrinsic Semiconductors 3.1 Find values of the intrinsic carrier concentration ni for silicon at −55°C, 0°C, 20°C, 75°C, and 125°C. At each temperature, what fraction of the atoms is ionized? 22 Recall that a silicon crystal has approximately 5 × 10 3 atoms/cm . 3.2 Calculate the value of ni for gallium arsenide (GaAs) at 14 −3 −3/2 T = 300 K. The constant B = 3.56 × 10 cm K and the bandgap voltage Eg = 1.42 eV.
Section 3.2: Doped Semiconductors 3.3 For a p-type silicon in which the dopant concentration 18 3 NA = 5 × 10 /cm , find the hole and electron concentrations at T = 300 K. 3.4 For a silicon crystal doped with phosphorus, what must ND be if at T = 300 K the hole concentration drops below the 8 intrinsic level by a factor of 10 ?
2
of 3 V is imposed. Let μn = 1350 cm /V · s and μp = 2 480 cm /V · s· 3.8 Find the current that flows in a silicon bar of 10-μm length having a 5-μm × 4-μm cross-section and having 4 3 16 3 free-electron and hole densities of 10 /cm and 10 /cm , respectively, when a 1 V is applied end-to-end. Use μn = 2 2 1200 cm /V · s and μp = 500 cm /V · s. 3.9 In a 10-μm-long bar of donor-doped silicon, what donor concentration is needed to realize a current density 2 of 2 mA/μm in response to an applied voltage of 1 V? (Note: Although the carrier mobilities change with doping concentration, as a first approximation you may assume μn 2 to be constant and use 1350 cm /V · s, the value for intrinsic silicon.) 3.10 Holes are being steadily injected into a region of n-type silicon (connected to other devices, the details of which are not important for this question). In the steady state, the excess-hole concentration profile shown in Fig. P3.10 is established in the n-type silicon region. Here “excess” means over and above the thermal-equilibrium concentration (in the 16 3 absence of hole injection), denoted pn0 . If ND = 10 /cm , 10 3 2 ni = 1.5 × 10 /cm , Dp = 12 cm /s, and W = 50 nm, find the density of the current that will flow in the x direction.
3.5 In a phosphorus-doped silicon layer with impurity 17 3 concentration of 10 /cm , find the hole and electron concentrations at 27°C and 125°C.
Section 3.3: Current Flow in Semiconductors 3.6 A young designer, aiming to develop intuition concerning conducting paths within an integrated circuit, examines the end-to-end resistance of a connecting bar 10-μm long, 3-μm wide, and 1 μm thick, made of various materials. The designer considers: (a) (b) (c) (d) (e)
intrinsic silicon 16 3 n-doped silicon with ND = 5 × 10 /cm 18 3 n-doped silicon with ND = 5 × 10 /cm 16 3 p-doped silicon with NA = 5 × 10 /cm aluminum with resistivity of 2.8 μ0005· cm
Find the resistance in each case. For intrinsic silicon, use the data in Table 3.1. For doped silicon, assume μn = 3μp = 2 1200 cm /V · s. (Recall that R = ρL/A.) 3.7 Contrast the electron and hole drift velocities through a 10-μm layer of intrinsic silicon across which a voltage
pn(x)
108 pn0
n region
pn0
0
W
x
Figure P3.10
3.11 Both the carrier mobility and the diffusivity decrease as the doping concentration of silicon is increased. Table P3.11 provides a few data points for μn and μp versus doping concentration. Use the Einstein relationship to obtain the corresponding values for Dn and Dp .
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 3
PROBLEMS
172 Chapter 3 Semiconductors Table P3.11 Doping Concentration 3
(carriers/cm )
Intrinsic 16 10 17 10 18 10
2
2
μn (cm /V · s)
μp (cm /V · s)
1350 1200 750 380
480 400 260 160
Section 3.4: The pn Junction 3.12 Calculate the built-in voltage of a junction in which the 16 3 p and n regions are doped equally with 5 × 10 atoms/cm . 10 3 Assume ni = 1.5 × 10 /cm . With the terminals left open, what is the width of the depletion region, and how far does it extend into the p and n regions? If the cross-sectional area 2 of the junction is 20 μm , find the magnitude of the charge stored on either side of the junction. 3.13 If, for a particular junction, the acceptor concentration 17 3 16 3 is 10 /cm and the donor concentration is 10 /cm , find the 10 3 junction built-in voltage. Assume ni = 1.5 × 10 /cm . Also, find the width of the depletion region (W) and its extent in each of the p and n regions when the junction terminals are left open. Calculate the magnitude of the charge stored on either side of the junction. Assume that the junction area is 2 100 μm . 3.14 Estimate the total charge stored in a 0.1-μm depletion layer on one side of a 10-μm × 10-μm junction. The doping 18 3 concentration on that side of the junction is 10 /cm . 3.15 In a pn junction for which NA 0003 ND , and the depletion layer exists mostly on the shallowly doped side with W = 16 3 0.2 μm, find V0 if ND = 10 /cm . Also calculate QJ for the 2 case A = 10 μm . 3.16 By how much does V0 change if NA or ND is increased by a factor of 10?
Section 3.5: The pn Junction with an Applied Voltage 3.17 If a 3-V reverse-bias voltage is applied across the junction specified in Problem 3.13, find W and QJ . 3.18 Show that for a pn junction reverse-biased with a voltage VR , the depletion-layer width W and the
2
2
Dn (cm /s)
Dp (cm /s)
charge stored on either side of the junction, QJ , can be expressed as W = W0 1 +
VR V0
QJ = QJ0 1 +
VR V0
where W0 and QJ0 are the values in equilibrium. 3.19 In a forward-biased pn junction show that the ratio of the current component due to hole injection across the junction to the component due to electron injection is given by Ip Dp Ln NA = In Dn Lp ND 18
3
Evaluate this ratio for the case NA = 10 /cm , ND = 16 3 2 10 /cm , Lp = 5 μm, Ln = 10 μm, Dp = 10 cm /s, and 2 Dn = 20 cm /s, and hence find Ip and In for the case in which the pn junction is conducting a forward current I = 100 μA. 3.20 Calculate IS and the current I for V = 750 mV for 17 3 16 3 a pn junction for which NA = 10 /cm , ND = 10 /cm , 2 10 3 A = 100 μm , ni = 1.5 × 10 /cm , Lp = 5 μm, Ln = 10 μm, 2 2 Dp = 10 cm /s, and Dn = 18 cm /s. 3.21 Assuming that the temperature dependence of IS arises 2 mostly because IS is proportional to ni , use the expression for 2 ni in Eq. (3.2) to determine the factor by which ni changes as T changes from 300 K to 305 K. This will be approximately the same factor by which IS changes for a 5°C rise in temperature. What is the factor?
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Problems 173
2
I 0002 Ip = Aqni
0003 Dp 0002 V/VT −1 e Lp ND 3
2
For the specific case in which ND = 10 /cm , Dp = 10 cm /s, 4 2 Lp = 10 μm, and A = 10 μm , find IS and the voltage V obtained when I = 1 mA. Assume operation at 300 K where 10 3 ni = 1.5 × 10 /cm . 3.23 A pn junction for which the breakdown voltage is 12 V has a rated (i.e., maximum allowable) power dissipation of 0.25 W. What continuous current in the breakdown region will raise the dissipation to half the rated value? If breakdown occurs for only 10 ms in every 20 ms, what average breakdown current is allowed?
Section 3.6: Capacitive Effects in the pn Junction
+
3.28 For the p n junction specified in Problem 3.22, find τp and calculate the excess minority-carrier charge and the value of the diffusion capacitance at I = 0.1 mA. *3.29 A short-base diode is one where the widths of the p and n regions are much smaller than Ln and Lp , respectively. As a result, the excess minority-carrier distribution in each region is a straight line rather than the exponentials shown in Fig. 3.12. (a) For the short-base diode, sketch a figure corresponding to Fig. 3.12 and assume as in Fig. 3.12 that NA 0003 ND . (b) Following a derivation similar to that given in Section 3.5.2, show that if the widths of the p and n regions are denoted Wp and Wn then 0012 I = Aqn
0004 00052 1 Wn − xn Qp = Ip 2 Dp
3.25 For a particular junction for which Cj0 = 0.4 pF, V0 = 0.75 V, and m = 1/3, find Cj at reverse-bias voltages of 1 V and 10 V.
Cj =
2
0002
3.27 A pn junction operating in the forward-bias region with a current I of 1 mA is found to have a diffusion capacitance of 5 pF. What diffusion capacitance do you expect this junction
1 Wn I , for Wn 0003 xn 2 Dp p
(c) Also, assuming Q 0002 Qp , I 0002 Ip , show that
eA W
Show that this approach leads to a formula identical to that obtained by combining Eqs. (3.43) and (3.45) [or equivalently, by combining Eqs. (3.47) and (3.48)].
0013 0003 0002 Dn V/V 0004 0005 +0004 0005 e T −1 Wn − xn ND Wp − xp NA Dp
and
3.24 For the pn junction specified in Problem 3.13, find Cj0 and Cj at VR = 3 V.
3.26 The junction capacitance Cj can be thought of as that of a parallel-plate capacitor and thus given by
2 i
Cd =
τT I VT
where 2
τT =
1 Wn 2 Dp
(d) If a designer wishes to limit Cd to 8 pF at I = 1 mA, what 2 should Wn be? Assume Dp = 10 cm /s.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
17
to have at I = 0.1 mA? What is the mean transit time for this junction?
CHAPTER 3
+
3.22 A p n junction is one in which the doping concentration in the p region is much greater than that in the n region. In such a junction, the forward current is mostly due to hole injection across the junction. Show that
230 Chapter 4 Diodes 0002
In many applications, a conducting diode is modeled as having a constant voltage drop, usually approximately 0.7 V.
0002
A diode biased to operate at a dc current ID has a small-signal resistance rd = VT /ID .
0002
Rectifiers convert ac voltages into unipolar voltages. Half-wave rectifiers do this by passing the voltage in half of each cycle and blocking the opposite-polarity voltage in the other half of the cycle. Full-wave rectifiers accomplish the task by passing the voltage in half of each cycle and inverting the voltage in the other half-cycle.
0002
The bridge-rectifier circuit is the preferred full-wave rectifier configuration.
0002
The variation of the output waveform of the rectifier is reduced considerably by connecting a capacitor C across the output load resistance R. The resulting circuit is the peak rectifier. The output waveform then consists of a dc voltage almost equal to the peak of the input sine
wave, Vp , on which is superimposed a ripple component of frequency 2f (in the full-wave case) and of peak-to-peak amplitude Vr = Vp /2fCR. To reduce this ripple voltage further, a voltage regulator is employed. 0002
Combination of diodes, resistors, and possibly reference voltages can be used to design voltage limiters that prevent one or both extremities of the output waveform from going beyond predetermined values, the limiting level(s).
0002
Applying a time-varying waveform to a circuit consisting of a capacitor in series with a diode and taking the output across the diode provides a clamping function. Specifically, depending on the polarity of the diode, either the positive or negative peaks of the signal will be clamped to the voltage at the other terminal of the diode (usually ground). In this way the output waveform has a nonzero average or dc component, and the circuit is known as a dc restorer.
0002
By cascading a clamping circuit with a peak-rectifier circuit, a voltage doubler is realized.
PROBLEMS
Computer Simulation Problems Problems identified by the Multisim/PSpice icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion. Instructions to assist in setting up PSPice and Multisim simulations for all the indicated problems can be found in the corresponding files on the website. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
Section 4.1: The Ideal Diode 4.1 An AA flashlight cell, whose Th´evenin equivalent is a voltage source of 1.5 V and a resistance of 1 0002, is connected
to the terminals of an ideal diode. Describe two possible situations that result. What are the diode current and terminal voltage when (a) the connection is between the diode cathode and the positive terminal of the battery and (b) the anode and the positive terminal are connected? 4.2 For the circuits shown in Fig. P4.2 using ideal diodes, find the values of the voltages and currents indicated. 4.3 For the circuits shown in Fig. P4.3 using ideal diodes, find the values of the labeled voltages and currents. 4.4 In each of the ideal-diode circuits shown in Fig. P4.4, v I is a 1-kHz, 5-V peak sine wave. Sketch the waveform resulting at v O . What are its positive and negative peak values?
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Problems 231
3
3
3
3
3
3
(b)
(a)
(c)
PROBLEMS
3
CHAPTER 4
3
(d)
Figure P4.2
3
D
2
2 D
D 2 2 D
3 (a)
(b)
Figure P4.3
vI
D1
vO
D1
vI
D2
vO
1 k000b
D1
vI
D2
1 k000b
(a)
vO 1 k000b
(b)
(c) D3
vI
D1
vO
vI
D2
vO
1 k D2
1 k D1
(d)
(e)
vI
D1
vO D2
(f )
Figure P4.4
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1 k000b
232 Chapter 4 Diodes 1 k000b
PROBLEMS
vI vI
1 k000b
vO
1 k000b
vI
CHAPTER 4
D1
vO
D1
(g)
vO 1 k D1
D2
(i)
(h) 000315 V
1 mA vO
D1 1 k vO
vI 1 k 1 k000b
D1
D2 vI
( j)
(k)
Figure P4.4 continued
4.5 The circuit shown in Fig. P4.5 is a model for a battery charger. Here v I is a 6-V peak sine wave, D1 and D2 are ideal diodes, I is a 60-mA current source, and B is a 3-V battery. Sketch and label the waveform of the battery current iB . What is its peak value? What is its average value? If the peak value of v I is reduced by 10%, what do the peak and average values of iB become?
4.6 The circuits shown in Fig. P4.6 can function as logic gates for input voltages that are either high or low. Using “1” to denote the high value and “0” to denote the low value, prepare a table with four columns including all possible input combinations and the resulting values of X and Y. What logic function is X of A and B? What logic function is Y of A and B? For what values of A and B do X and Y have the same value? For what values of A and B do X and Y have opposite values?
D3 A
I I
iB vI
vO D1
B
D1 A
D2
X
Y D4 I
B
B D2 (a)
Figure P4.5
Figure P4.6
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
(b)
Problems 233
D 4.8 Repeat Problem 4.7 for the logic gate of Fig. 4.5(b).
00033V
4.13 A symmetrical square wave of 5-V peak-to-peak amplitude and zero average is applied to a circuit resembling that in Fig. 4.3(a) and employing a 100-0002 resistor. What is the peak output voltage that results? What is the average output voltage that results? What is the peak diode current? What is the average diode current? What is the maximum reverse voltage across the diode?
00033V
12 k000b
D
6 k000b
D
D
D
6 k000b
12 k000b
00023V
00023V
(a)
(b)
Figure P4.9
4.10 Assuming that the diodes in the circuits of Fig. P4.10 are ideal, utilize Th´evenin’s theorem to simplify the circuits and thus find the values of the labeled currents and voltages.
00035 V
00035V
4.12 Consider the rectifier circuit of Fig. 4.3(a) in the event that the input source v I has a source resistance Rs . For the case Rs = R and assuming the diode to be ideal, sketch and clearly label the transfer characteristic v O versus v I .
00033 V
10 k000b
4.14 Repeat Problem 4.13 for the situation in which the average voltage of the square wave is 1 V, while its peak-to-peak value remains at 5 V. D *4.15 Design a battery-charging circuit, resembling that in Fig. 4.4(a) and using an ideal diode, in which current flows to the 12-V battery 25% of the time with an average value of 100 mA. What peak-to-peak sine-wave voltage is required? What resistance is required? What peak diode current flows? What peak reverse voltage does the diode endure? If resistors can be specified to only one significant digit, and the peak-to-peak voltage only to the nearest volt, what design would you choose to guarantee the required charging current? What fraction of the cycle does diode current flow? What is the average diode current? What is the peak diode current? What peak reverse voltage does the diode endure? 4.16 The circuit of Fig. P4.16 can be used in a signaling system using one wire plus a common ground return. At any moment, the input has one of three values: +3 V, 0 V, –3 V.
10 k I 0002 V 0003
10 k000b
10
(a)
10 k000b
D
(b)
Figure P4.10
D 4.11 For the rectifier circuit of Fig. 4.3(a), let the input sine wave have 120-V rms value and assume the diode to
Figure P4.16
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
D
PROBLEMS
4.9 Assuming that the diodes in the circuits of Fig. P4.9 are ideal, find the values of the labeled voltages and currents.
be ideal. Select a suitable value for R so that the peak diode current does not exceed 40 mA. What is the greatest reverse voltage that will appear across the diode?
CHAPTER 4
D 4.7 For the logic gate of Fig. 4.5(a), assume ideal diodes and input voltage levels of 0 V and +5 V. Find a suitable value for R so that the current required from each of the input signal sources does not exceed 0.2 mA.
PROBLEMS
What is the status of the lamps for each input value? (Note that the lamps can be located apart from each other and that there may be several of each type of connection, all on one wire!)
CHAPTER 4
234 Chapter 4 Diodes
4.17 Calculate the value of the thermal voltage, VT , at –55°C, 0°C, +40°C, and +125°C. At what temperature is VT exactly 25 mV?
Section 4.2: Terminal Characteristics of Junction Diodes
4.18 At what forward voltage does a diode conduct a current equal to 10,000IS ? In terms of IS , what current flows in the same diode when its forward voltage is 0.7 V? Figure P4.23
4.19 A diode for which the forward voltage drop is 0.7 V at 1.0 mA is operated at 0.5 V. What is the value of the current? 4.20 A particular diode is found to conduct 1 mA with a junction voltage of 0.7 V. What current will flow in this diode if the junction voltage is raised to 0.71 V? To 0.8 V? If the junction voltage is lowered to 0.69 V? To 0.6 V? What change in junction voltage will increase the diode current by a factor of 10? 4.21 The following measurements are taken on particular junction diodes for which V is the terminal voltage and I is the diode current. For each diode, estimate values of IS and the terminal voltage at 10% of the measured current. (a) (b) (c) (d)
V V V V
= 0.700 V at I = 1.00 A = 0.650 V at I = 1.00 mA = 0.650 V at I = 10 μA = 0.700 V at I = 100 mA
4.22 Listed below are the results of measurements taken on several different junction diodes. For each diode, the data provided are the diode current I and the corresponding diode voltage V. In each case, estimate IS , and the diode voltage at 10I and I/10. (a) (b) (c) (d) (e)
10.0 mA, 700 mV 1.0 mA, 700 mV 10 A, 800 mV 1 mA, 700 mV 10 μA, 600 mV
4.23 The circuit in Fig. P4.23 utilizes three identical diodes −14 having IS = 10 A. Find the value of the current I required to obtain an output voltage VO = 2.0 V. If a current of 1 mA is drawn away from the output terminal by a load, what is the change in output voltage?
4.24 A junction diode is operated in a circuit in which it is supplied with a constant current I. What is the effect on the forward voltage of the diode if an identical diode is connected in parallel? 4.25 Two diodes with saturation currents IS1 and IS2 are connected in parallel with their cathodes joined together and connected to grounds. The two anodes are joined together and fed with a constant current I. Find the currents ID1 and ID2 that flow through the two diodes, and the voltage VD that appears across their parallel combination. 4.26 Four diodes are connected in parallel: anodes joined together and fed with a constant current I, and cathodes joined together and connected to ground. What relative junction areas should these diodes have if their currents must have binary-weighted ratios, with the smallest being 0.1 mA? What value of I is needed? 4.27 In the circuit shown in Fig. P4.27, D1 has 10 times the junction area of D2 . What value of V results? To obtain a value for V of 60 mV, what current I2 is needed?
I1 10 mA
D1
D2
I2 3 mA
0003 V 0002 Figure P4.27
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 235
D1 0003 R
V 0002
Figure P4.28
4.29 A diode fed with a constant current I = 1 mA has a voltage V = 690 mV at 20°C. Find the diode voltage at −20°C and at +85°C. 4.30 In the circuit shown in Fig. P4.30, D1 is a large-area, high-current diode whose reverse leakage is high and independent of applied voltage, while D2 is a much smaller, low-current diode. At an ambient temperature of 20°C, resistor R1 is adjusted to make VR1 = V2 = 520 mV. Subsequent measurement indicates that R1 is 520 k0002. What do you expect the voltages VR1 and V2 to become at 0°C and at 40°C?
000310 V
*4.33 As an alternative to the idea suggested in Problem 4.32, the designer considers a second approach to producing a relatively constant small voltage from a variable current supply: It relies on the ability to make quite accurate copies of any small current that is available (using a process called current mirroring). The designer proposes to use this idea to supply two diodes of different junction areas with equal currents and to measure their junction-voltage difference. Two types of diodes are available: for a forward voltage of 700 mV, one conducts 0.1 mA, while the other conducts 1 A. Now, for identical currents in the range of 1 mA to 3 mA supplied to each, what range of difference voltages result? What is the effect of a temperature change of ±20°C on this arrangement?
Section 4.3: Modeling the Diode Forward Characteristic *4.34 Consider the graphical analysis of the diode circuit of Fig. 4.10 with VDD = 1 V, R = 1 k0002, and a diode having −15 IS = 10 A. Calculate a small number of points on the diode characteristic in the vicinity of where you expect the load line to intersect it, and use a graphical process to refine your estimate of diode current. What value of diode current and voltage do you find? Analytically, find the voltage corresponding to your estimate of current. By how much does it differ from the graphically estimated value?
R1
D1
0003 V1 0002
D2
0003 V2 0002 Figure P4.30
4.31 When a 10-A current is applied to a particular diode, it is found that the junction voltage immediately becomes 700 mV. However, as the power being dissipated in the diode raises its temperature, it is found that the voltage decreases and eventually reaches 600 mV. What is the apparent rise in
4.35 Use the iterative-analysis procedure to determine the diode current and voltage in the circuit of Fig. 4.10 for −15 VDD = 1 V, R = 1 k0002, and a diode having IS = 10 A. 4.36 A “1-mA diode” (i.e., one that has v D = 0.7 V at iD = 1 mA) is connected in series with a 500-0002 resistor to a 1.0 V supply.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
*4.32 A designer of an instrument that must operate over a wide supply-voltage range, noting that a diode’s junction-voltage drop is relatively independent of junction current, considers the use of a large diode to establish a small relatively constant voltage. A power diode, for which the nominal current at 0.8 V is 10 A, is available. If the current source feeding the diode changes in the range 1 mA to 3 mA and if, in addition, the temperature changes by ±20°C, what is the expected range of diode voltage?
I 10 mA
D2
junction temperature? What is the power dissipated in the diode in its final state? What is the temperature rise per watt of power dissipation? (This is called the thermal resistance.)
CHAPTER 4
4.28 For the circuit shown in Fig. P4.28, both diodes are identical. Find the value of R for which V = 50 mV.
CHAPTER 4
PROBLEMS
236 Chapter 4 Diodes (a) Provide a rough estimate of the diode current you would expect. (b) Estimate the diode current more closely using iterative analysis. D 4.37 Assuming the availability of diodes for which v D = 0.75 V at iD = 1 mA, design a circuit that utilizes four diodes connected in series, in series with a resistor R connected to a 15-V power supply. The voltage across the string of diodes is to be 3.3 V. 4.38 A diode operates in a series circuit with a resistance R and a dc source V. A designer, considering using a constant-voltage model, is uncertain whether to use 0.7 V or 0.6 V for VD . For what value of V is the difference in the calculated values of current only 1%? For V = 3 V and R = 1 k0002, what two current estimates would result from the use of the two values of VD ? What is their percentage difference? 4.39 A designer has a supply of diodes for which a current of 2 mA flows at 0.7 V. Using a 1-mA current source, the designer wishes to create a reference voltage of 1.3 V. Suggest a combination of series and parallel diodes that will do the job as well as possible. How many diodes are needed? What voltage is actually achieved? 4.40 Solve the problems in Example 4.2 using the constant-voltage-drop (VD = 0.7 V) diode model. 4.41 For the circuits shown in Fig. P4.2, using the constant-voltage-drop (VD = 0.7 V) diode model, find the voltages and currents indicated. 4.42 For the circuits shown in Fig. P4.3, using the constant-voltage-drop (VD = 0.7 V) diode model, find the voltages and currents indicated.
4.46 The small-signal model is said to be valid for voltage variations of about 5 mV. To what percentage current change does this correspond? (Consider both positive and negative signals.) What is the maximum allowable voltage signal (positive or negative) if the current change is to be limited to 10%? 4.47 In a particular circuit application, ten “20-mA diodes” (a 20-mA diode is a diode that provides a 0.7-V drop when the current through it is 20 mA) connected in parallel operate at a total current of 0.1 A. For the diodes closely matched, what current flows in each? What is the corresponding small-signal resistance of each diode and of the combination? Compare this with the incremental resistance of a single diode conducting 0.1 A. If each of the 20-mA diodes has a series resistance of 0.2 0002 associated with the wire bonds to the junction, what is the equivalent resistance of the 10 parallel-connected diodes? What connection resistance would a single diode need in order to be totally equivalent? (Note: This is why the parallel connection of real diodes can often be used to advantage.) 4.48 In the circuit shown in Fig. P4.48, I is a dc current and v s is a sinusoidal signal. Capacitors C1 and C2 are very large; their function is to couple the signal to and from the diode but block the dc current from flowing into the signal source or the load (not shown). Use the diode small-signal model to show that the signal component of the output voltage is vo = vs
VT VT + IRs
If v s = 10 mV, find v o for I = 1 mA, 0.1 mA, and 1 μA. Let Rs = 1 k0002. At what value of I does v o become one-half of v s ? Note that this circuit functions as a signal attenuator with the attenuation factor controlled by the value of the dc current I.
4.43 For the circuits in Fig. P4.9, using the constant-voltage-drop (VD = 0.7 V) diode model, find the values of the labeled currents and voltages.
C1
0003
4.44 For the circuits in Fig. P4.10, utilize Th´evenin’s theorem to simplify the circuits and find the values of the labeled currents and voltages. Assume that conducting diodes can be represented by the constant-voltage-drop model (VD = 0.7 V). D 4.45 Repeat Problem 4.11, representing the diode by the constant-voltage-drop (VD = 0.7 V) model. How different is the resulting design?
C2
vo 0002
Figure P4.48
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 237
I
D3
D1
vo vi
0003 0002
1 mA
D2
D4
10 k000b
I
C2 vo
C1
D1
D2
vi I
Figure P4.50
*4.51 In the circuit shown in Fig. P4.51, diodes D1 through D4 are identical, and each exhibits a voltage drop of 0.7 V at a 1-mA current. (a) For small input signals (e.g., 10-mV peak), find the small-signal equivalent circuit and use it to determine values of the small-signal transmission v o /v i for various values of I: 0 μA, 1 μA, 10 μA, 100 μA, 1 mA, and 10 mA.
Figure P4.51
**4.52 In Problem 4.51 we investigated the operation of the circuit in Fig. P4.51 for small input signals. In this problem we wish to find the voltage-transfer characteristic (VTC) v O versus v I for −12 V ≤ v I ≤ 12 V for the case I = 1 mA and each of the diodes exhibits a voltage drop of 0.7 V at a current of 1 mA. Toward this end, use the diode exponential characteristic to construct a table that gives the values of: the current iO in the 10-k0002 resistor, the current in each of the four diodes, the voltage drop across each of the four diodes, and the input voltage v I , for v O = 0, +1 V, +2 V, +5 V, +9 V, +9.9 V, +9.99 V, +10.5 V, +11 V, and +12 V. Use these data, with extrapolation to negative values of v I and v O , to sketch the required VTC. Also sketch the VTC that results if I is reduced to 0.5 mA. (Hint: From symmetry, observe that as vO increases and iO correspondingly increases, iD3 and iD2 increase by equal amounts and iD4 and iD1 decrease by (the same) equal amounts.)
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
4.50 In the capacitor-coupled attenuator circuit shown in Fig. P4.50, I is a dc current that varies from 0 mA to 1 mA, and C1 and C2 are large coupling capacitors. For very small input signals, so that the diodes can be represented by their small-signal resistances rd1 and rd2 , give the small-signal v rd2 equivalent circuit and thus show that o = and hence v i rd1 + rd2 vo = I, where I is in mA. Find v o /v i for I = 0 μA, 1 μA, that vi 10 μA, 100 μA, 500 μA, 600 μA, 900 μA, 990 μA, and 1 mA. Note that this is a signal attenuator whose transmission is linearly controlled by the dc current I.
(b) For a forward-conducting diode, what is the largest signal-voltage magnitude that it can support while the corresponding signal current is limited to 10% of the dc bias current? Now, for the circuit in Fig. P4.51, for 10-mV peak input, what is the smallest value of I for which the diode currents remain within ±10% of their dc values? (c) For I = 1 mA, what is the largest possible output signal for which the diode currents deviate by at most 10% of their dc values? What is the corresponding peak input? What is the total current in each diode?
CHAPTER 4
4.49 In the attenuator circuit of Fig. P4.48, let Rs = 10 k0002. The diode is a 1-mA device; that is, it exhibits a voltage drop of 0.7 V at a dc current of 1 mA. For small input signals, what value of current I is needed for v o /v s = 0.50? 0.10? 0.01? 0.001? In each case, what is the largest input signal that can be used while ensuring that the signal component of the diode current is limited to ±10% of its dc current? What output signals correspond?
CHAPTER 4
PROBLEMS
238 Chapter 4 Diodes *4.53 In the circuit shown in Fig. P4.53, I is a dc current and v i is a sinusoidal signal with small amplitude (less than 10 mV) and a frequency of 100 kHz. Representing the diode by its small-signal resistance rd , which is a function of I, sketch the small-signal equivalent circuit and use it to determine the sinusoidal output voltage Vo , and thus find the phase shift between Vi and Vo . Find the value of I that will provide a phase shift of –45°, and find the range of phase shift achieved as I is varied over the range of 0.1 times to 10 times this value.
(b) Generalize the expression above for the case of m diodes connected in series and the value of R adjusted so that the voltage across each diode is 0.7 V (and VO = 0.7m V). + (c) Calculate the value of line regulation for the case V = 15 V (nominally) and (i) m = 1 and (ii) m = 4. *4.55 Consider the voltage-regulator circuit shown in Fig P4.54 under the condition that a load current IL is drawn from the output terminal. (a) If the value of IL is sufficiently small that the corresponding change in regulator output voltage 0005VO is small enough to justify using the diode small-signal model, show that
I vo C 10 nF
vi 0003 0002
Figure P4.53
*4.54 Consider the voltage-regulator circuit shown in Fig. P4.54. The value of R is selected to obtain an output voltage VO (across the diode) of 0.7 V.
0002 0003 0005VO = − rd R IL This quantity is known as the load regulation and is usually expressed in mV/mA. (b) If the value of R is selected such that at no load the voltage across the diode is 0.7 V and the diode current is ID , show that the expression derived in (a) becomes +
0005VO V V −0.7 =− T + IL ID V − 0.7 + VT Select the lowest possible value for ID that results in a + load regulation whose magnitude is ≤ 5 mV/mA. If V is nominally 15 V, what value of R is required? Also, specify the diode required in terms of its IS . (c) Generalize the expression derived in (b) for the case of m diodes connected in series and R adjusted to obtain VO = 0.7m V at no load.
V
R
VO
Figure P4.54
(a) Use the diode small-signal model to show that the change in output voltage corresponding to a change of 1 V in + V is 0005VO VT = + 0005V + V + VT − 0.7 This quantity is known as the line regulation and is usually expressed in mV/V.
D *4.56 Design a diode voltage regulator to supply 1.5 V to a 1.5-k0002 load. Use two diodes specified to have a 0.7-V drop at a current of 1 mA. The diodes are to be connected to a +5-V supply through a resistor R. Specify the value for R. What is the diode current with the load connected? What is the increase resulting in the output voltage when the load is disconnected? What change results if the load resistance is reduced to 1 k0002? To 750 0002? To 500 0002? (Hint: Use the small-signal diode model to calculate all changes in output voltage.) D *4.57 A voltage regulator consisting of two diodes in series fed with a constant-current source is used as a replacement for a single carbon–zinc cell (battery) of nominal voltage 1.5 V. The regulator load current varies from 2 mA to
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 239
00035 V
0003
D2
VO
D 4.60 A designer requires a shunt regulator of approximately 20 V. Two kinds of zener diodes are available: 6.8-V devices with rz of 10 0002 and 5.1-V devices with rz of 25 0002. For the two major choices possible, find the load regulation. In this calculation neglect the effect of the regulator resistance R. 4.61 A shunt regulator utilizing a zener diode with an incremental resistance of 8 0002 is fed through an 82-0002 resistor. If the raw supply changes by 1.0 V, what is the corresponding change in the regulated output voltage?
200
D1
Assuming that the power rating of a breakdown diode is established at about twice the specified zener current (IZT ), what is the power rating of each of the diodes described above?
150
0002
Figure P4.58
(a) What is the regulator output voltage VO with the 150-0002 load connected? (b) Find VO with no load. (c) With the load connected, to what value can the 5-V supply be lowered while maintaining the loaded output voltage within 0.1 V of its nominal value? (d) What does the loaded output voltage become when the 5-V supply is raised by the same amount as the drop found in (c)? (e) For the range of changes explored in (c) and (d), by what percentage does the output voltage change for each percentage change of supply voltage in the worst case?
4.62 A 9.1-V zener diode exhibits its nominal voltage at a test current of 20 mA. At this current the incremental resistance is specified as 10 0002. Find VZ0 of the zener model. Find the zener voltage at a current of 10 mA and at 50 mA. D 4.63 Design a 7.5-V zener regulator circuit using a 7.5-V zener specified at 10 mA. The zener has an incremental resistance rz = 30 0002 and a knee current of 0.5 mA. The regulator operates from a 10-V supply and has a 1.5-k0002 load. What is the value of R you have chosen? What is the regulator output voltage when the supply is 10% high? Is 10% low? What is the output voltage when both the supply is 10% high and the load is removed? What is the smallest possible load resistor that can be used while the zener operates at a current no lower than the knee current while the supply is 10% low? What is the load voltage in this case?
4.59 Partial specifications of a collection of zener diodes are provided below. For each, identify the missing parameter and estimate its value. Note from Fig. 4.19 that VZK 0004 VZ0 and IZK is very small.
D 4.64 Provide two designs of shunt regulators utilizing the 1N5235 zener diode, which is specified as follows: VZ = 6.8 V and rz = 5 0002 for IZ = 20 mA; at IZ = 0.25 mA (nearer the knee), rz = 750 0002. For both designs, the supply voltage is nominally 9 V and varies by ±1 V. For the first design, assume that the availability of supply current is not a problem, and thus operate the diode at 20 mA. For the second design, assume that the current from the raw supply is limited, and therefore you are forced to operate the diode at 0.25 mA. For the purpose of these initial designs, assume no load. For each design find the value of R and the line regulation.
(a) VZ = 10.0 V, VZK = 9.6 V, and IZT = 50 mA (b) IZT = 10 mA, VZ = 9.1 V, and rz = 30 0002
D *4.65 A zener shunt regulator employs a 9.1-V zener diode for which VZ = 9.1 V at IZ = 9 mA, with rz = 40 0002 and
Section 4.4: Operation in the Reverse Breakdown Region—Zener Diodes
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
**4.58 A particular design of a voltage regulator is shown in Fig. P4.58. Diodes D1 and D2 are 10-mA units; that is, each has a voltage drop of 0.7 V at a current of 10 mA. Use the diode exponential model and iterative analysis to answer the following questions:
(c) rz = 2 0002, VZ = 6.8 V, and VZK = 6.6 V (d) VZ = 18 V, IZT = 5 mA, and VZK = 17.6 V (e) IZT = 200 mA, VZ = 7.5 V, and rz = 1.5 0002
CHAPTER 4
7 mA. Constant-current supplies of 5 mA, 10 mA, and 15 mA are available. Which would you choose, and why? What change in output voltage would result when the load current varies over its full range?
CHAPTER 4
PROBLEMS
240 Chapter 4 Diodes IZK = 0.5 mA. The available supply voltage of 15 V can vary as much as ±10%. For this diode, what is the value of VZ0 ? For a nominal load resistance RL of 1 k0002 and a nominal zener current of 10 mA, what current must flow in the supply resistor R? For the nominal value of supply voltage, select a value for resistor R, specified to one significant digit, to provide at least that current. What nominal output voltage results? For a ±10% change in the supply voltage, what variation in output voltage results? If the load current is reduced by 50%, what increase in VO results? What is the smallest value of load resistance that can be tolerated while maintaining regulation when the supply voltage is low? What is the lowest possible output voltage that results? Calculate values for the line regulation and for the load regulation for this circuit using the numerical results obtained in this problem. D *4.66 It is required to design a zener shunt regulator to provide a regulated voltage of about 10 V. The available 10-V, 1-W zener of type 1N4740 is specified to have a 10-V drop at a test current of 25 mA. At this current, its rz is 7 0002. The raw supply, VS , available has a nominal value of 20 V but can vary by as much as ±25%. The regulator is required to supply a load current of 0 mA to 20 mA. Design for a minimum zener current of 5 mA. (a) Find VZ0 . (b) Calculate the required value of R. (c) Find the line regulation. What is the change in VO expressed as a percentage, corresponding to the ±25% change in VS ? (d) Find the load regulation. By what percentage does VO change from the no-load to the full-load condition? (e) What is the maximum current that the zener in your design is required to conduct? What is the zener power dissipation under this condition?
Section 4.5: Rectifier Circuits 4.67 Consider the half-wave rectifier circuit of Fig. 4.23(a) with the diode reversed. Let v S be a sinusoid with 10-V peak amplitude, and let R = 1 k0002. Use the constant-voltage-drop diode model with VD = 0.7 V. (a) (b) (c) (d) (e)
Sketch the transfer characteristic. Sketch the waveform of v O . Find the average value of v O . Find the peak current in the diode. Find the PIV of the diode.
4.68 Using the exponential diode characteristic, show that for v S and v O both greater than zero, the circuit of Fig. 4.23(a) has the transfer characteristic 0002 0003 0002 0003 v O = v S − v D at iD = 1 mA − VT ln v O /R where v S and v O are in volts and R is in kilohms. Note that this relationship can be used to obtain the voltage transfer characteristic v O vs. v S by finding v S corresponding to various values of v O . 4.69 Consider a half-wave rectifier circuit with a triangular-wave input of 5-V peak-to-peak amplitude and zero average, and with R = 1 k0002. Assume that the diode can be represented by the constant-voltage-drop model with VD = 0.7 V. Find the average value of v O . 4.70 A half-wave rectifier circuit with a 1-k0002 load operates from a 120-V (rms) 60-Hz household supply through a 12-to-1 step-down transformer. It uses a silicon diode that can be modeled to have a 0.7-V drop for any current. What is the peak voltage of the rectified output? For what fraction of the cycle does the diode conduct? What is the average output voltage? What is the average current in the load? 4.71 A full-wave rectifier circuit with a 1-k0002 load operates from a 120-V (rms) 60-Hz household supply through a 6-to-1 transformer having a center-tapped secondary winding. It uses two silicon diodes that can be modeled to have a 0.7-V drop for all currents. What is the peak voltage of the rectified output? For what fraction of a cycle does each diode conduct? What is the average output voltage? What is the average current in the load? 4.72 A full-wave bridge-rectifier circuit with a 1-k0002 load operates from a 120-V (rms) 60-Hz household supply through a 12-to-1 step-down transformer having a single secondary winding. It uses four diodes, each of which can be modeled to have a 0.7-V drop for any current. What is the peak value of the rectified voltage across the load? For what fraction of a cycle does each diode conduct? What is the average voltage across the load? What is the average current through the load? D 4.73 It is required to design a full-wave rectifier circuit using the circuit of Fig. 4.24 to provide an average output voltage of: (a) 10 V (b) 100 V
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 241
D
CHAPTER 4
D
D
D
PROBLEMS
Figure P4.76
In each case find the required turns ratio of the transformer. Assume that a conducting diode has a voltage drop of 0.7 V. The ac line voltage is 120 V rms. D 4.74 Repeat Problem 4.73 for the bridge-rectifier circuit of Fig. 4.25. D 4.75 Consider the full-wave rectifier in Fig. 4.24 when the transformer turns ratio is such that the voltage across the entire secondary winding is 20 V rms. If the input ac line voltage (120 V rms) fluctuates by as much as ±10%, find the required PIV of the diodes. (Remember to use a factor of safety in your design.) 4.76 The circuit in Fig. P4.76 implements a complementary-output rectifier. Sketch and clearly label + − the waveforms of v O and v O . Assume a 0.7-V drop across each conducting diode. If the magnitude of the average of each output is to be 12 V, find the required amplitude of the sine wave across the entire secondary winding. What is the PIV of each diode? 4.77 Augment the rectifier circuit of Problem 4.70 with a capacitor chosen to provide a peak-to-peak ripple voltage of (i) 10% of the peak output and (ii) 1% of the peak output. In each case: (a) (b) (c) (d)
What average output voltage results? What fraction of the cycle does the diode conduct? What is the average diode current? What is the peak diode current?
4.78 Repeat Problem 4.77 for the rectifier in Problem 4.71. 4.79 Repeat Problem 4.77 for the rectifier in Problem 4.72.
D *4.80 It is required to use a peak rectifier to design a dc power supply that provides an average dc output voltage of 12 V on which a maximum of ±1-V ripple is allowed. The rectifier feeds a load of 200 0002. The rectifier is fed from the line voltage (120 V rms, 60 Hz) through a transformer. The diodes available have 0.7-V drop when conducting. If the designer opts for the half-wave circuit: (a) Specify the rms voltage that must appear across the transformer secondary. (b) Find the required value of the filter capacitor. (c) Find the maximum reverse voltage that will appear across the diode, and specify the PIV rating of the diode. (d) Calculate the average current through the diode during conduction. (e) Calculate the peak diode current. D *4.81 Repeat Problem 4.80 for the case in which the designer opts for a full-wave circuit utilizing a center-tapped transformer. D *4.82 Repeat Problem 4.80 for the case in which the designer opts for a full-wave bridge-rectifier circuit. D *4.83 Consider a half-wave peak rectifier fed with a voltage v S having a triangular waveform with 24-V peak-to-peak amplitude, zero average, and 1-kHz frequency. Assume that the diode has a 0.7-V drop when conducting. Let the load resistance R = 100 0002 and the filter capacitor C = 100 μF. Find the average dc output voltage, the time interval during which the diode conducts, the average diode current during conduction, and the maximum diode current.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 4
PROBLEMS
242 Chapter 4 Diodes D *4.84 Consider the circuit in Fig. P4.76 with two equal filter capacitors placed across the load resistors R. Assume that the diodes available exhibit a 0.7-V drop when conducting. Design the circuit to provide ±12-V dc output voltages with a peak-to-peak ripple no greater than 1 V. Each supply should be capable of providing 100-mA dc current to its load resistor R. Completely specify the capacitors, diodes, and the transformer.
(c) v I = −1 V (d) v I = −3 V
4.85 The op amp in the precision rectifier circuit of Fig. P4.85 is ideal with output saturation levels of ±13 V. Assume that when conducting the diode exhibits a constant voltage drop of 0.7 V. Find v − , v O , and v A for:
vI
(a) (b) (c) (d)
vI vI vI vI
= +1 V = +3 V = −1 V = −3 V
0003
D
0002 v0002
D1 R
0002
v0002
D2
0003
vA
Section 4.6: Limiting and Clamping Circuits 4.87 Sketch the transfer characteristic v O versus v I for the limiter circuits shown in Fig. P4.87. All diodes begin conducting at a forward voltage drop of 0.5 V and have voltage drops of 0.7 V when conducting a current iD ≥ 1 mA.
vO
vA R
00033 V RL
R
vI
vO
1 k (a)
Figure P4.85
00033 V 4.86 The op amp in the circuit of Fig. P4.86 is ideal with output saturation levels of ±12 V. The diodes exhibit a constant 0.7-V drop when conducting. Find v − , v A , and v O for: (a) v I = +1 V (b) v I = +3 V
vO
Figure P4.86
Also, find the average output voltage obtained when v I is a symmetrical square wave of 1-kHz frequency, 5-V amplitude, and zero average.
vI
R
vI
1 k000b
vO
(b) Figure P4.87
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 243
1 k000b
the diodes can be represented by the constant-voltage-drop model with VD = 0.7 V. Also assume that the zener voltage is 6.8 V and that rz is negligibly small.
vO
00023 V (c) vI
1 k000b
vO
00023 V (d) Figure P4.87 continued
4.88 The circuits in Fig. P4.87(a) and (d) are connected as follows: The two input terminals are tied together, and the two output terminals are tied together. Sketch the transfer characteristic of the circuit resulting, assuming that the cut-in voltage of the diodes is 0.5 V and their voltage drop when conducting a current iD ≥ 1 mA is 0.7 V.
Figure P4.91
4.89 Repeat Problem 4.88 for the two circuits in Fig. P4.87(a) and (b) connected together as follows: The two input terminals are tied together, and the two output terminals are tied together.
4.92 Design limiter circuits using only diodes and 10-k0002 resistors to provide an output signal limited to the range:
4.90 Sketch and clearly label the transfer characteristic of the circuit in Fig. P4.90 for −15 V ≤ v I ≤ +15 V. Assume that
(a) –0.7 V and above (b) +2.1 V and below (c) ±1.4 V Assume that each diode has a 0.7-V drop when conducting.
Figure P4.90
D
D
D
D
4.93 Design a two-sided limiting circuit using a resistor, two diodes, and two power supplies to feed a 1-k0002 load with nominal limiting levels of ±2.2 V. Use diodes modeled by a constant 0.7 V. In the nonlimiting region, the voltage gain should be at least 0.94 V/V. **4.94 In the circuit shown in Fig. P4.94, the diodes exhibit a 0.7-V drop at 0.1 mA. For inputs over the range of ±5 V, use the diode exponential model to provide a calibrated sketch of the voltages at outputs B and C versus v A . For a 5-V peak,
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
*4.91 Plot the transfer characteristic of the circuit in Fig. P4.91 by evaluating v I corresponding to v O = 0.5 V, 0.6 V, 0.7 V, 0.8 V, 0 V, –0.5 V, –0.6 V, –0.7 V, and –0.8 V. Use the exponential model for the diodes, and assume that they have 0.7-V drops at 1-mA currents. Characterize the circuit as a hard or soft limiter. What is the value of K? Estimate L+ and L− .
CHAPTER 4
vI
PROBLEMS
100-Hz sinusoid applied at A, sketch the signals at nodes B and C.
CHAPTER 4
244 Chapter 4 Diodes
A
00031 V
1 k 5 k B D2
D3
D1
D4
D1 vI
3 k000b
vO D2
C 1 k000b
D3
1 k000b
00022 V
Figure P4.94 Figure P4.95
**4.95 Sketch and label the voltage-transfer characteristic v O versus v I of the circuit shown in Fig. P4.95 over a ±10-V range of input signals. Use the diode exponential model and assume that all diodes are 1-mA units (i.e., each exhibits a 0.7-V drop at a current of 1 mA). What are the slopes of the characteristics at the extreme ±10-V levels?
4.96 A clamped capacitor using an ideal diode with cathode grounded is supplied with a sine wave of 5-V rms. What is the average (dc) value of the resulting output? *4.97 For the circuits in Fig. P4.97, each utilizing an ideal diode (or diodes), sketch the output for the input shown. Label the most positive and most negative output levels. Assume CR 0005 T .
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 245
CHAPTER 4 PROBLEMS
(a)
(e) Figure P4.97
(b)
(f)
(c)
(g)
(d)
(h)
PROBLEMS Computer Simulations Problems Problems identified by the Multisim/PSpice icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion. Instructions to assist in setting up PSPice and Multisim simulations for all the indicated problems can be found in the corresponding files on the website. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
Section 5.1: Device Structure and Physical Operation 5.1 MOS technology is used to fabricate a capacitor, utilizing the gate metallization and the substrate as the capacitor electrodes. Find the area required per 1-pF capacitance for oxide thickness ranging from 2 nm to 10 nm. For a square plate capacitor of 10 pF, what dimensions are needed? 5.2 Calculate the total charge stored in the channel of an 2 NMOS transistor having Cox = 9 fF/μm , L = 0.36 μm, and W = 3.6 μm, and operated at VOV = 0.2 V and VDS = 0 V. 5.3 Use dimensional analysis to show that the units of 0003 2 the process transconductance parameter kn are A/V . What are the dimensions of the MOSFET transconductance parameter kn ? 5.4 An NMOS transistor that is operated with a small v DS is found to exhibit a resistance rDS . By what factor will rDS change in each of the following situations? (a) VOV is doubled. (b) The device is replaced with another fabricated in the same technology but with double the width.
(c) The device is replaced with another fabricated in the same technology but with both the width and length doubled. (d) The device is replaced with another fabricated in a more advanced technology for which the oxide thickness is halved and similarly for W and L (assume μn remains unchanged). D 5.5 An NMOS transistor fabricated in a technology for 0003 2 which kn = 400 μA/V and Vt = 0.5 V is required to operate with a small v DS as a variable resistor ranging in value from 250 0002 to 1 k0002. Specify the range required for the control voltage VGS and the required transistor width W. It is required to use the smallest possible device, as limited by the minimum channel length of this technology (Lmin = 0.18 μm) and the maximum allowed voltage of 1.8 V. 5.6 Sketch a set of iD −v DS characteristic curves for an NMOS transistor operating with a small v DS (in the manner shown in 2 Fig. 5.4). Let the MOSFET have kn = 5 mA/V and Vtn = 0.5 V. Sketch and clearly label the graphs for VGS = 0.5, 1.0, 1.5, 2.0, and 2.5 V. Let VDS be in the range 0 to 50 mV. Give the value of rDS obtained for each of the five values of VGS . Although only a sketch, your diagram should be drawn to scale as much as possible. D 5.7 An n-channel MOS device in a technology for which oxide thickness is 4 nm, minimum channel length is 0.18 μm, 0003 2 kn = 400 μA/V , and Vt = 0.5 V operates in the triode region, with small v DS and with the gate–source voltage in the range 0 V to +1.8 V. What device width is needed to ensure that the minimum available resistance is 1 k0002? 5.8 Consider an NMOS transistor operating in the triode region with an overdrive voltage VOV . Find an expression for the incremental resistance
∂i D rds ≡ 1 ∂ v DS v =V DS
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
DS
Problems 293
2
5.9 An NMOS transistor with kn = 4 mA/V and Vt = 0.5 V is operated with VGS = 1.0 V. At what value of VDS does the transistor enter the saturation region? What value of ID is obtained in saturation?
0003 n
(a) Find Cox and k . (b) For an NMOS transistor with W/L = 20 μm/0.25 μm, calculate the values of VOV , VGS , and VDS min needed to operate the transistor in the saturation region with a dc current ID = 0.5 mA. (c) For the device in (b), find the values of VOV and VGS required to cause the device to operate as a 100-0002 resistor for very small v DS . 5.11 A p-channel MOSFET with a threshold voltage Vtp = −0.7 V has its source connected to ground. (a) What should the gate voltagebe for the device to operate with an overdrive voltage of VOV = 0.4 V? (b) With the gate voltage as in (a), what is the highest voltage allowed at the drain while the device operates in the saturation region? (c) If the drain current obtained in (b) is 0.5 mA, what would the current be for VD = −20 mV and for VD = −2V? 5.12 With the knowledge that μp = 0.4 μn , what must be the relative width of n-channel and p-channel devices having equal channel lengths if they are to have equal drain currents when operated in the saturation mode with overdrive voltages of the same magnitude? 0003
2
5.13 An n-channel device has kn = 100 μA/V , Vt = 0.7 V, and W/L = 20. The device is to operate as a switch for small v DS , utilizing a control voltage v GS in the range 0 V to 5 V. Find the switch closure resistance, rDS , and closure
5.14 Consider an n-channel MOSFET with tox = 6 nm, μn = 2 460 cm /V · s, Vt = 0.5 V, and W/L = 10. Find the drain current in the following cases: (a) (b) (c) (d)
v GS = 2.5 V and v DS = 1 V v GS = 2 V and v DS = 1.5 V v GS = 2.5 V and v DS = 0.2 V v GS = v DS = 2.5 V
*5.15 This problem illustrates the central point in the electronics revolution that has been in effect for the past four decades: By continually reducing the MOSFET size, we are able to pack more devices on an IC chip. Gordon Moore, co-founder of Intel Corporation, predicted this exponential growth of chip-packing density very early in the history of the development of the integrated circuit in the formulation that has become known as Moore’s law. The table on the next page shows four technology generations, each characterized by the minimum possible MOSFET channel length (row 1). In going from one generation to another, both L and tox are scaled by the same factor. The power supply utilized VDD is also scaled by the same factor, to keep the magnitudes of all electrical fields within the device unchanged. Unfortunately, but for good reasons, Vt cannot be scaled similarly. Complete the table entries, noting that row 5 asks for the transconductance parameter of an NMOS transistor with W/L = 10; row 9 asks for the value of ID obtained with VGS = VDS = VDD ; row 10 asks for the power P = VDD ID dissipated in the circuit. An important quantity is the power density, P/A, asked for in row 11. Finally, you are asked to find the number of transistors that can be placed on an IC chip fabricated in each of the technologies in terms of the number obtained with the 0.5-μm technology (n).
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
5.10 Consider a CMOS process for which Lmin = 0.25 μm, 2 tox = 6 nm, μn = 460 cm /V · s, and Vt = 0.5 V.
voltage, VDS , obtained when v GS = 5 V and iD = 1 mA. If μp 0006 0.4 μn , what must W/L be for a p-channel device that provides the same performance as the n-channel device in this application?
CHAPTER 5
Give the values of rds in terms of kn and VOV for VDS = 0, 0.2VOV , 0.5VOV , 0.8VOV , and VOV .
CHAPTER 5
PROBLEMS
294 Chapter 5 MOS Field-Effect Transistors (MOSFETs)
1
L (μm)
0.5
2
tox (nm)
10
3
Cox (fF/μm )
4
kn (μA/V ) 2 (μn = 500 cm / V · s)
5
kn (mA/V ) For W/L = 10
6
Device area, A (μm )
7
VDD (V)
5
8
Vt (V)
0.7
9
ID (mA) For VGS = VDS = VDD
10
P (mW)
11
P/A (mW/μm )
12
Devices per chip
0.25
0.18
0.13
0.5
0.4
0.4
2
0003
2
2
2
2
n
Section 5.2: Current–Voltage Characteristics In the following problems, when λ is not specified, assume it is zero. 5.16 Show that when channel-length modulation is neglected (i.e., λ = 0), plotting iD /kn versus v DS for various values of v OV , and plotting iD /kn versus v OV for v DS ≥ v OV , results in universal representation of the iD −v DS and iD −v GS characteristics of the NMOS transistor. That is, the resulting graphs are both technology and device independent. Furthermore, these graphs apply equally well to the PMOS transistor by a simple relabeling of variables. (How?) What is the slope at v DS = 0
of each of the iD /kn versus v DS graphs? For the iD /kn versus v OV graph, find the slope at a point v OV = VOV . 5.17 An NMOS transistor having Vt = 0.8 V is operated in the triode region with v DS small. With VGS = 1.2 V, it is found to have a resistance rDS of 1 k0002. What value of VGS is required to obtain rDS = 200 0002? Find the corresponding resistance values obtained with a device having twice the value of W. 5.18 A particular MOSFET for which Vtn = 0.5 V and 0003 2 kn (W/L) = 1.6 mA/V is to be operated in the saturation region. If iD is to be 50 μA, find the required v GS and the minimum required v DS . Repeat for iD = 200 μA.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 295
5.21 An NMOS transistor, operating in the linear-resistance region with v DS = 50 mV, is found to conduct 25 μA for v GS = 1 V and 50 μA for v GS = 1.5 V. What is the apparent 0003 2 value of threshold voltage Vt ? If kn = 50 μA/V , what is the device W/L ratio? What current would you expect to flow with v GS = 2 V and v DS = 0.1 V? If the device is operated at v GS = 2 V, at what value of v DS will the drain end of the MOSFET channel just reach pinch-off, and what is the corresponding drain current?
v
v
0003
0003
(a)
(b)
Figure P5.24
5.25 For the circuit in Fig. P5.25, sketch iD versus v S for v S varying from 0 to VDD . Clearly label your sketch.
VDD
5.22 For an NMOS transistor, for which Vt = 0.4 V, operating with v GS in the range of 1.0 V to 1.8 V, what is the largest value of v DS for which the channel remains continuous? 5.23 An NMOS transistor, fabricated with W = 20 μm and 0003 2 L = 1 μm in a technology for which kn = 100 μA/V and Vt = 0.8 V, is to be operated at very low values of v DS as a linear resistor. For v GS varying from 1.0 V to 4.8 V, what range of resistor values can be obtained? What is the available range if (a) the device width is halved? (b) the device length is halved? (c) both the width and length are halved?
iD vS
0002 0003
Figure P5.25
5.26 For the circuit in Fig. P5.26, find an expression for v DS in terms of iD . Sketch and clearly label a graph for v DS versus iD .
5.24 When the drain and gate of a MOSFET are connected together, a two-terminal device known as a “diode-connected transistor” results. Figure P5.24 shows such devices obtained from MOS transistors of both polarities. Show that (a) the i–v relationship is given by 00072 1 0003W0006 i= k v − Vt 2 L (b) the incremental resistance r for a device biased to operate at v = Vt + VOV is given by 0004
0003 W
0002 ∂i 0005 0003 = 1 k VOV r≡1 ∂v L
0002
iD
0002 vDS 0003 Figure P5.26
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
D 5.20 For a particular IC-fabrication process, the transcon0003 2 ductance parameter kn = 400 μA/V , and Vt = 0.5 V. In an application in which v GS = v DS = Vsupply = 1.8 V, a drain current of 2 mA is required of a device of minimum length of 0.18 μm. What value of channel width must the design use?
i
0002
i
CHAPTER 5
5.19 A particular n-channel MOSFET is measured to have a drain current of 0.4 mA at VGS = VDS = 1 V and of 0.1 mA at VGS = VDS = 0.8 V. What are the values of kn and Vt for this device?
PROBLEMS
296 Chapter 5 MOS Field-Effect Transistors (MOSFETs)
CHAPTER 5
Voltage (V) Case
VS
VG
VD
a
+1.0
+1.0
+2.0
b
+1.0
+2.5
+2.0
c
+1.0
+2.5
+1.5
d
+1.0
+1.5
0
e
0
+2.5
+1.0
f
+1.0
+1.0
+1.0
g
−1.0
0
0
h
−1.5
0
0
i
−1.0
0
+1.0
j
+0.5
+2.0
+0.5
VGS
*5.27 The table above lists 10 different cases labeled (a) to (j) for operating an NMOS transistor with Vt = 1 V. In each case the voltages at the source, gate, and drain (relative to the circuit ground) are specified. You are required to complete the table entries. Note that if you encounter a case for which v DS is negative, you should exchange the drain and source before solving the problem. You can do this because the MOSFET is a symmetric device. 5.28 The NMOS transistor in Fig. P5.28 has Vt = 0.4 V and 0003 2 kn (W/L) = 1 mA/V . Sketch and clearly label iD versus v G with v G varying in the range 0 to +1.8 V. Give equations for the various portions of the resulting graph.
VOV
VDS
Region of operation
5.29 Figure P5.29 shows two NMOS transistors operating in saturation at equal VGS and VDS . (a) If the two devices are matched except for a maximum possible mismatch in their W/L ratios of 3%, what is the maximum resulting mismatch in the drain currents? (b) If the two devices are matched except for a maximum possible mismatch in their Vt values of 10 mV, what is the maximum resulting mismatch in the drain currents? Assume that the nominal value of Vt is 0.6 V.
00022.5 V
00021V ID1
iD 00021.0 V
Q1
vG 0002 0003
Figure P5.28
Figure P5.29
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
ID2 Q2
Problems 297
D 5.32 In a particular IC design in which the standard channel length is 1 μm, an NMOS device with W/L of 10 operating at 200 μA is found to have an output resistance of 100 k0002, about 15 of that needed. What dimensional change can be made to solve the problem? What is the new device length? The new device width? The new W/L ratio? What is VA for the standard device in this IC? The new device? D 5.33 For a particular n-channel MOS technology, in which the minimum channel length is 0.5 μm, the associated −1 value of λ is 0.03 V . If a particular device for which L is 1.5 μm operates in saturation at v DS = 1 V with a drain current of 100 μA, what does the drain current become if v DS is raised to 5 V? What percentage change does this represent? What can be done to reduce the percentage by a factor of 2? 5.34 An NMOS transistor is fabricated in a 0.5-μm process 0003 2 0003 having kn = 200 μA/V and VA = 20 V/μm of channel length. If L = 1.5 μm and W = 15 μm, find VA and λ. Find the value of ID that results when the device is operated with an overdrive voltage of 0.5 V and VDS = 2 V. Also, find the value of ro at this operating point. If VDS is increased by 1 V, what is the corresponding change in ID ? VS
VG
VD
a
+2
+2
0
b
+2
+1
0
c
+2
0
0
d
+2
0
+1
e
+2
0
+1.5
f
+2
0
+2
VSG
|VOV |
D 5.36 Consider the circuit in Fig. P5.29 with both transistors perfectly matched but with the dc voltage at the drain of Q1 lowered to +2 V. If the two drain currents are to be matched within 1% (i.e., the maximum difference allowed between the two currents is 1%), what is the minimum required value of 0003 VA ? If the technology is specified to have VA = 100 V/μm, what is the minimum channel length the designer must use? 5.37 Complete the missing entries in the following table, which describes characteristics of suitably biased NMOS transistors: MOS
λ (V−1 ) VA (V) ID (mA) ro (k0002)
1
2
3
4
0.02 20 0.5
100 25
0.1 100
500
5.38 A PMOS transistor has kp0003 (W/L) = 100 μA/V2 , Vt = −1.0 V, and λ = –0.02 V−1 . The gate is connected to ground and the source to +5 V. Find the drain current for v D = +4 V, +2 V, +1 V, 0 V, and –5 V. 5.39 A p-channel transistor for which Vt = 0.8 V and VA = 40 V operates in saturation with v GS = 3 V,v DS = 4 V, and iD = 3 mA. Find corresponding signed values for v GS , v SG , v DS , v SD , Vt , VA , λ, and kp0003 (W/L). 5.40 The table below lists the terminal voltages of a PMOS transistor in six cases, labeled a, b, c, d, e, and f. The transistor has Vtp = −1 V. Complete the table entries. VSD
Region of operation
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
5.31 A particular MOSFET has VA = 20 V. For operation at 0.1 mA and 1 mA, what are the expected output resistances? In each case, for a change in v DS of 1 V, what percentage change in drain current would you expect?
5.35 If in an NMOS transistor, both W and L are quadrupled and VOV is halved, by what factor does ro change?
CHAPTER 5
5.30 For a particular MOSFET operating in the saturation region at a constant v GS , iD is found to be 0.5 mA for v DS = 1 V and 0.52 mA for v DS = 2 V. What values of ro , VA , and λ correspond?
CHAPTER 5
PROBLEMS
298 Chapter 5 MOS Field-Effect Transistors (MOSFETs) 5.41 The PMOS transistor in Fig. P5.41 has Vtp = −0.5 V. As the gate voltage v G is varied from +3 V to 0 V, the transistor moves through all of its three possible modes of operation. Specify the values of v G at which the device changes modes of operation.
saturated-mode operation of each transistor at ID = I? In the latter limiting situation, what do V1 , V2 , V3 , and V4 become?
00021 V
00022.5 V
00021 V
Q2
I
00023 V
V2
V1 I
Q1
vG 0002 0003
00021 V 00031.5 V
Figure P5.41
(a) 00022.5 V
*5.42 Various NMOS and PMOS transistors, numbered 1 to 4, are measured in operation, as shown in the table at the bottom of the page. For each transistor, find the values of μCox W/L and Vt that apply and complete the table, with V in volts, I in μA, and μCox W/L in μA/V2 . Assume λ = 0. *5.43 All the transistors inthe circuits shown in Fig. P5.43 have the same values of Vt , k 0003 , W/L, and λ. Moreover, λ is VGS = negligibly small. All operate in saturation at I = I and D VDS = 1 V. Find the voltages V1 , V2 , V3 , and V4 . If Vt = 0.5 V and I = 0.1 mA, how large a resistor can be inserted in series with each drain while maintaining saturation? If the current source I requires at least 0.5 V between its terminals to operate properly, what is the largest resistor that can be placed in series with each MOSFET source while ensuring
Case a b c d
Transistor
VS
VG
1 1 2 2 3 3 4 4
0 0 5 5 5 5 −2 −4
1 1.5 3 2 3 2 0 0
VD 2.5 2.5 −4.5 −0.5 4 0 0 −3
(b) 00021.25 V
Q4
I
V4
V3 I
Q3
00031.25 V (c)
(d)
Figure P5.43
ID
Type
Mode
μCox W/L
100 400 50 450 200 800 72 270
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Vt
Problems 299
Note: If λ is not specified, assume it is zero.
00021 V
00021.3 V
RD
RD
Figure P5.47
RS D 5.48 It is required to operate the transistor in the circuit of Fig. P5.47 at the edge of saturation with ID = 0.1 mA. If Vt = 0.4 V, find the required value of RD .
00031 V Figure P5.44
5.45 The NMOS transistor in the circuit of Fig. P5.44 has 2 Vt = 0.4 V and kn = 4 mA/V . The voltages at the source and the drain are measured and found to be −0.6 V and +0.2 V, respectively. What current ID is flowing, and what must the values of RD and RS be? What is the largest value for RD for which ID remains unchanged from the value found?
D 5.49 The PMOS transistor in the circuit of Fig. P5.49 2 has Vt = −0.5 V, μp Cox = 100 μA/V , L = 0.18 μm, and λ = 0. Find the values required for W and R in order to establish a drain current of 180 μA and a voltage VD of 1 V.
1.8 V
D 5.46 For the circuit in Fig. E5.10, assume that Q1 and Q2 are matched except for having different widths, W1 and 0003 2 W2 . Let Vt = 0.5 V, kn = 0.4 mA/V , L1 = L2 = 0.36 μm, W1 = 1.44 μm, and λ = 0. (a) Find the value of R required to establish a current of 50 μA in Q1 . (b) Find W2 and R2 so that Q2 operates at the edge of saturation with a current of 0.5 mA. 0003
5.47 The transistor in the circuit of Fig. P5.47 has kn = 2 0.4 mA/V , Vt = 0.4 V, and λ = 0. Show that operation at the
Figure P5.49
D 5.50 The NMOS transistors in the circuit of Fig. P5.50 2 have Vt = 0.5 V, μn Cox = 250 μA/V , λ = 0, and L1 = L2 = 0.25 μm. Find the required values of gate width for each of Q1
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
D 5.44 Design the circuit of Fig. P5.44 to establish a drain current of 0.1 mA and a drain voltage of +0.3 V. The 2 MOSFET has Vt = 0.5 V, μn Cox = 400 μA/V , L = 0.4 μm, and W = 5 μm. Specify the required values for RS and RD .
edge of saturation is obtained when the following condition is satisfied: 0003 0004 W RD 0006 2.5 k0002 L
CHAPTER 5
Section 5.3: MOSFET Circuits at DC
PROBLEMS
300 Chapter 5 MOS Field-Effect Transistors (MOSFETs) and Q2 , and the value of R, to obtain the voltage and current values indicated.
00022.5 V
the drain current is 0.5 mA and the drain voltage is +7 V. If the transistor is replaced with another having Vt = 1.5 V with 0003 2 kn (W/L) = 1.5 mA/V , find the new values of ID and VD . Comment on how tolerant (or intolerant) the circuit is to changes in device parameters.
CHAPTER 5
0003
0.5 mA 00021.8 V
00021.0 V
D 5.53 Using a PMOS transistor with Vt = −1.5 V, kp 2 (W/L) = 4 mA/V , and λ = 0, design a circuit that resembles that in Fig. 5.24(a). Using a 10-V supply, design for a gate voltage of +6 V, a drain current of 0.5 mA, and a drain voltage of +5 V. Find the values of RS and RD . Also, find the values of the resistances in the voltage divider feeding the gate, assuming a 1-μA current in the divider. 0003
5.54 The MOSFET in Fig. P5.54 has Vt = 0.4 V, kn = 2 500 μA/V , and λ = 0. Find the required values of W/L and of R so that when v I = VDD = +1.3 V, rDS = 50 0002 and v O = 50 mV.
Figure P5.50
D 5.51 The NMOS transistors in the circuit of Fig. P5.51 2 have Vt = 0.5 V, μn Cox = 90 μA/V , λ = 0, and L1 = L2 = L3 = 0.5 μm. Find the required values of gate width for each of Q1 , Q2 , and Q3 to obtain the voltage and current values indicated.
VDD
R vO
00022.5 V 90 A
vI
00021.5 V Figure P5.54
00020.8 V
Figure P5.51
5.52 Consider the circuit of Fig. 5.24(a). In Example 5.5 0003 2 it was found that when Vt = 1 V and kn (W/L) = 1 mA/V ,
5.55 In the circuits shown 0003 in Fig. P5.55, 2transistors are characterized by Vt = 1 V, k W/L = 4 mA/V , and λ = 0. (a) Find the labeled voltages V1 through V7 . (b) In each of the circuits, replace the current source with a resistor. Select the resistor value to yield a current as close to that of the current source as possible, while using resistors specified in the 1% table provided in Appendix J.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 301
00025 V
2 k
CHAPTER 5
00025 V 00025 V
00025 V V2
V1
V2
10 A
V3
100 A
2 mA (a)
(b)
00035 V (a)
00025 V
(b)
00025 V
00025 V 10 A
V3
V4
2 mA 1 mA V4
V6
(c) V5
V7
1.5 k
00025 V
2 mA 1 mA
00035 V (c)
(d)
400 k
V5
(d)
V6
Figure P5.55
5.56 For each of the circuits in Fig. P5.56, find the labeled 0003 2 node voltages. For all transistors, kn (W/L) = 0.5 mA/V , Vt = 0.8 V, and λ = 0.
(e)
(f)
Figure P5.56 continued
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
V1
2 mA
CHAPTER 5
PROBLEMS
302 Chapter 5 MOS Field-Effect Transistors (MOSFETs) 00025 V
000210 V 0002
00025 V 0003
2.2 k
VSG
0002 VSD 0003
V8
V7
400 k
R
00035 V (g)
(h)
I
Figure P5.56 continued
5.57 For each of the circuits shown in Fig. P5.57, find the labeled node voltages. The NMOS transistors have Vt = 0.9 V 0003 2 and kn (W/L) = 1.5 mA/V .
5V
2.5 V
5V
Figure P5.58
5.59 For the circuits in Fig. P5.59, μn Cox = 3 μp Cox = 2 270 μA/V , Vt = 0.5 V, λ = 0, L = 1 μm, and W = 3 μm, unless otherwise specified. Find the labeled currents and voltages.
3V
1k
3V
V3
Q1 Q1
V1
I3
I1 V4
V4
V2
Q2 Q2 V2 V5 1k 1k
(a)
(b)
3V 2.5 V (a)
(b) W = 9 μm
Figure P5.57
I6
*5.58 For the circuit in Fig. P5.58:
V5
(a) Show that for the PMOS transistor to operate in saturation, the following condition must be satisfied: IR ≤ | Vtp | (b) If the transistor is specified to have |Vtp | = 1 V and 2 kp = 0.2 mA/V , and for I = 0.1 mA, find the voltages VSD and VSG for R = 0, 10 k0002, 30 k0002, and 100 k0002.
(c)
Figure P5.59
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 303
00025 V
Section 5.4: The Body Effect and Other Topics 5.62 In a particular application, an n-channel MOSFET operates with VSB in the range 0 V to 4 V. If Vt0 is nominally 1/2 1.0 V, find the range of Vt that results if γ = 0.5 V and 2φf = 0.6 V. If the gate oxide thickness is increased by a factor of 4, what does the threshold voltage become?
Q4
Q2 I2
V2 Q3
Q1
Figure P5.60
*5.64 (a) Using the expression for iD in saturation and neglecting the channel-length modulation effect (i.e., let λ = 0), derive an expression for the per unit change in iD 000e0006 0007 000f 0003 per °C ∂iD /iD /∂T in terms of the per unit change in kn 000e0006 0003 0003 0007 000f per °C ∂kn /kn /∂T , the temperature coefficient of Vt in 0006 0007 V/°C ∂Vt /∂T , and VGS and Vt . (b) If Vt decreases by 2 mV for every °C rise in temperature, 0003 find the temperature coefficient of kn that results in iD decreasing by 0.2%/°C when the NMOS transistor with Vt = 1 V is operated at VGS = 5 V. 0003
5.61 In the circuit of Fig. P5.61, transistors Q1 and Q2 have 0003 Vt = 0.7 V, and the process transconductance parameter kn = 2 125 μA/V . Find V1 , V2 , and V3 for each of the following cases: (a) (W/L)1 = (W/L)2 = 20 (b) (W/L)1 = 1.5(W/L)2 = 20
00022.5 V
20 k
20 k
V2
V1 Q1
Q2
V3 200 A
Figure P5.61
5.65 A depletion-type n-channel MOSFET with kn W/L = 2 2 mA/V and Vt = −3 V has its source and gate grounded. Find the region of operation and the drain current for v D = 0.1 V, 1 V, 3 V, and 5 V. Neglect the channel-length-modulation effect. 5.66 For a particular depletion-mode NMOS device, Vt = 0003 2 −1 −2 V, kn W/L = 200 μA/V , and λ = 0.02 V . When operated at v GS = 0, what is the drain current that flows for v DS = 1 V, 2 V, 3 V, and 10 V? What does each of these currents become if the device width is doubled with L the same? With L also doubled? *5.67 Neglecting the channel-length-modulation effect, show that for the depletion-type NMOS transistor of Fig. P5.67, the i−v relationship is given by 0007 0006 2 1 0003 i = kn (W/L) v − 2Vt v for v ≥ Vt 2 1 0003 2 i = − kn (W/L)Vt for v ≤ Vt 2 (Recall that Vt is negative.) Sketch the i−v relationship for the 0003 2 case: Vt = −2 V and kn (W/L) = 2 mA/V .
i 0002 v
0003
Figure P5.67
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
5.63 A p-channel transistor operates in saturation with its 1/2 source voltage 3 V lower than its substrate. For γ = 0.5 V , 2φf = 0.75 V, and Vt0 = −0.7 V, find Vt .
CHAPTER 5
of Fig. P5.60, *5.60 For the devices in the circuit Vt = 1 V, λ = 0, μn Cox = 50 μA/V2 , L = 1 μm, and W = 10 μm. Find V2 and I2 . How do these values change if Q3 and Q4 are made to have W = 100 μm?
PROBLEMS Computer Simulations Problems Problems identified by the Multisim/PSpice icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion. Instructions to assist in setting up PSPice and Multisim simulations for all the indicated problems can be found in the corresponding files on the website. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
Section 6.1: Device Structure and Physical Operation 6.1 The terminal voltages of various npn transistors are measured during operation in their respective circuits with the following results: Case
E
B
C
1 2 3 4 5 6
0 0 −0.7 −0.7 1.3 0
0.7 0.8 0 0 2.0 0
0.7 0.1 1.0 −0.6 5.0 5.0
Mode
In this table, where the entries are in volts, 0 indicates the reference terminal to which the black (negative) probe of the voltmeter is connected. For each case, identify the mode of operation of the transistor. 6.2 Two transistors, fabricated with the same technology but having different junction areas, when operated at a base-emitter voltage of 0.75 V, have collector currents of 0.5 mA and 2 mA. Find IS for each device. What are the relative junction areas? 6.3 In a particular technology, a small BJT operating at v BE = 30VT conducts a collector current of 200 μA. What is the corresponding saturation current? For a transistor in the same technology but with an emitter junction that is 32 times larger, what is the saturation current? What current will this transistor conduct at v BE = 30VT ? What is the base–emitter voltage of the latter transistor at iC = 1 mA? Assume active-mode operation in all cases. 6.4 Two transistors have EBJ areas as follows: AE1 = 200 μm × 200 μm and AE 2 = 0.4 μm × 0.4 μm. If the two
transistors are operated in the active mode and conduct equal collector currents, what do you expect the difference in their v BE values to be? 6.5 Find the collector currents that you would expect for operation at v BE = 700 mV for transistors for which IS = 10−13 A and IS = 10−18 A. For the transistor with the larger EBJ, what is the v BE required to provide a collector current equal to that provided by the smaller transistor at v BE = 700 mV? Assume active-mode operation in all cases. 6.6 In this problem, we contrast two BJT integrated-circuit fabrication technologies: For the “old” technology, a typical npn transistor has IS = 2 × 10−15 A, and for the “new” technology, a typical npn transistor has IS = 2 × 10−18 A. These typical devices have vastly different junction areas and base width. For our purpose here we wish to determine the v BE required to establish a collector current of 1 mA in each of the two typical devices. Assume active-mode operation. 6.7 Consider an npn transistor whose base–emitter drop is 0.76 V at a collector current of 5 mA. What current will it conduct at v BE = 0.70 V? What is its base–emitter voltage for iC = 5 μA? 6.8 In a particular BJT, the base current is 10 μA, and the collector current is 800 μA. Find β and α for this device. 6.9 Find the values of β that correspond to α values of 0.5, 0.8, 0.9, 0.95, 0.98, 0.99, 0.995, and 0.999. 6.10 Find the values of α that correspond to β values of 1, 2, 10, 20, 50, 100, 200, 500, and 1000. *6.11 Show that for a transistor with α close to unity, if α changes by a small per-unit amount (0006α/α), the corresponding per-unit change in β is given approximately by 0002 0003 0006β 0006α 0002β β α Now, for a transistor whose nominal β is 100, find the percentage change in its α value corresponding to a drop in its β of 10%. 6.12 An npn transistor of a type whose β is specified to range from 50 to 300 is connected in a circuit with emitter grounded, collector at + 10 V, and a current of 10 μA injected into the base. Calculate the range of collector and emitter currents that can result. What is the maximum power dissipated in the transistor? (Note: Perhaps you can see why this is a bad way to establish the operating current in the collector of a BJT.)
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 6
PROBLEMS
356 Chapter 6 Bipolar Junction Transistors (BJTs) 6.13 A BJT is specified to have IS = 5 × 10−15 A and β that falls in the range of 50 to 200. If the transistor is operated in the active mode with v BE set to 0.700 V, find the expected range of iC , iB , and iE . 6.14 Measurements made on a number of transistors operating in the active mode with iE = 1 mA indicate base currents of 10 μA, 20 μA, and 50 μA. For each device, find iC , β, and α. 6.15 Measurements of VBE and two terminal currents taken on a number of npn transistors operating in the active mode are tabulated below. For each, calculate the missing current value as well as α, β, and IS as indicated by the table. Transistor
a
b
VBE (mV) IC (mA) IB (μA) IE (mA) α β IS
700 1.000 10
690 1.000 1.020
c
580 5 0.235
and across CBJ when each is forward biased and conducting a current of 1 mA. Also find the forward current each junction would conduct when forward biased with 0.5 V. *6.20 We wish to investigate the operation of the npn transistor in saturation using the model of Fig. 6.9. Let IS = 10−15 A, v BE = 0.7 V, β = 100, and ISC /IS = 100. For each of three values of v CE (namely, 0.4 V, 0.3 V, and 0.2 V), find v BC , iBC , iBE , iB , iC , and iC /iB . Present your results in tabular form. Also find v CE that results in iC = 0.
d
e
780 10.10 120
820
*6.21 Use Eqs. (6.14), (6.15), and (6.16) to show that an npn transistor operated in saturation exhibits a collector-to-emitter voltage, VCEsat , given by 0002 0003 ISC 1 + β forced VCEsat = VT ln IS 1 − β forced /β
1050 75.00
Use this relationship to evaluate VCEsat for β forced = 50, 10, 5, and 1 for a transistor with β = 100 and with a CBJ area 100 times that of the EBJ. Present your results in a table.
6.16 When operated in the active mode, a particular npn BJT conducts a collector current of 1 mA and has v BE = 0.70 V and iB = 10 μA. Use these data to create specific transistor models of the form shown in Fig. 6.5(a) to (d). 6.17 Using the npn transistor model of Fig. 6.5(b), consider the case of a transistor for which the base is connected to ground, the collector is connected to a 5-V dc source through a 2-k0004 resistor, and a 2-mA current source is connected to the emitter with the polarity so that current is drawn out of the emitter terminal. If β = 100 and IS = 5 × 10−15 A, find the voltages at the emitter and the collector and calculate the base current. D 6.18 Consider an npn transistor operated in the active mode and represented by the model of Fig. 6.5(d). Let the transistor be connected as indicated by the equivalent circuit shown in Fig. 6.6(b). It is required to calculate the values of RB and RC that will establish a collector current IC of 0.5 mA and a collector-to-emitter voltage VCE of 1 V. The BJT is specified to have β = 50 and IS = 5 × 10−15 A. 6.19 An npn transistor has a CBJ with an area 100 times that of the EBJ. If IS = 10−15 A, find the voltage drop across EBJ
6.22 Consider the pnp large-signal model of Fig. 6.11(b) applied to a transistor having IS = 10−14 A and β = 50. If the emitter is connected to ground, the base is connected to a current source that pulls 10 μA out of the base terminal, and the collector is connected to a negative supply of −5 V via a 8.2-k0004 resistor, find the collector voltage, the emitter current, and the base voltage. 6.23 A pnp transistor has v EB = 0.7 V at a collector current of 1 mA. What do you expect v EB to become at iC = 10 mA? At iC = 100 mA? 6.24 A pnp transistor modeled with the circuit in Fig. 6.11 (b) is connected with its base at ground, collector at –2.0 V, and a 1-mA current is injected into its emitter. If the transistor is said to have β = 10, what are its base and collector currents? In which direction do they flow? If IS = 10−15 A, what voltage results at the emitter? What does the collector current become if a transistor with β = 1000 is substituted? (Note: The fact that the collector current changes by less than 10% for a large change in β illustrates that this is a good way to establish a specific collector current.) 6.25 A pnp power transistor operates with an emitter-to-collector voltage of 5 V, an emitter current of 5 A, and VEB = 0.8 V. For β = 20, what base current is required? What is IS for this transistor? Compare the emitter–base junction area of this transistor with that of a small-signal
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 357
Section 6.2: Current–Voltage Characteristics 6.28 For the circuits in Fig. P6.28, assume that the transistors have very large β. Some measurements have been made on these circuits, with the results indicated in the figure. Find the values of the other labeled voltages and currents.
6.26 While Fig. 6.5 provides four possible large-signal equivalent circuits for the npn transistor, only two equivalent circuits for the pnp transistor are provided in Fig. 6.11. Supply the missing two.
5.6 k 5k
2
9.1 k
V3
I5
V7
15 k
4V
V4
V2
0V
0.7 V
2.4 k
I6
20 k
5k
(a)
(b)
(c)
3k
(d)
Figure P6.28
7V 6.3 V 45 k + 3.0 V
200 k 2k
(a)
27 k⍀
750 ⍀
(b)
Figure P6.29
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
1.5 k
(c)
PROBLEMS
6.29 Measurements on the circuits of Fig. P6.29 produce labeled voltages as indicated. Find the value of β for each transistor.
6.27 By analogy to the npn case shown in Fig. 6.9, give the equivalent circuit of a pnp transistor in saturation.
CHAPTER 6
transistor that conducts iC = 1 mA with v EB = 0.70 V. How much larger is it?
CHAPTER 6
PROBLEMS
358 Chapter 6 Bipolar Junction Transistors (BJTs) 6.30 A very simple circuit for measuring β of an npn transistor is shown in Fig. P6.30. In a particular design, VCC is provided by a 9-V battery; M is a current meter with a 50-μA full scale and relatively low resistance that you can neglect for our purposes here. Assuming that the transistor has VBE = 0.7 V at IE = 1 mA, what value of RC would establish a resistor current of 1 mA? Now, to what value of β does a meter reading of full scale correspond? What is β if the meter reading is 1/5 of full scale? 1/10 of full scale?
D 6.33 Examination of the table of standard values for resistors with 5% tolerance in Appendix J reveals that the closest values to those found in the design of Example 6.2 are 5.1 k0004 and 6.8 k0004. For these values, use approximate calculations (e.g., VBE 0002 0.7 V and α 0002 1) to determine the values of collector current and collector voltage that are likely to result. D 6.34 Design the circuit in Fig. P6.34 to establish IC = 0.2 mA and VC = 0.5 V. The transistor exhibits v BE of 0.8 V at iC = 1 mA, and β = 100.
VCC
1.5 V RC
RC
M IC
VC
RE Figure P6.30
1.5 V 6.31 Repeat Exercise 6.13 for the situation in which the power supplies are reduced to ±2.5 V. D 6.32 Design the circuit in Fig. P6.32 to establish a current of 0.5 mA in the emitter and a voltage of −0.5 V at the collector. The transistor v EB = 0.64 V at IE = 0.1 mA, and β = 100. To what value can RC be increased while the collector current remains unchanged?
Figure P6.34
6.35 For each of the circuits shown in Fig. P6.35, find the emitter, base, 0006 and 0006 collector voltages and currents. Use β = 50, but assume 0006VBE 0006 = 0.8 V independent of current level.
1.5 V
1.5 V
2.7 k
2.5 V
RE
2k
Q1
Q2
2.7 k
RC
1.5 V (a)
2.5 V
2k
Figure P6.32
Figure P6.35
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
1.5 V (b)
Problems 359
8.2 k
10 k 1.5 V
1.0 V
5.6 k
(c)
4.7 k
*6.42 In the circuit shown in Fig. P6.42, current source I is 1.1 mA, and at 25°C v BE = 680 mV at iE = 1 mA. At 25°C with β = 100, what currents flow in R1 and R2 ? What voltage would you expect at node E? Noting that the temperature coefficient of v BE for IE constant is −2 mV/°C, what is the TC of v E ? For an ambient temperature of 75°C, what voltage would you expect at node E? Clearly state any simplifying assumptions you make.
(d)
Figure P6.35 continued
6.36 The current ICBO of a small transistor is measured to be 10 nA at 25°C. If the temperature of the device is raised to 125°C, what do you expect ICBO to become?
R2 68 k
R1 6.8 k
6.37 Augment the model of the npn BJT shown in Fig. 6.19(a) by a current source representing ICBO . Assume that ro is very large and thus can be neglected. In terms of this addition, what do the terminal currents iB , iC , and iE become? If the base lead is open-circuited while the emitter is connected to ground, and the collector is connected to a positive supply, find the emitter and collector currents.
E I
Figure P6.42
6.38 A BJT whose emitter current is fixed at 1 mA has a base–emitter voltage of 0.70 V at 25°C. What base–emitter voltage would you expect at 0°C? At 100°C? 6.39 A particular pnp transistor operating at an emitter current of 0.5 mA at 20°C has an emitter–base voltage of 692 mV. (a) What does v EB become if the junction temperature rises to 50°C? (b) If the transistor is operated at a fixed emitter–base voltage of 700 mV, what emitter current flows at 20°C? At 50°C? 6.40 Consider a transistor for which the base–emitter voltage drop is 0.7 V at 10 mA. What current flows for v BE = 0.5 V? Evaluate the ratio of the slopes of the iC –v BE curve at v BE = 700 mV and at v BE = 500 mV. The large ratio confirms the point that the BJT has an “apparent threshold” at v BE 0002 0.5 V.
6.43 For a particular npn transistor operating at a v BE of 680 mV and IC = 1 mA, the iC –v CE characteristic has a slope −5 of 0.8 × 10 0002. To what value of output resistance does this correspond? What is the value of the Early voltage for this transistor? For operation at 10 mA, what would the output resistance become? 6.44 For a BJT having an Early voltage of 50 V, what is its output resistance at 1 mA? At 100 μA? 6.45 Measurements of the iC –v CE characteristic of a small-signal transistor operating at v BE = 710 mV show that iC = 1.1 mA at v CE = 5 V and that iC = 1.3 mA at v CE = 15 V. What is the corresponding value of iC near saturation? At what value of v CE is iC = 1.2 mA? What is the value of the Early voltage for this transistor? What is the output resistance that corresponds to operation at v BE = 710 mV?
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
Q4
Q3
6.41 Use Eq. (6.18) to plot iC versus v CE for an npn transistor −15 having IS = 10 A and VA = 100 V. Provide curves for v BE = 0.65, 0.70, 0.72, 0.73, and 0.74 volts. Show the characteristics for v CE up to 15 V.
CHAPTER 6
3V
3V
CHAPTER 6
PROBLEMS
360 Chapter 6 Bipolar Junction Transistors (BJTs) 5V
6.46 Give the pnp equivalent circuit models that correspond to those shown in Fig. 6.19 for the npn case. 6.47 A BJT operating at iB = 10 μA and iC = 1.0 mA undergoes a reduction in base current of 1.0 μA. It is found that when v CE is held constant, the corresponding reduction in collector current is 0.08 mA. What are the values of β and the incremental β or β ac that apply? If the base current is increased from 10 μA to 12 μA and v CE is increased from 8 V to 10 V, what collector current results? Assume VA = 100 V.
RB
10 k
VC 1k
6.48 For the circuit in Fig. P6.48 let VCC = 10 V, RC = 1 k0004, and RB = 10 k0004. The BJT has β = 50. Find the value of VBB that results in the transistor operating (a) in the active mode with VC = 2 V; (b) at the edge of saturation; (c) deep in saturation with β forced = 10. Assume VBE 0002 0.7 V.
Figure P6.50
Section 6.3: BJT Circuits at DC 6.51 The transistor in the circuit of Fig. P6.51 has a very high β. Find VE and VC for VB (a) +2.0 V, (b) +1.7 V, and (c) 0 V.
VCC
IC
VBB
3V
RC 1k VC
RB
VB
VC
VE 1k
Figure P6.48
D *6.49 Consider the circuit of Fig. P6.48 for the case VBB = VCC . If the BJT is saturated, use the equivalent circuit of Fig. 6.21 to derive an expression for β forced in terms of VCC 0007 and RB /RC . Also derive an expression for the total power dissipated in the circuit. For VCC = 5 V, design the circuit to obtain operation at a forced β as close to 10 as possible while limiting the power dissipation to no larger than 20 mW. Use 1% resistors (see Appendix J).
6.52 The transistor in the circuit of Fig. P6.51 has a very high β. Find the highest value of VB for which the transistor still operates in the active mode. Also, find the value of VB for which the transistor operates in saturation with a forced β of 2.
6.50 The pnp transistor in the circuit in Fig. P6.50 has β = 50. Show that the BJT is operating in the saturation mode and find β forced and VC . To what value should RB be increased in order for the transistor to operate at the edge of saturation?
6.53 Consider the operation of the circuit shown in Fig. P6.53 for VB at –1 V, 0 V, and +1 V. Assume that β is very high. What values of VE and VC result? At what value of VB does the emitter current reduce to one-tenth of
Figure P6.51
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 361
6.56 A single measurement indicates the emitter voltage of the transistor in the 0006circuit 0006 of Fig. P5.56 to be 1.0 V. Under the assumption that 0006VBE 0006 = 0.7 V, what are VB , IB , IE , IC , VC , β, and α ? (Note: Isn’t it surprising what a little measurement can lead to?)
1k VC VB VE
3V
1k
5k 3V
VE
Figure P6.53
6.54 For the transistor shown in Fig. P6.54, assume α 00021 and v BE = 0.5 V at the edge of conduction. What are the values of VE and VC for VB = 0 V? For what value of VB does the transistor cut off? Saturate? In each case, what values of VE and VC result?
VB 50 k
VC 5k 3V
+5 V Figure P6.56
4 mA VC 1k VB
VE 2 mA
–5 V Figure P6.54
1k
D 6.57 Design a circuit using a pnp transistor for which α 0002 1 using two resistors connected appropriately to ±3 V so that IE = 0.5 mA and VBC = 1 V. What exact values of RE and RC would be needed? Now, consult a table of standard 5% resistor values (e.g., that provided in Appendix J) to select suitable practical values. What values of resistors have you chosen? What are the values of IE and VBC that result? 6.58 In the circuit shown in Fig. P6.58, the transistor has β = 40. Find the values of VB , VE , and VC . If RB is raised to 100 k0004, what voltages result? With RB = 100 k0004, what value of β would return the voltages to the values first calculated?
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
3V
D 6.55 Consider the circuit in Fig. P6.51 with the base voltage VB obtained using a voltage divider across the 3-V supply. Assuming the transistor β to be very large (i.e., ignoring the base current), design the voltage divider to obtain VB = 1.2 V. Design for a 0.1-mA current in the voltage divider. Now, if the BJT β = 100, analyze the circuit to determine the collector current and the collector voltage.
CHAPTER 6
its value for VB = 0 V? For what value of VB is the transistor just at the edge of conduction? (v BE = 0.5 V) What values of VE and VC correspond? For what value of VB does the transistor reach the edge of saturation? What values of VC and VE correspond? Find the value of VB for which the transistor operates in saturation with a forced β of 2.
362 Chapter 6 Bipolar Junction Transistors (BJTs)
CHAPTER 6
PROBLEMS
3V
6.61 For the circuits in Fig. P6.61, find values for the labeled node voltages and branch currents. Assume β to be very high.
RE 2.2 k VE
3V
VB
RB 20 k
VC
3V
3.6 k
3.6 k
RC 2.2 k
V3
V2 43 k
3V
I4
V1
Figure P6.58
4.7 k 0.5 mA
6.59 In the circuit shown in Fig. P6.58, the transistor has β = 50. Find the values of VB , VE , and VC , and verify that the transistor is operating in the active mode. What is the largest value that RC can have while the transistor remains in the active mode?
3V (b)
(a)
6.60 For the circuit in Fig. P6.60, find VB , VE , and VC for RB = 100 k0004, 10 k0004, and 1 k0004. Let β = 100.
3V
3V
6.2 k
3.6 k V7 43 k
V8
0.75 V 110 k
V6
V9
V5 10 k
4.7 k
3V
3V (c) Figure P6.60
Figure P6.61
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
(d)
Problems 363
6.2 k
180 k
V11
D 6.64 The pnp has β = 50. Find What happens if having β = 100? case.
transistor in the circuit of Fig. P6.64 the value for RC to obtain VC = +2 V. the transistor is replaced with another Give the value of VC in the latter
PROBLEMS
3V
V10 V12
300 k 10 k
3V (e) Figure P6.61 continued
Figure P6.64
*6.62 Repeat the analysis of the circuits in Problem 6.61 using β = 100. Find all the labeled node voltages and branch currents.
***6.65 Consider the circuit shown in Fig. P6.65. It resembles that in Fig. 6.30 but includes other features. First, note diodes D1 and D2 are included to make design (and analysis) easier and to provide temperature compensation for the emitter–base voltages of Q1 and Q2 . Second, note resistor R, whose purpose is to provide feedback 0006 negative 0006 (more on this later in the book!). Using 0006VBE 0006 and VD = 0.7 V independent of current, and β = ∞, find the voltages VB1 , VE1 , VC1 , VB2 , VE2 , and VC2 , initially with R open-circuited and then with R connected. Repeat for β = 100, with R open-circuited initially, then connected.
D **6.63 It is required to design the circuit in Fig. P6.63 so that a current of 1 mA is established in the emitter and a voltage of −1 V appears at the collector. The transistor type used has a nominal β of 100. However, the β value can be as low as 50 and as high as 150. Your design should ensure that the specified emitter current is obtained when β = 100 and that at the extreme values of β the emitter current does not change by more than 10% of its nominal value. Also, design for as large a value for RB as possible. Give the values of RB , RE , and RC to the nearest kilohm. What is the expected range of collector current and collector voltage corresponding to the full range of β values?
9V
2k
+5V
80 k
100
D2 Q2
E
Q1 R
D1
2k C
40 k
2k
–5V Figure P6.63
CHAPTER 6
3V
Figure P6.65
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
100
CHAPTER 6
PROBLEMS
364 Chapter 6 Bipolar Junction Transistors (BJTs) *6.66 For the circuit shown in Fig. P6.66, find the labeled node voltages for: (a) β = ∞ (b) β = 100
are 0.5 mA, 0.5 mA, and 1 mA, respectively, and V3 = 0, V5 = −2 V, and V7 = 1 V. For each resistor, select the nearest standard value utilizing the table of standard values for 5% resistors in Appendix J. Now, for β = 100, find the values of V3 , V4 , V5 , V6 , and V7 .
3V
9.1 k
*6.68 For the circuit in Fig. P6.68, find VB and VE for v I = 0 V, +2 V, –2.5 V, and –5 V. The BJTs have β = 50.
5.1 k
V2 V1
V5
Q1
100 k
2.5 V
Q2
V3
V4
9.1 k 4.3 k
3V Figure P6.66
D *6.67 Using β = ∞, design the circuit shown in Fig. P6.67 so that the emitter currents of Q1 , Q2 , and Q3
2.5 V Figure P6.68
5V
R3 R2
R5 V4 V7
Q2 Q1
V3
**6.69 All the transistors in the circuits of Fig. P6.69 are specified to have a minimum β of 50. Find approximate values for the collector voltages and calculate forced β for each of the transistors. (Hint: Initially, assume all transistors are operating in saturation, and verify the assumption.)
Q3 V5
V2
V6
R4
R1
R6 5V
Figure P6.67
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Problems 365
5V
5V
5V
Figure P6.69
PROBLEMS
20
CHAPTER 6
5V
PROBLEMS Computer Simulation Problems Problems identified by the Multisim/PSpice icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion. Instructions to assist in setting up PSpice and Multisim simulations for all the indicated problems can be found in the corresponding files on the website. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
Section 7.1: Basic Principles 7.1 For the MOS amplifier of Fig. 7.2(a) with VDD = 5 V, 2 Vt = 0.5 V, kn = 10 mA/V , and RD = 20 k0002, determine the coordinates of the active-region segment (AB) of the VTC [Fig. 7.2(b)]. D 7.2 For the MOS amplifier of Fig. 7.2(a) with VDD = 5 V 2 and kn = 5 mA/V , it is required to have the end point of the VTC, point B, at VDS = 0.5 V. What value of RD is required? If the transistor is replaced with another having twice the value of the transconductance parameter kn , what new value of RD is needed? D 7.3 It is required to bias the MOS amplifier of Fig. 7.3 at point Q for which VOV = 0.2 V and VDS = 1 V. Find the required value of RD when VDD = 5 V, Vt = 0.5 V, and 2 kn = 10 mA/V . Also specify the coordinates of the VTC end point B. What is the small-signal voltage gain of this amplifier? Assuming linear operation, what is the maximum allowable negative signal swing at the output? What is the corresponding peak input signal? 7.4 The MOS amplifier of Fig. 7.4(a), when operated with VDD = 2 V, is found to have a maximum small-signal voltage gain magnitude of 14 V/V. Find VOV and VDS for bias point Q at which a voltage gain of −12 V/V is obtained. 7.5 Consider the amplifier of Fig. 7.4(a) for the case VDD = 0006 2 5 V, RD = 24 k0002, kn (W/L) = 1 mA/V , and Vt = 1 V. (a) Find the coordinates of the two end points of the saturation-region segment of the amplifier transfer characteristic, that is, points A and B on the sketch of Fig. 7.4(b). (b) If the amplifier is biased to operate with an overdrive voltage VOV of 0.5 V, find the coordinates of the bias point
Q on the transfer characteristic. Also, find the value of ID and of the incremental gain Av at the bias point. (c) For the situation in (b), and disregarding the distortion caused by the MOSFET’s square-law characteristic, what is the largest amplitude of a sine-wave voltage signal that can be applied at the input while the transistor remains in saturation? What is the amplitude of the output voltage signal that results? What gain value does the combination of these amplitudes imply? By what percentage is this gain value different from the incremental gain value calculated above? Why is there a difference? 7.6 Various measurements are made on an NMOS amplifier for which the drain resistor RD is 20 k0002. First, dc measurements show the voltage across the drain resistor, VRD , to be 1.5 V and the gate-to-source bias voltage to be 0.7 V. Then, ac measurements with small signals show the voltage gain to be –10 V/V. What is the value of Vt for this transistor? If the 0006 2 process transconductance parameter kn is 200 μA/V , what is the MOSFET’s W/L? *7.7 The expression for the incremental voltage gain Av given in Eq. (7.16) can be written in as
Av = −
0006 0007 2 VDD − VDS VOV
where VDS is the bias voltage at the drain. This expression indicates that for given values of VDD and VOV , the gain magnitude can be increased by biasing the transistor at a lower VDS . This, however, reduces the allowable output signal swing in the negative direction. Assuming linear operation around the bias point, show that the largest possible negative output signal peak vˆ o that is achievable while the transistor remains saturated is 0007 1 1+ 0002 0002 vˆ o = VDS − VOV 0002Av 0002 0006
For VDD = 5 V and VOV = 0.5 V, provide a table of values for Av , vˆ o , and the corresponding vˆ i for VDS = 1 V, 1.5 V, 2 V, and 0006 2 2.5 V. If kn (W/L) = 1 mA/V , find ID and RD for the design for which VDS = 1 V. D *7.8 Design the MOS amplifier of Fig. 7.4(a) to obtain maximum gain while allowing for an output voltage swing of at least ±0.5 V. Let VDD = 5 V, and utilize an overdrive
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Problems 481
*7.9 Figure P7.9 shows an amplifier in which the load resistor RD has been replaced with another NMOS transistor Q2 connected as a two-terminal device. Note that because v DG of Q2 is zero, it will be operating in saturation at all times, even when v I = 0 and iD2 = iD1 = 0. Note also that the two transistors conduct equal drain currents. Using iD1 = iD2 , show that for the range of v I over which Q1 is operating in saturation, that is, for Vt1 ≤ v I ≤ v O + Vt1 the output voltage will be given by
v O = VDD − Vt +
(W/L)1 V − (W/L)2 t
(W/L)1 v (W/L)2 I
where we have assumed Vt1 = Vt2 = Vt . Thus the circuit functions as a linear amplifier, even for large input signals. For (W/L)1 = (50 μm/0.5 μm) and (W/L)2 = (5 μm/0.5 μm), find the voltage gain.
VDD
iD2 Q2 vO iD1 vI
Q1
Figure P7.9
7.11 For the amplifier circuit in Fig. 7.6 with VCC = + 5 V and RC = 1 k0002, find VCE and the voltage gain at the following dc collector bias currents: 0.5 mA, 1 mA, 2.5 mA, 4 mA, and 4.5 mA. For each, give the maximum possible positive- and negative-output signal swing as determined by the need to keep the transistor in the active region. Present your results in a table. D 7.12 Consider the CE amplifier circuit of Fig. 7.6 when operated with a dc supply VCC = +5 V. It is required to find the point at which the transistor should be biased; that is, find the value of VCE so that the output sine-wave signal v ce resulting from an input sine-wave signal v be of 5-mV peak amplitude has the maximum possible magnitude. What is the peak amplitude of the output sine wave and the value of the gain obtained? Assume linear operation around the bias point. (Hint: To obtain the maximum possible output amplitude for a given input, you need to bias the transistor as close to the edge of saturation as possible without entering saturation at any time, that is, without v CE decreasing below 0.3 V.) 7.13 A designer considers a number of low-voltage BJT amplifier designs utilizing power supplies with voltage VCC of 1.0, 1.5, 2.0, or 3.0 V. For transistors that saturate at VCE = 0.3 V, what is the largest possible voltage gain achievable with each of these supply voltages? If in each case biasing is adjusted so that VCE = VCC /2, what gains are achieved? If a negative-going output signal swing of 0.4 V is required, at what VCE should the transistor be biased to obtain maximum gain? What is the gain achieved with each of the supply voltages? (Notice that all of these gains are independent of the value of IC chosen!) D *7.14 A BJT amplifier such as that in Fig. 7.6 is to be designed to support relatively undistorted sine-wave output signals of peak amplitudes P volt without the BJT entering saturation or cutoff and to have the largest possible voltage gain, denoted Av V/V. Show that the minimum supply voltage VCC needed is given by 0002 0002 VCC = VCEsat + P + 0002Av 0002VT
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PROBLEMS
(a) Specify VDS at the bias point. (b) What is the gain achieved? What is the signal amplitude vˆ gs that results in the 0.5-V signal amplitude at the output? (c) If the dc bias current in the drain is to be 100 μA, what value of RD is needed? 0006 2 (d) If kn = 200 μA/V , what W/L ratio is required for the MOSFET?
7.10 A BJT amplifier circuit such as that in Fig. 7.6 is operated with VCC = + 5 V and is biased at VCE = +1 V. Find the voltage gain, the maximum allowed output negative swing without the transistor entering saturation, and the corresponding maximum input signal permitted.
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voltage of approximately 0.2 V.
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PROBLEMS
482 Chapter 7 Transistor Amplifiers Also, find VCC , specified to the nearest 0.5 V, for the following situations: (a) Av = −20 V/V, P = 0.2 V (b) Av = −50 V/V, P = 0.5 V (c) Av = −100 V/V, P = 0.5 V (d) Av = −100 V/V, P = 1.0 V (e) Av = −200 V/V, P = 1.0 V (f) Av = −500 V/V, P = 1.0 V (g) Av = −500 V/V, P = 2.0 V
v BE /VT
iC = I S e
5V
1+
v CE VA
0005
0006 0007000e V − VCE VT −I C RC /VT
= − CC
I R V − VCE 1+ C C 1 + CC VA + VCE VA + VCE
Av =
For the case VCC = 5 V and VCE = 3 V, what is the gain without and with the Early effect taken into account? Let VA = 100 V. 7.18 When the amplifier circuit of Fig. 7.6 is biased with a certain VBE , the dc voltage at the collector is found to be +2 V. For VCC = +5 V and RC = 1 k0002, find IC and the small-signal voltage gain. For a change v BE = +5 mV, calculate the resulting v O . Calculate it two ways: by using the transistor exponential characteristic iC , and approximately, using the small-signal voltage gain. Repeat for v BE = −5 mV. Summarize your results in a table.
10 k vO 10 k
Figure P7.15
*7.19 Consider the amplifier circuit of Fig. 7.6 when operated with a supply voltage VCC = +3V.
7.16 Sketch and label the voltage-transfer characteristics of the pnp amplifiers shown in Fig. P7.16.
VCC
vI
5V
vI vO
vO
RC
RC
0003VCC = 00035 V (a) Figure P7.16
0004
0006 0007 in Eq. (7.4) and including the factor 1 + VCE /VA in Eq. (7.11). Show that the gain expression changes to
7.15 The transistor in the circuit of Fig. P7.15 is biased at a dc collector current of 0.3 mA. What is the voltage gain? (Hint: Use Th´evenin’s theorem to convert the circuit to the form in Fig. 7.6.)
vI
*7.17 In deriving the expression for small-signal voltage gain Av in Eq. (7.21) we neglected the Early effect. Derive this expression including the Early effect by substituting
(b)
(a) What is the theoretical maximum voltage gain that this amplifier can provide? (b) What value of VCE must this amplifier be biased at to provide a voltage gain of –60 V/V? (c) If the dc collector current IC at the bias point in (b) is to be 0.5 mA, what value of RC should be used? (d) What is the value of VBE required to provide the bias point mentioned above? Assume that the BJT has −15 IS = 10 A. (e) If a sine-wave signal v be having a 5-mV peak amplitude is superimposed on VBE , find the corresponding output voltage signal v ce that will be superimposed on VCE assuming linear operation around the bias point. (f) Characterize the signal current ic that will be superimposed on the dc bias current IC .
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Problems 483
7.21 The purpose of this problem is to illustrate the application of graphical analysis to the circuit shown in Fig. P7.21. Sketch iC −v CE characteristic curves for the BJT for iB = 10 μA, 20 μA, 30 μA, and 40 μA. Assume the lines to be horizontal (i.e., neglect the Early effect), and let β = 100. For VCC = 5 V and RC = 1 k0002, sketch the load line. What peak-to-peak collector voltage swing will result for iB varying
*7.22 Sketch the iC −v CE characteristics of an npn transistor having β = 100 and VA = 100 V. Sketch characteristic curves for iB = 20 μA, 50 μA, 80 μA, and 100 μA. For the purpose of this sketch, assume that iC = β iB at v CE = 0. Also, sketch the load line obtained for VCC = 10 V and RC = 1 k0002. If the dc bias current into the base is 50 μA, write the equation for the corresponding iC −v CE curve. Also, write the equation for the load line, and solve the two equations to obtain VCE and IC . If the input signal causes a sinusoidal signal of 30-μA peak amplitude to be superimposed on IB , find the corresponding signal components of iC and v CE .
Section 7.2: Small-Signal Operation and Models *7.23 This problem investigates the nonlinear distortion introduced by a MOSFET amplifier. Let the signal v gs be a sine wave with amplitude Vgs , and substitute v gs = Vgs sin ωt in Eq. (7.28). Using the trigonometric identity 2 sin θ = 21 − 21 cos 2θ, show that the ratio of the signal at frequency 2ω to that at frequency ω, expressed as a percentage (known as the second-harmonic distortion) is
Second-harmonic distortion =
If in a particular application Vgs is 10 mV, find the minimum overdrive voltage at which the transistor should be operated so that the second-harmonic distortion is kept to less than 1%.
VCC
iC
VBB
1 Vgs × 100 4 VOV
RC
2
RB vCE iB
Figure P7.21
7.24 Consider an NMOS transistor having kn = 10 mA/V . Let the transistor be biased at VOV = 0.2 V. For operation in saturation, what dc bias current ID results? If a 0.02-V signal is superimposed on VGS , find the corresponding increment in collector current by evaluating the total collector current iD and subtracting the dc bias current ID . Repeat for a –0.02-V signal. Use these results to estimate gm of the FET at this bias point. Compare with the value of gm obtained using Eq. (7.33).
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PROBLEMS
7.20 The essence of transistor operation is that a change in v BE , v BE , produces a change in iC , iC . By keeping v BE small, iC is approximately linearly related to v BE , iC = gm v BE , where gm is known as the transistor transconductance. By passing iC through RC , an output voltage signal v O is obtained. Use the expression for the small-signal voltage gain in Eq. (7.20) to derive an expression for gm . Find the value of gm for a transistor biased at IC = 0.5 mA.
over the range 10 μA to 40 μA? If the BJT is biased at VCE = 21 VCC , find the value of IC and IB . If at this current VBE = 0.7 V and if RB = 100 k0002, find the required value of VBB .
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(g) What is the value of the dc base current IB at the bias point? Assume β = 100. Characterize the signal current ib that will be superimposed on the base current IB . (h) Dividing the amplitude of v be by the amplitude of ib , evaluate the incremental (or small-signal) input resistance of the amplifier. (i) Sketch and clearly label correlated graphs for v BE , v CE , iC , and iB versus time. Note that each graph consists of a dc or average value and a superimposed sine wave. Be careful of the phase relationships of the sine waves.
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PROBLEMS
484 Chapter 7 Transistor Amplifiers 7.25 Consider the FET amplifier of Fig. 7.10 for the case 2 Vt = 0.4 V, kn = 5 mA/V , VGS = 0.6 V, VDD = 1.8 V, and RD = 10 k0002. (a) (b) (c) (d)
Find the dc quantities ID and VDS . Calculate the value of gm at the bias point. Calculate the value of the voltage gain. −1 If the MOSFET has λ = 0.1 V , find ro at the bias point and calculate the voltage gain.
D *7.26 An NMOS amplifier is to be designed to provide a 0.20-V peak output signal across a 20-k0002 load that can be used as a drain resistor. If a gain of at least 10 V/V is needed, what gm is required? Using a dc supply of 1.8 V, what values of ID and VOV would you choose? What W/L ratio is required 2 if μn Co x = 200 μA/V ? If Vt = 0.4 V, find VGS . D *7.27 In this problem we investigate an optimum design of the CS amplifier circuit of Fig. 7.10. First, use the voltage gain expression Av = −gm RD together with Eq. (7.42) for gm to show that 0006 0007 2 VDD − VDS 2ID RD Av = − =− VOV VOV
Voltages (V) Case
Type
ID (mA)
a b c d e f g h i j k l
N N N N N N P P P P P P
1 1 10 0.5 0.1
0002 0002 0002V 0002
0002 0002 0002V 0002
3
2 0.7
GS
t
1.8
0.8
3
1
Next, let the maximum positive input signal be vˆ i . To keep the second-harmonic distortion to an acceptable level, we bias the MOSFET to operate at an overdrive voltage 0002 V0002OV vˆ i . Let VOV = mvˆ i . Now, to maximize the voltage gain 0002Av 0002, we design for the lowest possible VDS . Show that the minimum VDS that is consistent 0002 with 0002 allowing a negative signal voltage swing at the drain of 0002Av 0002 vˆ i while maintaining saturation-mode operation is given by
VDS =
Now, find VOV , VDS , Av , and vˆ o for the case VDD = 2.5 V, vˆ i = 20 mV, and m = 15. If it is desired to operate this transistor at ID = 200 μA, find the values of RD and W/L, assuming that 0006 2 for this process technology kn = 100 μA/V . 7.28 In the table below, for MOS transistors operating under a variety of conditions, complete as many entries as possible. Although some data is not available, it is always possible to calculate gm using one of Eqs. (7.40), (7.41), or 2 2 (7.42). Assume μn = 500 cm /V· s, μp = 250 cm /V · s, and 2 Co x = 0.4 fF/μm .
Dimensions (μm) VOV
W
L
W/L
0006
k (W/L)
1 0.5 2 0.5
50 1 10 40
2 4
0.5 10 10
0006 0007 VOV + vˆ i + 2VDD vˆ i /VOV 0007 0006 1 + 2 vˆ i /VOV
25 0.5 4 1 5
4000
2
30
3
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0.08
gm (mA/V)
Problems 485
*7.33 Figure P7.33 shows a discrete-circuit amplifier. The input signal v sig is coupled to the gate through a very large capacitor (shown as infinite). The transistor source is connected to ground at signal frequencies via a very large capacitor (shown as infinite). The output voltage signal that develops at the drain is coupled to a load resistance via a very large capacitor (shown as infinite). All capacitors behave as short circuits for signals and as open circuits for dc. 2
Figure P7.30
0002 7.31 0002 In the circuit of Fig. P7.31, the NMOS transistor has 0002Vt 0002 = 0.5 V and VA = 50 V and operates with VD = 1 V. What is the voltage gain v o /v i ? What do VD and the gain become for I increased to 1 mA?
(a) If the transistor has Vt = 1 V, and kn = 4 mA/V , verify that the bias circuit establishes VGS = 1.5 V, ID = 0.5 mA, and VD = +7.0 V. That is, assume these values, and verify that they are consistent with the values of the circuit components and the device parameters. (b) Find gm and ro if VA = 100 V. (c) Draw a complete small-signal equivalent circuit for the amplifier, assuming all capacitors behave as short circuits at signal frequencies. (d) Find Rin , v gs /v sig , v o /v gs , and v o /v sig .
000215 V
10 M0006
Rsig = 200 k0006
0007
16 k0006 0007 vo
vgs 16 k0006 0007
vo vsig 0002 0003
5 M0006
Rin Figure P7.31
Figure P7.33
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
7 k0006
PROBLEMS
7.30 For the NMOS amplifier in Fig. P7.30, replace the transistor with its T equivalent circuit, assuming λ = 0. Derive expressions for the voltage gains v s /v i and v d /v i .
7.32 For a 0.18-μm CMOS fabrication process: Vtn = 0.5 V, 2 2 Vtp = –0.5 V, μn Co x = 400 μA/V , μp Co x = 100 μA/V , 2 C 0002 o x0002 = 8.6 fF/μm , VA (n-channel devices) = 5L (μm), and 0002VA 0002 (p-channel devices) = 6L (μm). Find the small-signal model parameters (gm and ro ) for both an NMOS and a PMOS transistor having W/L = 10 μm/0.5 μm and operating at ID = 100 μA. Also, find the overdrive voltage at which each device must be operating.
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2
7.29 An NMOS technology has μn Co x = 250 μA/V and Vt = 0.5 V. For a transistor with L = 0.5 μm, find the value of W that results in gm = 2 mA/V at ID = 0.25 mA. Also, find the required VGS .
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PROBLEMS
486 Chapter 7 Transistor Amplifiers 7.34 Consider a transistor biased to operate in the active mode at a dc collector current IC . Calculate the collector signal current as a fraction of IC (i.e., ic /IC ) for input signals v be of +1 mV, –1 mV, +2 mV, –2 mV, +5 mV, –5 mV, +8 mV, –8 mV, +10 mV, –10 mV, +12 mV, and –12 mV. In each case do the calculation two ways: (a) using the exponential characteristic, and (b) using the small-signal approximation. Present your results in the form of a table that includes a column for the error introduced by the small-signal approximation. Comment on the range of validity of the small-signal approximation. 7.35 An npn BJT with grounded emitter is operated with VBE = 0.700 V, at which the collector current is 0.5 mA. A 5-k0002 resistor connects the collector to a +5-V supply. What is the resulting collector voltage VC ? Now, if a signal applied to the base raises v BE to 705 mV, find the resulting total collector current iC and total collector voltage v C using the exponential iC –v BE relationship. For this situation, what are v be and v c ? Calculate the voltage gain v c /v be . Compare with the value obtained using the small-signal approximation, that is, –gm RC . 7.36 A transistor with β = 100 is biased to operate at a dc collector current of 0.5 mA. Find the values of gm , rπ , and re . Repeat for a bias current of 50 μA. 7.37 A pnp BJT is biased to operate at IC = 1.0 mA. What is the associated value of gm ? If β = 100, what is the value of the small-signal resistance seen looking into the emitter (re )? Into the base (rπ )? If the collector is connected to a 5-k0002 load, with a signal of 5-mV peak applied between base and emitter, what output signal voltage results? D 7.38 A designer wishes to create a BJT amplifier with a gm of 30 mA/V and a base input resistance of 3000 0002 or more.
Transistor
a
α β IC (mA) IE (mA) IB (mA) gm (mA/V) re (0002) rπ (0002)
1.000
b
c
7.39 A transistor operating with nominal gm of 40 mA/V has a β that ranges from 50 to 150. Also, the bias circuit, being less than ideal, allows a ±20% variation in IC . What are the extreme values found of the resistance looking into the base? 7.40 In the circuit of Fig. 7.20, VBE is adjusted so that VC = 1 V. If VCC = 3 V, RC = 2 k0002, and a signal v be = 0.005 sin ωt volts is applied, find expressions for the total instantaneous quantities iC (t), v C (t), and iB (t). The transistor has β = 100. What is the voltage gain? D *7.41 We wish to design the amplifier circuit of Fig. 7.20 under the constraint that VCC is fixed. Let the input signal v be = Vˆ be sin ωt, where Vˆ be is the maximum value for acceptable linearity. For the design that results in the largest signal at the collector, without the BJT leaving the active region, show that 0006 0007 Vˆ be RC IC = VCC − 0.3 1+ VT and find an expression for the voltage gain obtained. For VCC = 3 V and Vˆ be = 5 mV, find the dc voltage at the collector, the amplitude of the output voltage signal, and the voltage gain. 7.42 The table below summarizes some of the basic attributes of a number of BJTs of different types, operating as amplifiers under various conditions. Provide the missing entries. (Note: Isn’t it remarkable how much two parameters can reveal?) 7.43 A BJT is biased to operate in the active mode at a dc collector current of 1 mA. It has a β of 100 and VA of 100 V. Give the four small-signal models (Figs. 7.25 and 7.27) of the BJT complete with the values of their parameters.
d
e
f
g
0.90
∞
100 1.00
What collector-bias current should he choose? What is the minimum β he can tolerate for the transistor used?
1.00 1.00
5 0.020
1.10 700 25
100 10.1 k0002
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Problems 487 input, v π /v sig , and the voltage gain from base to collector, v o /v π . Use these to show that the overall voltage gain v o /v sig is given by
7.45 Show that the collector current provided by the model of Fig. 7.26(b) is equal to that provided by the model in Fig. 7.26(a).
vo βRC =− v sig rπ + Rsig
PROBLEMS
7.46 Show that the hybrid-π model of Fig. 7.24(b) is the incremental version of the large-signal model of Fig. 6.5(d).
7.48 The transistor amplifier in Fig. P7.48 is biased with a current source I and has a very high β. Find the dc voltage at the collector, VC . Also, find the value of re . Replace the transistor with the T model of Fig. 7.26(b) (note that the dc current source I should be replaced with an open circuit). Hence find the voltage gain v c /v i .
3
ib
Rsig
7.47 Show that the T model of Fig. 7.26(b) is the incremental version of the large-signal model of Fig. 6.5(b).
RC vsig
vo
v
Rin Figure P7.50
7.51 Figure P7.51 shows a transistor with the collector connected to the base. The bias arrangement is not shown. Since a zero v BC implies operation in the active mode, the BJT can be replaced by one of the small-signal models of Figs. 7.24 and 7.26. Use the model of Fig. 7.26(b) and show that the resulting two-terminal device, known as a diode-connected transistor, has a small-signal resistance r equal to re .
10 k
I
ix
0.2 mA
vx
Figure P7.48
7.49 For the conceptual circuit shown in Fig. 7.23, RC = 2 k0002, gm = 50 mA/V, and β = 100. If a peak-to-peak output voltage of 1 V is measured at the collector, what are the peak-to-peak values of v be and ib ? 7.50 Figure P7.50 shows the circuit of an amplifier fed with a signal source v sig with a source resistance Rsig . The bias circuitry is not shown. Replace the BJT with its hybrid-π equivalent circuit of Fig. 7.24(a). Find the input resistance Rin ≡ v π /ib , the voltage transmission from source to amplifier
v r = ix x Figure P7.51
7.52 Figure P7.52 shows a particular configuration of BJT amplifiers known as “emitter follower.” The bias arrangement is not shown. Replace the BJT with its T equivalent-circuit
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 7
7.44 Using the T model of Fig. 7.26(a), show that the input resistance between base and emitter, looking into the base, is equal to rπ .
7.54 In the circuit shown in Fig. P7.54, the transistor has a β of 200. What is the dc voltage at the collector? Replacing the BJT with one of the hybrid-π models (neglecting ro ), draw the equivalent circuit of the amplifier. Find the input resistances 0006 0007 Rib and Rin and the overall voltage gain v o /v sig . For an output signal of ±0.4 V, what values of v sig and v b are required?
model of Fig. 7.26(b). Show that Rin ≡
CHAPTER 7
PROBLEMS
488 Chapter 7 Transistor Amplifiers
0007 0006 vi = (β + 1) re + Re ib Re vo = vi Re + re
5V
ib
1.5 V
10 mA
10 k
vi
Rsig
Re
vo
vb
1k vo
vsig
Rin
RC 100
Figure P7.52
Rin
7.53 For the circuit shown in Fig. P7.53, draw a complete small-signal equivalent circuit utilizing an appropriate T model for the BJT (use α = 0.99). Your circuit should show the values of all components, including the model parameters. What is the input resistance Rin ? Calculate the overall voltage 0006 0007 gain v o /v sig . 5V
12 k
RC C2 vo
C1
Rsig
RL 12 k
Q1
75 0.33 mA
vsig Rin Figure P7.53
Rib
Figure P7.54
7.55 Consider the augmented hybrid-π model shown in Fig. 7.25(a). Disregarding how biasing is to be done, what is the largest possible voltage gain available for a signal source connected directly to the base and a very-high-resistance load? Calculate the value of the maximum possible gain for VA = 25 V and VA = 125 V. D 7.56 Redesign the circuit of Fig. 7.30(a) by raising the resistor values by a factor n to increase the resistance seen by the input v i to 75 0002. What value of voltage gain results? Grounded-base circuits of this kind are used in systems such as cable TV, in which, for highest-quality signaling, load resistances need to be “matched” to the equivalent resistances of the interconnecting cables. D *7.57 Design an amplifier using the configuration of Fig. 7.30(a). The power supplies available are ±5 V. The input signal source has a resistance of 50 0002, and it is required that the amplifier input resistance match this value. (Note that Rin = re RE 0004 re .) The amplifier is to have the greatest possible voltage gain and the largest possible output signal but retain small-signal linear operation (i.e., the signal component across the base–emitter junction should be limited to no more
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 489
v o1 RE v i = RE + re −αRC v o2 v i = RE + re
(a) No more than 5% of the signal strength is lost in the connection to the amplifier input; (b) If the load resistance changes from the nominal value of 2 k0002 to a low value of 1 k0002, the change in output voltage is limited to 5% of nominal value; and (c) The nominal overall voltage gain is 10 V/V. 7.61 Figure P7.61 shows an alternative equivalent-circuit representation of an amplifier. If this circuit is to be equivalent to that in Fig. 7.34(b) show that Gm = Av o /Ro . Also convince yourself that the transconductance Gm is defined as 0002 io 00020002 Gm = v 0002 i R
5V 3.3
L =0
and hence is known as the short-circuit transconductance. Now, if the amplifier is fed with a signal source (v sig , Rsig ) and is connected to a load resistance RL show that the gain of 0006 0007 the amplifier proper Av is given by Av = Gm Ro RL and the overall voltage gain Gv is given by Gv =
0006 0007 Rin G R R Rin + Rsig m o L
3.6 Io 0002
0002
Figure P7.58
vi Find the values of these voltage gains (for α 0004 1). Now, if the terminal labeled v o1 is connected to ground, what does the voltage gain v o2 /v i become?
Rin
Gmvi
Ro
0003
vo
0003
Figure P7.61
Section 7.3: Basic Configurations 7.59 An amplifier with an input resistance of 100 k0002, an open-circuit voltage gain of 100 V/V, and an output resistance of 100 0002 is connected between a 20-k0002 signal source and a 2-k0002 load. Find the overall voltage gain Gv . Also find the current gain, defined as the ratio of the load current to the current drawn from the signal source.
7.62 An alternative equivalent circuit of an amplifier fed with a signal source (v sig , Rsig ) and connected to a load RL is shown in Fig. P7.62. Here Gv o is the open-circuit overall voltage gain, 0002 v 0002 Gv o = v o 00020002 sig R
L =∞
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
*7.58 The transistor in the circuit shown in Fig. P7.58 is biased to operate in the active mode. Assuming that β is very large, find the collector bias current IC . Replace the transistor with the small-signal equivalent-circuit model of Fig. 7.26(b) (remember to replace the dc power supply with a short circuit). Analyze the resulting amplifier equivalent circuit to show that
D 7.60 Specify the parameters Rin , Av o , and Ro of an amplifier that is to be connected between a 100-k0002 source and a 2-k0002 load and is required to meet the following specifications:
CHAPTER 7
than 10 mV). Find appropriate values for RE and RC . What is the value of voltage gain realized from signal source to output?
CHAPTER 7
PROBLEMS
490 Chapter 7 Transistor Amplifiers and Rout is the output resistance with v sig set to zero. This is different than Ro . Show that Gv o = 0002 where Ri = Rin 0002R
L =∞
Ri A Ri + Rsig v o
.
7.64 Calculate the overall voltage gain of a CS amplifier fed with a 1-M0002 source and connected to a 10-k0002 load. The MOSFET has gm = 2 mA/V, and a drain resistance RD = 10 k0002 is utilized.
Also show that the overall voltage gain is Gv = Gv o
RL RL + Rout
**7.63 Most practical amplifiers have internal feedback that make them non-unilateral. In such a case, Rin depends on RL . To illustrate this point we show in Fig. P7.63 the equivalent circuit of an amplifier where a feedback resistance Rf models the internal feedback mechanism that is present in this amplifier. It is Rf that makes the amplifier non-unilateral. Show that 000f 0007 0010 0006 Rf + R2 RL 0006 0007 Rin = R1 1 + gm R2 RL 0006 0007 1 − 1/ gm Rf 0006 0007 Av o = −gm R2 1 + R2 /Rf Ro = R2 Rf
Rsig
Evaluate Rin , Av o , and Ro for the case R1 = 100 k0002, Rf = 1 M0002, gm = 100 mA/V, R2 = 100 0002, and RL = 1 k0002. Which of the amplifier characteristic parameters is most affected by Rf (that is, relative to the case with Rf = ∞)? For Rsig = 100 k0002 determine the overall voltage gain, Gv , with and without Rf present.
Rout
7.65 A CS amplifier utilizes a MOSFET with μn Co x = 2 400 μA/V and W/L = 10. It is biased at ID = 320 μA and uses RD = 10 k0002. Find Rin , Av o , and Ro . Also, if a load resistance of 10 k0002 is connected to the output, what overall voltage gain Gv is realized? Now, if a 0.2-V peak sine-wave signal is required at the output, what must the peak amplitude of v sig be? 7.66 A common-source amplifier utilizes a MOSFET operated at VOV = 0.25 V. The amplifier feeds a load resistance RL = 15 k0002. The designer selects RD = 2RL . If it is required to realize an overall voltage gain Gv of −10 V/V what gm is needed? Also specify the bias current ID . If, to increase the output signal swing, RD is reduced to RD = RL , what does Gv become?
io
0002 vsig 0002 0003
vi
0002 Rin
0003
0002 Gvovsig0003
RL vo 0003
Figure P7.62
Rsig
ii
Rf
0002 vsig 0002 0003
vi 0003
0002 R1
g mvi
R2
RL
vo 0003
Rin Figure P7.63
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 491
7.68 A CE amplifier utilizes a BJT with β = 100 biased at IC = 0.5 mA; it has a collector resistance RC = 10 k0002. Find Rin , Ro , and Av o . If the amplifier is fed with a signal source having a resistance of 10 k0002, and a load resistance RL = 10 k0002 is connected to the output terminal, find the resulting Av and Gv . If the peak voltage of the sine wave appearing between base and emitter is to be limited to 5 mV, what vˆ sig is allowed, and what output voltage signal appears across the load? D *7.69 In this problem we investigate the effect of the inevitable variability of β on the realized gain of the CE amplifier. For this purpose, use the overall gain expression in Eq. (7.114). 0002 0002 0002Gv 0002 = 0006
0006
R 0007L0006 0007 Rsig /β + 1/gm
0006
where RL = RL RC . 0006 Consider the case RL = 10 k0002 and Rsig = 10 k0002, and let the BJT be biased at IC = 1 mA. The BJT has a nominal β of 100. 0002 0002 (a) What is the nominal value of 0002Gv 0002? (b) If β can be anywhere between 50 and 150, what is the 0002 0002 corresponding range of 0002Gv 0002? 0002 0002 (c) If in a particular design, it is required to maintain 0002Gv 0002 within ±20% of its nominal value, what is the maximum allowable range of β? (d) If it is not possible to restrict β to the range found in (c), and the designer has to contend with β in the range0002 500002 to 150, what value of bias current IC would result in 0002Gv 0002 falling in a range of ±20% 0002 of 0002 a new nominal value? What is the nominal value of 0002Gv 0002 in this case? 7.70 Two identical CE amplifiers are connected in cascade. The first stage is fed with a source v sig having a resistance Rsig = 10 k0002. A load resistance RL = 10 k0002 is connected to the collector of the second stage. Each BJT is biased at IC = 0.25 mA and has β = 100. Each stage utilizes a collector resistance RC = 10 k0002.
7.71 A MOSFET connected in the CS configuration has a transconductance gm = 5 mA/V. When a resistance Rs is connected in the source lead, the effective transconductance is reduced to 2 mA/V. What do you estimate the value of Rs to be? 7.72 A CS amplifier using an NMOS transistor with gm = 2 mA/V is found to have an overall voltage gain of −10 V/V. What value should a resistance Rs inserted in the source lead have to reduce the overall voltage gain to −5 V/V? 7.73 The overall voltage gain of a CS amplifier with a resistance Rs = 0.5 k0002 in the source lead was measured and found to be −10 V/V. When Rs was shorted, but the circuit operation remained linear, the gain doubled. What must gm be? What value of Rs is needed to obtain an overall voltage gain of −16 V/V? 7.74 A CE amplifier utilizes a BJT with β = 100 biased at IC = 0.5 mA and has a collector resistance RC = 12 k0002 and a resistance Re = 250 0002 connected in the emitter. Find Rin , Av o , and Ro . If the amplifier is fed with a signal source having a resistance of 10 k0002, and a load resistance RL = 12 k0002 is connected to the output terminal, find the resulting Av and Gv . If the peak voltage of the sine wave appearing between base and emitter is to be limited to 5 mV, what vˆ sig is allowed, and what output voltage signal appears across the load? D 7.75 Design a CE amplifier with a resistance Re in the emitter to meet the following specifications: (i) Input resistance Rin = 15 k0002. (ii) When fed from a signal source with a peak amplitude of 0.15 V and a source resistance of 30 k0002, the peak amplitude of v π is 5 mV. Specify Re and the bias current IC . The BJT has β = 74. If the total resistance in the collector is 6 k0002, find the overall voltage gain Gv and the peak amplitude of the output signal v o . D 7.76 Inclusion of an emitter resistance Re reduces the variability of the gain Gv due to the inevitable wide variance in the value of β. Consider a CE amplifier operating between a signal source with Rsig = 10 k0002 and a total collector resistance RC RL of 10 k0002. The BJT is biased at IC = 1 mA and its β is specified to be nominally 100 but can lie in the range of 50 to 150. First determine the nominal value and the range of
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
(a) Sketch the equivalent circuit of the two-stage amplifier. (b) Calculate the overall voltage gain Gv .
(a) Sketch the equivalent circuit of the two-stage amplifier. (b) Find the overall voltage gain, v o2 /v sig .
CHAPTER 7
7.67 Two identical CS amplifiers are connected in cascade. The first stage is fed with a source v sig having a resistance Rsig = 200 k0002. A load resistance RL = 10 k0002 is connected to the drain of the second stage. Each MOSFET is biased at ID = 0.3 mA and operates with VOV = 0.2 V. Each stage utilizes a drain resistance RD = 10 k0002.
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PROBLEMS
492 Chapter 7 Transistor Amplifiers 0002 0002 0002Gv 0002 without resistance Re . Then select a value for Re that will 0002 0002 ensure that 0002Gv 0002 be within ±20% of its new nominal 0002 value. 0002 0002Gv 0002, and Specify the value of R0002e , the new nominal value of 0002 the expected range of 0002Gv 0002. 7.77 A CG amplifier using an NMOS transistor for which gm = 2 mA/V has a 5-k0002 drain resistance RD and a 5-k0002 load resistance RL . The amplifier is driven by a voltage source having a 750-0002 resistance. What is the input resistance of the amplifier? What is the overall voltage gain Gv ? By what factor must the bias current ID of the MOSFET be changed so that Rin matches Rsig ? 7.78 A CG amplifier when fed with a signal source having Rsig = 100 0002 is found to have an overall voltage gain of 12 V/V. When a 100-0002 resistance was added in series with the signal generator the overall voltage gain decreased to 10 V/V. What must gm of the MOSFET be? If the MOSFET is biased at ID = 0.25 mA, at what overdrive voltage must it be operating? D 7.79 A CB amplifier is operating with RL = 10 k0002, RC = 10 k0002, and Rsig = 50 0002. At what current IC should the transistor be biased for the input resistance Rin to equal that of the signal source? What is the resulting overall voltage gain? Assume α 0004 1. 7.80 For the circuit in Fig. P7.80, let Rsig re and α 0004 1. Find v o .
RC
isig
vo
Rsig
Figure P7.80
7.81 A CB amplifier is biased at IE = 0.2 mA with RC = RL = 10 k0002 and is driven by a signal source with Rsig = 0.5 k0002. Find the overall voltage gain Gv . If the maximum signal amplitude of the voltage between base and emitter is limited to 10 mV,
what are the corresponding amplitudes of v sig and v o ? Assume α 0004 1. 7.82 A source follower is required to connect a high-resistance source to a load whose resistance is nominally 2 k0002 but can be as low as 1.5 k0002 and as high as 5 k0002. What is the maximum output resistance that the source follower must have if the output voltage is to remain within ±10% of 2 nominal value? If the MOSFET has kn = 2.5 mA/V , at what current ID must it be biased? At what overdrive voltage is the MOSFET operating? D 7.83 A source follower is required to deliver a 0.5-V peak sinusoid to a 2-k0002 load. If the peak amplitude of v gs is to be limited to 50 mV, and the MOSFET transconductance 2 parameter kn is 5 mA/V , what is the lowest value of ID at which the MOSFET can be biased? At this bias current, what are the maximum and minimum currents that the MOSFET will be conducting (at the positive and negative peaks of the output sine wave)? What must the peak amplitude of v sig be? D 7.84 An emitter follower is required to deliver a 0.5-V peak sinusoid to a 2-k0002 load. If the peak amplitude of v be is to be limited to 5 mV, what is the lowest value of IE at which the BJT can be biased? At this bias current, what are the maximum and minimum currents that the BJT will be conducting (at the positive and negative peaks of the output sine wave)? If the resistance of the signal source is 200 k0002, what value of Gv is obtained? Thus determine the required amplitude of v sig . Assume β = 100. 7.85 An emitter follower with a BJT biased at IC = 2 mA and having β = 100 is connected between a source with Rsig = 10 k0002 and a load RL = 0.5 k0002. (a) Find Rin , v b /v sig , and v o /v sig . (b) If the signal amplitude across the base–emitter junction is to be limited to 10 mV, what is the corresponding amplitude of v sig and v o ? (c) Find the open-circuit voltage gain Gv o and the output resistance Rout . Use these values first to verify the value of Gv obtained in (a), then to find the value of Gv obtained with RL reduced to 250 0002. 7.86 An emitter follower is operating at a collector bias current of 0.5 mA and is used to connect a 10-k0002 source to a 1-k0002 load. If the nominal value of β is 100, what output resistance Rout and overall voltage gain Gv result? Now if
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 493
7.88 For the general amplifier circuit shown in Fig. P7.88 neglect the Early effect. (a) Find expressions for v c /v sig and v e /v sig . (b) If v sig is disconnected from node X, node X is grounded, and node Y is disconnected from ground and connected to v sig , find the new expression for v c /v sig .
ic
X
RB
vc
ib RC ve
ie vsig
RE Y
Figure P7.88
7.89 When the Early effect is neglected, the overall voltage gain of a CE amplifier with a collector resistance RC = 10 k0002 is calculated to be −100 V/V. If the BJT is biased at IC = 1 mA and the Early voltage is 100 V, provide a better estimate of the voltage gain Gv . *7.90 Show that when ro is taken into account, the voltage gain of the source follower becomes Gv ≡
vo RL ro =0006 0007 1 v sig RL ro + gm
Now, with RL removed, the voltage gain is carefully measured and found to be 0.98. Then, when RL is connected and its value is varied, it is found that the gain is halved at RL = 500 0002. If the amplifier remained linear throughout this measurement, what must the values of gm and ro be?
Section 7.4: Biasing D 7.92 Consider the classical biasing scheme shown in Fig. 7.48(c), using a 9-V supply. For the MOSFET, Vt = 1 V, 2 λ = 0, and kn = 2 mA/V . Arrange that the drain current is 1 mA, with about one-third of the supply voltage across each of RS and RD . Use 22 M0002 for the larger of RG1 and RG2 . What are the values of RG1 , RG2 , RS , and RD that you have chosen? Specify them to two significant digits. For your design, how far is the drain voltage from the edge of saturation? D 7.93 Using the circuit topology displayed in Fig. 7.48(e), arrange to bias the NMOS transistor at ID = 0.5 mA with VD midway between cutoff and the beginning of triode operation. The available supplies are ±5 V. For the NMOS transistor, 2 Vt = 1.0 V, λ = 0, and kn = 1 mA/V . Use a gate-bias resistor of 10 M0002. Specify RS and RD to two significant digits. D *7.94 In an electronic instrument using the biasing scheme shown in Fig. 7.48(c), a manufacturing error reduces RS to zero. Let VDD = 15 V, RG1 = 10 M0002, and RG2 = 5.1 M0002. What is the value of VG created? If supplier specifications 2 allow kn to vary from 0.2 to 0.3 mA/V and Vt to vary from 1.0 V to 1.5 V, what are the extreme values of ID that may result? What value of RS should have been installed to limit the maximum value of ID to 1.5 mA? Choose an appropriate standard 5% resistor value (refer to Appendix J). What extreme values of current now result? 7.95 An NMOS transistor is connected in the bias circuit of Fig. 7.48(c), with VG = 5 V and RS = 3 k0002. The transistor 2 has Vt = 1 V and kn = 2 mA/V . What bias current results? If a transistor for which kn is 50% higher is used, what is the resulting percentage increase in ID ? 7.96 The bias circuit of Fig. 7.48(c) is used in a design with VG = 5 V and RS = 2 k0002. For a MOSFET with
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
7.87 An emitter follower, when driven from a 5-k0002 source, was found to have an output resistance Rout of 150 0002. The output resistance increased to 250 0002 when the source resistance was increased to 10 k0002. Find the overall voltage gain when the follower is driven by a 10-k0002 source and loaded by a 1-k0002 resistor.
D 7.91 In this problem, we investigate the effect of changing the bias current IC on the overall voltage gain Gv of a CE amplifier. Consider the situation of a CE amplifier operating with a signal source having Rsig = 10 k0002 and having RC ||RL = 10 k0002. The BJT is specified to have β = 100 and VA = 25 V. Use Eq. (7.114) (with r0002o included in parallel with RC and RL in 0002 the numerator) to find 0002Gv 0002 at IC = 0.1 mA, 0.2 mA, 0.5 mA, 00021.0 0002mA, and 1.25 mA. Observe the effect of ro on limiting 0002Gv 0002 as IC is increased. Find the value of IC that results in 0002 0002 0002Gv 0002 = 50 V/V.
CHAPTER 7
transistor β is specified to lie in the range 50 to 150, find the corresponding range of Rout and Gv .
CHAPTER 7
PROBLEMS
494 Chapter 7 Transistor Amplifiers 2
kn = 2 mA/V , the source voltage was measured and found to be 2 V. What must Vt be for this device? If a device for which Vt is 0.5 V less is used, what does VS become? What bias current results? D 7.97 Design the circuit of Fig. 7.48(e) for a MOSFET 2 having Vt = 1 V and kn = 4 mA/V . Let VDD = VSS = 5 V. Design for a dc bias current of 0.5 mA and for the largest possible voltage gain (and thus the largest possible RD ) consistent with allowing a 2-V peak-to-peak voltage swing at the drain. Assume that the signal voltage on the source terminal of the FET is zero. D 7.98 Design the circuit in Fig. P7.98 so that the transistor operates in saturation with VD biased 1 V from the edge of the triode region, with ID = 1 mA and VD = 3 V, for each of the following two devices (use a 10-μA current in the voltage divider): 0002 0002 0006 2 (a) 00020002Vt 00020002 = 1 V and kp W/L = 0.5 mA/V 0006 2 (b) 0002Vt 0002 = 2 V and kp W/L = 1.25 mA/V For each case, specify the values of VG , VD , VS , R1 , R2 , RS , and RD .
000210 V
R1
and its value, when multiplied by the variability (or tolerance) of K, provides the corresponding expected variability of ID , 0005 0004 ID K I = SKD ID K The purpose of this problem is to investigate the use of the sensitivity function in the design of the bias circuit of Fig. 7.48(e). (a) Show that for Vt constant, 0011 0012 0003 I SKD = 1 1 + 2 KID RS 2
(b) For a MOSFET having K = 100 μA/V with a variability of ±10% and Vt = 1 V, find the value of RS that would result in ID = 100 μA with a variability of ±1%. Also, find VGS and the required value of VSS . (c) If the available supply VSS = 5 V, find the value of RS for ID = 100 μA. Evaluate the sensitivity function, and give the expected variability of ID in this case. D **7.100 The variability (ID /ID ) in the bias current ID due to the variability (Vt /Vt ) in the threshold voltage Vt can be evaluated from 0004 0005 ID Vt I = SVDt ID Vt I
where SVDt , the sensitivity of ID relative to Vt , is defined as
RS VS
I
SVDt =
VG VD R2
∂ID Vt ∂Vt ID
(a) For the case of a MOSFET biased with a fixed VGS , show that
RD I
SVDt = −
Figure P7.98
D **7.99 A very useful way to characterize the stability of the bias current ID is to evaluate the sensitivity of ID relative to a particular transistor parameter whose variability might be large. The sensitivity of ID relative to the MOSFET parameter 0006 K ≡ 21 k (W/L) is defined as ∂I /I ∂I K S ≡ D D= D ∂K/K ∂K ID ID K
2Vt VOV
and find the variability in ID for Vt = 0.5 V and Vt /Vt = ±5%. Let the MOSFET be biased at VOV = 0.25 V. (b) For the case of a MOSFET biased with a fixed gate voltage VG and a resistance RS included in the source lead, show that I
SVDt = −
2Vt VOV + 2ID RS
For the same parameters given in (a), find the required value of (ID RS ) and VG to limit ID /ID to ±5%. What value of RS is needed if ID is 100 μA?
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 495
2
(a) Vt = 1 V and kn = 0.5 mA/V 2 (b) Vt = 2 V and kn = 1.25 mA/V
D 7.103 Figure P7.103 shows a variation of the feedback-bias circuit of Fig. 7.50. Using a 5-V supply with an 2 NMOS transistor for which Vt = 0.8 V, kn = 8 mA/V , and λ = 0, provide a design that biases the transistor at ID = 1 mA, with VDS large enough to allow saturation operation for a 2-V negative signal swing at the drain. Use 22 M0002 as the largest resistor in the feedback-bias network. What values of RD , RG1 , and RG2 have you chosen? Specify all resistors to two significant digits.
VDD
RD RG1
RG2
Figure P7.103
D 7.104 For the circuit in Fig. 7.51(a), neglect the base current IB in comparison with the current in the voltage divider. It is required to bias the transistor at IC = 1 mA, which requires selecting RB1 and RB2 so that VBE = 0.710 V. If VCC = 3 V, what must the ratio RB1 /RB2 be? Now, if RB1 and RB2 are 1% resistors, that is, each can be in the range of 0.99 to 1.01 of its nominal value, what is the range obtained for VBE ? What is the corresponding range of IC ? If RC = 2 k0002, what is
D 7.105 It is required to bias the transistor in the circuit of Fig. 7.51(b) at IC = 1 mA. The transistor β is specified to be nominally 100, but it can fall in the range of 50 to 150. For VCC = +3 V and RC = 2 k0002, find the required value of RB to achieve IC = 1 mA for the “nominal” transistor. What is the expected range for IC and VCE ? Comment on the efficacy of this bias design. D 7.106 Consider the single-supply bias network shown in Fig. 7.52(a). Provide a design using a 9-V supply in which the supply voltage is equally split between RC , VCE , and RE with a collector current of 0.6 mA. The transistor β is specified to have a minimum value of 90. Use a voltage-divider current of IE /10, or slightly higher. Since a reasonable design should operate for the best transistors for which β is very high, do your initial design with β = ∞. Then choose suitable 5% resistors (see Appendix J), making the choice in a way that will result in a VBB that is slightly higher than the ideal value. Specify the values you have chosen for RE , RC , R1 , and R2 . Now, find VB , VE , VC , and IC for your final design using β = 90. D 7.107 Repeat Problem 7.106, but use a voltage-divider current that is IE /2. Check your design at β = 90. If you have the data available, find how low β can be while the value of IC does not fall below that obtained with the design of Problem 7.106 for β = 90. D *7.108 It is required to design the bias circuit of Fig. 7.52 for a BJT whose nominal β = 100. 0006 0007 (a) Find the largest ratio RB /RE that will guarantee IE remains within ±5% of its nominal value for β as low as 50 and as high as 150. (b) If the resistance ratio found in (a) is used, find an 0006 0007 expression for the voltage VBB ≡ VCC R2 / R1 + R2 that will result in a voltage drop of VCC /3 across RE . (c) For VCC = 5 V, find the required values of R1 , R2 , and RE to obtain IE = 0.5 mA and to satisfy the requirement for stability of IE in (a). (d) Find RC so that VCE = 1.0 V for β equal to its nominal value. Check your design by evaluating the resulting range of IE .
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
D 7.102 Using the feedback bias arrangement shown in Fig. 7.50 with a 5-V supply and an NMOS device for which 2 Vt = 1 V and kn = 10 mA/V , find RD to establish a drain current of 0.2 mA.
the range obtained for VCE ? Comment on the efficacy of this biasing arrangement.
CHAPTER 7
7.101 In the circuit of Fig. 7.50, let RG = 10 M0002, RD = 10 k0002, and VDD = 10 V. For each of the following two transistors, find the voltages VD and VG .
CHAPTER 7
PROBLEMS
496 Chapter 7 Transistor Amplifiers D *7.109 Consider the two-supply bias arrangement shown in Fig. 7.53 using ±5-V supplies. It is required to design the circuit so that IC = 0.5 mA and VC is placed 2 V above VE . (a) For β = ∞, what values of RE and RC are required? (b) If the BJT is specified to have a minimum β of 50, find the largest value for RB consistent with the need to limit the voltage drop across it to one-tenth the voltage drop across RE . (c) What standard 5% resistor values (see Appendix J) would you use for RB , RE , and RC ? In making your selection, use somewhat lower values in order to compensate for the low-β effects. (d) For the values you selected in (c), find IC , VB , VE , and VC for β = ∞ and for β = 50. D *7.110 Utilizing ±3-V power supplies, it is required to design a version of the circuit in Fig. 7.53 in which the signal will be coupled to the emitter and thus RB can be set to zero. Find values for RE and RC so that a dc emitter current of 0.4 mA is obtained and so that the gain is maximized while allowing ±1 V of signal swing at the collector. If temperature increases from the nominal value of 25°C to 125°C, estimate the percentage change in collector bias current. In addition to the –2 mV/°C change in VBE , assume that the transistor β changes over this temperature range from 50 to 150.
Design this circuit for β = 100. Use a current through RB2 equal to the base current. Now, what values of VC and IC result with β = ∞?
VCC
RC VC IC RB1
RB2
Figure P7.112
D 7.113 A circuit that can provide a very large voltage gain for a high-resistance load is shown in Fig. P7.113. Find the values of I and RB to bias the BJT at IC = 1 mA and VC = 1.5 V. Let β = 100.
D 7.111 Using a 3-V power supply, design a version of the circuit of Fig. 7.54 to provide a dc emitter current of 0.5 mA and to allow a ±1-V signal swing at the collector. The BJT has a nominal β = 100. Use standard 5% resistor values (see Appendix J). If the actual BJT used has β = 50, what emitter current is obtained? Also, what is the allowable signal swing at the collector? Repeat for β = 150. D *7.112 (a) Using a 3-V power supply, design the feedback bias circuit of Fig. 7.54 to provide IC = 1 mA and VC = VCC /2 for β = 100. (b) Select standard 5% resistor values, and reevaluate VC and IC for β = 100. (c) Find VC and IC for β = ∞. (d) To improve the situation that obtains when high-β transistors are used, we have to arrange for an additional current to flow through RB . This can be achieved by connecting a resistor between base and emitter, as shown in Fig. P7.112.
VCC
I
RB
IC
VC
Figure P7.113
7.114 The circuit in Fig. P7.114 provides a constant current IO as long as the circuit to which the collector is
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 497
IO = α
and keeping the current in each junction the same, the current IO will be
0013 0006 00070014 VCC R2 / R1 + R2 − VBE 0006 0007 RE + R1 R2 /(β + 1)
IO =
VCC 2RE
D 7.116 For the circuit in Fig. P7.116 find the value of R that will result in IO 0004 0.5 mA. What is the0002 largest 0002 voltage that can be applied to the collector? Assume 0002VBE 0002 = 0.7 V.
Figure P7.114
D *7.115 For the circuit in Fig. P7.115, assuming all transistors to be identical with β infinite, derive an expression for the output current IO , and show that by selecting R 1 = R2
Figure P7.116
Section 7.5: Discrete-Circuit Amplifiers 7.117 Calculate the overall voltage gain Gv of a common-source amplifier for which gm = 3 mA/V, ro = 100 k0002, RD = 10 k0002, and RG = 10 M0002. The amplifier is fed from a signal source with a Th´evenin resistance of 1 M0002, and the amplifier output is coupled to a load resistance of 20 k0002. 7.118 The NMOS transistor in the CS amplifier shown in Fig. P7.118 has Vt = 0.7 V and VA = 50 V.
Figure P7.115
(a) Neglecting the Early effect, verify that the MOSFET is operating in saturation with ID = 0.5 mA and VOV = 0.3 V. What must the MOSFET’s kn be? What is the dc voltage at the drain? (b) Find Rin and Gv . (c) If v sig is a sinusoid with a peak amplitude vˆ sig , find the maximum allowable value of vˆ sig for which the transistor remains in saturation. What is the corresponding amplitude of the output voltage?
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
which is independent of VBE . What must the relationship of RE to R1 and R2 be? For VCC = 10 V and VBE = 0.7 V, design the circuit to obtain an output current of 0.5 mA. What is the lowest voltage that can be applied to the collector of Q3 ?
CHAPTER 7
connected maintains the BJT in the active mode. Show that
498 Chapter 7 Transistor Amplifiers
CHAPTER 7
PROBLEMS
00025 V
300 k0006
5 k0006 CC2
vo
CC1
120 k0006
5 k0006 CS vsig 0002 0003
200 k0006
2 k0006
Rin Figure P7.118
(d) What is the value of resistance Rs that needs to be inserted in series with capacitor CS in order to allow us to double the input signal vˆ sig ? What output voltage now results? D *7.119 The PMOS transistor in the CS of 0002 amplifier 0002 Fig. P7.119 has Vtp = −0.7 V and a very large 0002VA 0002. (a) Select a value 0002 for 0002 RS to bias the transistor at ID = 0.3 mA and 0002VOV 0002 = 0.3 V. Assume v sig to have a zero dc component. (b) Select a value for RD that results in Gv = −10 V/V.
(c) Find the largest sinusoid vˆ sig that the amplifier can handle while remaining in the saturation region. What is the corresponding signal at the output? (d) If to obtain reasonably linear operation, vˆ sig is limited to 50 mV, what value can RD be increased to while maintaining saturation-region operation? What is the new value of Gv ? 7.120 Figure P7.120 shows a scheme for coupling and amplifying a high-frequency pulse signal. The circuit utilizes
VDD
00022.5 V RD
RS
vo
CS Rsig
50-0006 coaxial cable
CC vsig 0002 0003
Figure P7.119
vd1
vo
id
RD 00032.5 V
Q2
vi
Q1
5 mV
Figure P7.120
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Ri2 = 50 0006
Problems 499
(a) Find the values of RS , RD , and RG so that ID = 0.4 mA, the largest possible value for RD is used while a maximum signal swing at the drain of ±0.8 V is possible, and the input resistance at the gate is 10 M0002. Neglect the Early effect. (b) Find the values of gm and ro at the bias point. (c) If terminal Z is grounded, terminal X is connected to a signal source having a resistance of 1 M0002, and terminal Y is connected to a load resistance of 10 k0002, find the voltage gain from signal source to load. (d) If terminal Y is grounded, find the voltage gain from X to Z with Z open-circuited. What is the output resistance of the source follower?
*7.122 (a) The NMOS transistor in the source-follower circuit of Fig. P7.122(a) has gm = 10 mA/V and a large ro . Find the open-circuit voltage gain and the output resistance. (b) The NMOS transistor in the common-gate amplifier of Fig. P7.122(b) has gm = 10 mA/V and a large ro . Find the input resistance and the voltage gain. (c) If the output of the source follower in (a) is connected to the input of the common-gate amplifier in (b), use the results of (a) and (b) to obtain the overall voltage gain v o /v i .
vi 0007 vo1 10 k0006
(a)
00025 V
5 k0006
RD
0007
0007
vo
Y 0007
2 k0006
X 0007 Z
RG
v i2 10 k0006
RS
00035 V Figure P7.121
(b) Figure P7.122
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
D *7.121 The MOSFET in the circuit of Fig. P7.121 has 2 Vt = 0.8 V, kn = 5 mA/V , and VA = 40 V.
(e) If terminal X is grounded and terminal Z is connected to a current source delivering a signal current of 50 μA and having a resistance of 100 k0002, find the voltage signal that can be measured at Y. For simplicity, neglect the effect of ro .
CHAPTER 7
two MOSFETs whose bias details are not shown and a 50-0002 coaxial cable. Transistor Q1 operates as a CS amplifier and Q2 as a CG amplifier. For proper operation, transistor Q2 is required to present a 50-0002 resistance to the cable. This situation is known as “proper termination” of the cable and ensures that there will be no signal reflection coming back on the cable. When the cable is properly terminated, its input resistance is 50 0002. What must gm2 be? If Q1 is biased at the same point as Q2 , what is the amplitude of the current pulses in the drain of Q1 ? What is the amplitude of the voltage pulses at the drain of Q1 ? What value of RD is required to provide 1-V pulses at the drain of Q2 ?
CHAPTER 7
PROBLEMS
500 Chapter 7 Transistor Amplifiers D **7.123 The MOSFET in the amplifier circuit of 2 Fig. P7.123 has Vt = 0.6 V, kn = 5 mA/V , and VA = 60 V. The signal vsig has a zero average. (a) It is required to bias the transistor to operate at an overdrive voltage VOV = 0.2 V. What must the dc voltage at the drain be? Calculate the dc drain current ID taking into account VA . Now, what value must the drain resistance RD have? (b) Calculate the values of gm and ro at the bias point established in (a). (c) Using the small-signal equivalent circuit of the amplifier, show that the voltage gain is given by
D **7.124 The MOSFET in the amplifier circuit of 2 Fig. P7.124 has Vt = 0.6 V and kn = 5 mA/V . We shall assume that VA is sufficiently large so that we can ignore the Early effect. The input signal vsig has a zero average. (a) It is required to bias the transistor to operate at an overdrive voltage VOV = 0.2 V. What must the dc voltage at the drain be? Calculate the dc drain current ID . What value must RD have? (b) Calculate the value of gm at the bias point. (c) Use the small-signal equivalent circuit of the amplifier to show that vo vsig
vo vsig
1+
R2 /R1
=− 1+
1 + R2 /R1
1 + (R2 /R1 )
=
(1 + R2 /R1 ) gm RD0006
and
gm (RD ro R2 )(1 − 1/gm R2 )
1 R1 0006 (1 + gm RD ) gm R1 + R2
Rin = and find the value of the gain. where
0006
RD = RD (R1 + R2 )
VDD = + 10 V
(d) Evaluate vo /vsig and Rin .
RD R2 R1
2 M0006
VDD = + 10 V
vo
RD
500 k0006 R2
vsig 0002 0003
vo
0.5 M0006
R1
0.5 M0006
Figure P7.123
P.S. This feedback amplifier and the gain expression should remind you of an op amp utilized in the inverting configuration. We shall study feedback formally in Chapter 11.
0002 vsig 0003
Rin Figure P7.124
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 501
D 7.126 Using the topology of Fig. P7.125, design an amplifier to operate between a 2-k0002 source and a 2-k0002 load with a gain v o /v sig of –40 V/V. The power supply available is 15 V. Use an emitter current of approximately 2 mA and a current of about one-tenth of that in the voltage divider that feeds the base, with the dc voltage at the base about one-third of the supply. The transistor available has β = 100. Use standard 5% resistors (see Appendix J).
D 7.128 The CE amplifier circuit of Fig. P7.128 is biased with a constant-current source I. It is required to design the circuit (i.e., find values for I, RB , and RC ) to meet the following specifications:
PROBLEMS
7.125 For the common-emitter amplifier shown in Fig. P7.125, let VCC = 15 V, R1 = 27 k0002, R2 = 15 k0002, RE = 2.4 k0002, and RC = 3.9 k0002. The transistor has β = 100. Calculate the dc bias current IC . If the amplifier operates between a source for which Rsig = 2 k0002 and a load of 2 k0002, replace the transistor with its hybrid-π model, and find the values of Rin , and the overall voltage gain v o /v sig .
of the source by the amplifier input. As an experiment, the designer varies the resistance levels by a factor of approximately 3: R1 to 82 k0002, R2 to 47 k0002, RE to 7.2 k0002, and RC to 12 k0002 (standard values of 5%-tolerance resistors). With VCC = 15 V, Rsig = 2 k0002, RL = 2 k0002, and β = 100, what does the gain become? Comment.
CHAPTER 7
P.S. This feedback amplifier circuit and the gain formula should remind you of an op amp connected in the noninverting configuration. We shall study feedback formally in Chapter 11.
(a) Rin 0004 10 k0002. (b) The dc voltage drop across RB is approximately 0.2 V. (c) The open-circuit voltage gain from base to collector is the maximum possible, consistent with the requirement that the collector voltage never fall by more than approximately 0.4 V below the base voltage with the signal between base and emitter being as high as 5 mV. Assume that v sig is a sinusoidal source, the available supply VCC = 5 V, and the transistor has β = 100. Use standard 5% resistance values, and specify the value of I to one significant digit. What base-to-collector open-circuit voltage gain does your design provide? If Rsig = RL = 20 k0002, what is the overall voltage gain?
Figure P7.125
D 7.127 A designer, having examined the situation described in Problem 7.125 and estimating the available gain to be approximately –36.3 V/V, wants to explore the possibility of improvement by reducing the loading
Figure P7.128
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PROBLEMS
502 Chapter 7 Transistor Amplifiers D 7.129 In the circuit of Fig. P7.129, v sig is a small sine-wave signal with zero average. The transistor β is 100. (a) Find the value of RE to establish a dc emitter current of about 0.5 mA.
3V
*7.130 The amplifier of Fig. P7.130 consists of two identical common-emitter amplifiers connected in cascade. Observe that the input resistance of the second stage, Rin2 , constitutes the load resistance of the first stage.
CHAPTER 7
Rsig
(b) Find RC to establish a dc collector voltage of about +0.5 V. (c) For RL = 10 k0002, draw the small-signal equivalent circuit of the amplifier and determine its overall voltage gain.
(a) For VCC = 15 V, R1 = 100 k0002, R2 = 47 k0002, RE = 3.9 k0002, RC = 6.8 k0002, and β = 100, determine the dc collector current and dc collector voltage of each transistor. (b) Draw the small-signal equivalent circuit of the entire amplifier and give the values of all its components. (c) Find Rin1 and v b1 /v sig for Rsig = 5 k0002. (d) Find Rin2 and v b2 /v b1 . (e) For RL = 2 k0002, find v o /v b2 . (f) Find the overall voltage gain v o /v sig .
2.5 k
vsig
3V Figure P7.129
Rsig
vsig
in
in
Figure P7.130
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 503
7.133 For the circuit in Fig. P7.133, find the input resistance Rin and the voltage gain v o /v sig . Assume that the source provides a small signal v sig and that β = 100.
5k
Rsig
50 vsig
Figure P7.131
*7.132 The BJT in the circuit of Fig. P7.132 has β = 100. (a) Find the dc collector current and the dc voltage at the collector. (b) Replacing the transistor by its T model, draw the small-signal equivalent circuit of the amplifier. Analyze the resulting circuit to determine the voltage gain v o /v i .
Rin Figure P7.133
7.134 For the emitter-follower circuit shown in Fig. P7.134, the BJT used is specified to have β values in the range of 50 to 200 (a distressing situation for the circuit designer).
+3V
vsig in
Figure P7.132
Figure P7.134
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
0.5 mA
CHAPTER 7
7.131 In the circuit of Fig. P7.131, the BJT is biased with a constant-current source, and v sig is a small sine-wave signal. Find Rin and the gain v o /v sig . Assume β = 100. If the amplitude of the signal v be is to be limited to 5 mV, what is the largest signal at the input? What is the corresponding signal at the output?
PROBLEMS
For the two extreme values of β (β = 50 and β = 200), find:
CHAPTER 7
504 Chapter 7 Transistor Amplifiers
7.135 For the emitter follower in Fig. P7.135, the signal source is directly coupled to the transistor base. If the dc component of v sig is zero, find the dc emitter current. Assume β = 100. Neglecting ro , find Rin , the voltage gain v o /v sig , the current gain io /ii , and the output resistance Rout .
(a) IE , VE , and VB (b) the input resistance Rin (c) the voltage gain v o /v sig
3
Figure P7.136
2
vsig
**7.137 For the follower circuit in Fig. P7.137, let transistor Q1 have β = 50 and transistor Q2 have β = 100, and neglect the effect of ro . Use VBE = 0.7 V. 5
Rin
Rout
Figure P7.135
**7.136 For the circuit in Fig. P7.136, called a bootstrapped follower: (a) Find the dc emitter current and gm , re , and rπ . Use β = 100. (b) Replace the BJT with its T model (neglecting ro ), and analyze the circuit to determine the input resistance Rin and the voltage gain v o /v sig . (c) Repeat (b) for the case when capacitor CB is open-circuited. Compare the results with those obtained in (b) to find the advantages of bootstrapping.
50 A Rin
Figure P7.137
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
5 mA
Problems 505
(d) If the circuit is fed with a source having a 100-k0002 resistance, find the transmission to the base of Q1 , v b1 /v sig . (e) Find the overall voltage gain v o /v sig .
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
D A CE amplifier has a midband voltage gain of 0002 0002 7.138 0002AM 0002 = 100 V/V, a lower 3-dB frequency of fL = 100 Hz, and a higher 3-dB frequency fH = 500 kHz. In Chapter 10 we will learn that connecting a resistance Re in the emitter of the BJT 0007 0006 results in lowering fL and raising fH by the factor 1 + gm Re . If the BJT is biased at IC = 1 mA, find Re that will result in fH at least equal to 2 MHz. What will the new values of fL and AM be?
CHAPTER 7
(a) Find the dc emitter currents of Q1 and Q2 . Also, find the dc voltages VB1 and VB2 . (b) If a load resistance RL = 1 k0002 is connected to the output terminal, find the voltage gain from the base to the emitter of Q2 , v o /v b2 , and find the input resistance Rib2 looking into the base of Q2 . (Hint: Consider Q2 as an emitter follower fed by a voltage v b2 at its base.) (c) Replacing Q2 with its input resistance Rib2 found in (b), analyze the circuit of emitter follower Q1 to determine its input resistance Rin , and the gain from its base to its emitter, v e1 /v b1 .
576 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers stack between the power-supply rails results in the disadvantage of a severely limited output-signal swing. The folded-cascode configuration helps resolve this issue. 0002
A CS amplifier with a resistance Rs in its source lead has an output resistance Ro 0005 1 + gm Rs ro . The corresponding
000e formula for the BJT case is Ro = 1 + gm Re rπ ro .
0002
Cascoding can be applied to current mirrors to increase their output resistances. An alternative that also solves the β problem in the bipolar case is the Wilson circuit. The
MOS Wilson mirror has an output resistance of gm ro ro , 1 and the BJT version has an output resistance of 2 βro . Both the cascode and Wilson mirrors require at least 1 V or so for proper operation.
0002
The Widlar current source provides an area-efficient way to implement a low-valued constant-current source that also has a high output resistance.
0002
Preceding the CE (CS) transistor with an emitter follower (a source follower) results in increased input resistance in the BJT case and wider bandwidth in both the BJT and MOS cases.
0002
Preceding the CB (CG) transistor with an emitter follower (a source follower) solves the low-input-resistance problem of the CB and CG configurations.
0002
The Darlington configuration results in an equivalent BJT 2 with a current gain approaching β .
PROBLEMS Computer Simulation Problems Problems identified by the multisim/PSpice icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion. Instructions to assist in setting up PSpice and Multism simulations for all the indicated problems can be found in the corresponding files on the website. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
Section 8.2: IC Biasing—Current Sources, Current Mirrors, and Current-Steering Circuits D 8.1 For VDD = 1.3 V and using IREF = 100 μA, it is required to design the circuit of Fig. 8.1 to obtain an output current whose nominal value is 100 μA. Find R if Q1 and Q2 are matched with channel lengths of 0.5 μm, channel widths 0002 2 of 5 μm, Vt = 0.4 V, and kn = 500 μA/V . What is the lowest possible value of VO ? Assuming that for this process 0002 technology the Early voltage VA = 5 V/μm, find the output resistance of the current source. Also, find the change in output current resulting from a +0.5-V change in VO . D 8.2 Using VDD = 1.8 V and a pair of matched MOSFETs, design the current-source circuit of Fig. 8.1 to provide an output current of 150-μA nominal value. To simplify matters,
assume that the nominal value of the output current is obtained at VO 0005 VGS . It is further required that the circuit operate for VO in the range of 0.3 V to VDD and that the change in IO over this range be limited to 10% of the nominal value of IO . Find the required value of R and the device dimensions. For the fabrication-process technology utilized, μn Cox = 2 0002 400 μA/V , VA = 10 V/μm, and Vt = 0.5 V. D 8.3 Sketch the p-channel counterpart of the current-source circuit of Fig. 8.1. Note that while the circuit of Fig. 8.1 should more appropriately be called a current sink, the corresponding 0007 0007 PMOS circuit is a current source. Let VDD = 1.3 V, 0007Vt 0007 = 2 0.4 V, Q1 and Q2 be matched, and μp Cox = 80 μA/V . Find the device W/L ratios and the value of the resistor that sets the value of IREF so that a nominally 80-μA output current is obtained. The current source is required to operate for VO as high as 1.1 V. Neglect channel-length modulation. 8.4 Consider the current-mirror circuit of Fig. 8.2 with two transistors having equal channel lengths but with Q2 having a width five times that of Q1 . If IREF is 20 μA and the transistors are operating at an overdrive voltage of 0.2 V, what IO results? What is the minimum allowable value of VO for proper operation of the current source? If Vt = 0.5 V, at what value of VO will the nominal value of IO be obtained? If VO increases by 1 V, what is the corresponding increase in IO ? Let VA = 20 V.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 577
VDD
Q4
8.8 Consider the basic bipolar current mirror of Fig. 8.7 for the case in which Q1 and Q2 are identical devices having −17 IS = 10 A.
IO
Q1
Q2
Figure P8.5
D 8.6 The current-steering circuit of Fig. P8.6 is fabricated in 2 a CMOS technology for which μn Cox = 400 μA/V , μp Cox = 2 0002 100 μA/V , Vtn = 0.5 V Vtp = −0.5 V, VAn = 5 V/μ m, and 0002 |VAp | = 5 V/μm. If all devices have L = 0.5 μm, design the circuit so that IREF = 20 μA, I2 = 100 μA, I3 = I4 = 40 μA, and I5 = 80 μA. Use the minimum possible device widths needed to achieve proper operation of the current source Q2 for voltages at its drain as high as +0.8 V and proper operation of the current sink Q5 with voltages at its drain as low as –0.8 V. Specify the widths of all devices and the value of R. Find the output resistance of the current source Q2 and the output resistance of the current sink Q5 .
00031.0 V
Q1
Q2
I3
R
I4
I2
8.9 Consider the basic BJT current mirror of Fig. 8.7 for the case in which Q2 has m times the area of Q1 . Show that the current transfer ratio is given by Eq. (8.19). If β is specified to be a minimum of 80, what is the largest current transfer ratio possible if the error introduced by the finite β is limited to 10%? 8.10 Give the circuit for the pnp version of the basic current mirror of Fig. 8.7. If β of the pnp transistor is 50, what is the current gain (or transfer ratio) IO /IREF for the case of identical transistors, neglecting the Early effect?
Q3
IREF
(a) Assuming the transistor β is very high, find the range of VBE and IO corresponding to IREF increasing from 10 μA to 10 mA. Assume that Q2 remains in the active mode, and neglect the Early effect. (b) Find the range of IO corresponding to IREF in the range of 10 μA to 10 mA, taking into account the finite β. Assume that β remains constant at 100 over the current range 0.1 mA to 5 mA but that at IC 000510 mA and at IC 0005 10 μA, β = 50. Specify IO corresponding to IREF = 10 μA, 0.1 mA, 1 mA, and 10 mA. Note that β variation with current causes the current transfer ratio to vary with current.
I5 Q4
Q5
00021.0 V Figure P8.6
*8.7 A PMOS current mirror consists of three PMOS transistors, one diode connected and two used as current
8.11 Consider the basic BJT current mirror of Fig. 8.7 when Q1 and Q2 are matched and IREF = 1 mA. Neglecting the effect of finite β, find the change in IO , both as an absolute value and as a percentage, corresponding to VO changing from 1 V to 10 V. The Early voltage is 90 V. D 8.12 The current-source circuit of Fig. P8.12 utilizes a pair −15 pnp transistors having IS = 10 A, β = 50, and 0007of matched 0007 0007VA 0007 = 50 V. It is required to design the circuit to provide an output current IO = 1 mA at VO = 1 V. What values of IREF and R are needed? What is the maximum allowed value of VO while the current source continues to operate properly? What change occurs in IO corresponding to VO changing from the
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
Q3
I REF
0007 0007 0002 2 outputs. All transistors have 0007Vt 0007 = 0.6 V, kp = 100 μA/V , and L = 1.0 μm but three different widths, namely, 10 μm, 20 μm, and 40 μm. When the diode-connected transistor is supplied from a 100-μA source, how many different output currents are available? Repeat with two of the transistors diode connected and the third used to provide current output. For each possible input-diode combination, give the values of the output currents and of the VSG that results.
CHAPTER 8
8.5 For the current-steering circuit of Fig. P8.5, find IO in terms of IREF and device W/L ratios.
CHAPTER 8
PROBLEMS
578 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers VCC
Q1
0007 0007 8.14 For the circuit in Fig. P8.14, let 0007VBE 0007 = 0.7 V and β = ∞. Find I, V1 , V2 , V3 , V4 , and V5 for (a) R = 10 k0003 and (b) R = 100 k0003.
3V
+ 2.7 V
Q2 IO
IREF
VO
R
Figure P8.12
maximum positive value to –5 V? Hint: Adapt Eq. (8.21) for this case as: ⎤ ⎡ 3 − VO − VEB 1+ ⎥ ⎢ |VA | ⎥ IO = IREF ⎢ ⎦ ⎣ 2 1+ β 8.13 Find the voltages at all nodes and the currents 0007 0007 through all branches in the circuit of Fig. P8.13. Assume 0007VBE 0007 = 0.7 V and β = ∞.
– 2.7 V Figure P8.14
000310 V
00035 V
R5 0004 10 k0007
R2 0004 8 k0007
R1 0004 20 k0007
R4 0004 5 k0007
R3 0004 3.6 k0007
00025 V Figure P8.13 = Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 579
Y
X
Q2
8.19 Figure P8.19 shows an amplifier utilizing a current mirror Q2 –Q3 . Here Q1 is a common-source amplifier fed with v I = VGS + v i , where VGS is the gate-to-source dc bias voltage of Q1 and v i is a small signal to be amplified. Find the signal component of the output voltage v O and hence the small-signal voltage gain v o /v i . Also, find the small-signal resistance of the diode-connected transistor Q2 in terms of gm2 , and hence the total resistance between the drain of Q1 and ground. What is the voltage gain of the CS amplifier Q1 ? Neglect all ro ’s.
VDD
Q1 Z
0003 WL 0004 Q 2
Q3
Q4
0003 0004
Q3 W3 L
2
vO Q5
VEE Figure P8.16
(a) Assuming that Y is connected to a voltage V , a current I is forced into X, and terminal Z is connected to a voltage that keeps Q5 in the active region, show that a current equal to I flows through terminal Y, that a voltage equal to V appears at terminal X, and that a current equal to I flows through terminal Z. Assume β to be large; corresponding transistors are matched, and all transistors are operating in the active region. (b) With Y connected to ground, show that a virtual ground appears at X. Now, if X is connected to a +5-V supply through a 10-k0003 resistor, what current flows through Z?
vI
Q1
RL
Figure P8.19
*8.20 Figure P8.20 shows a current-mirror circuit prepared for small-signal analysis. Replace the BJTs with their hybridπ models and find expressions for Rin , io /ii , and Ro , where io is the output short-circuit current. Assume ro rπ .
ii Rin Ro
io Q1
Q2
8.17 The MOSFETs in the current mirror of Fig. 8.12(a) have equal channel lengths of 0.5 μm, W1 = 10 μm, W2 = 50 μm, 2 0002 μn Cox = 500 μA/V , and VA = 10 V/μm. If the input bias current is 100 μA, find Rin , Ais , and Ro . D 8.18 The MOSFETs in the current mirror of Fig. 8.12(a) 2 0002 have equal channel lengths, μn Cox = 400 μA/V and VA = 20 V/μm. If the input bias current is 200 μA, find W1 , W2 , and L
Figure P8.20
8.21 It is required to find the incremental (i.e., small-signal) resistance of each of the diode-connected transistors shown in
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
*8.16 The circuit shown in Fig. P8.16 is known as a current conveyor.
to obtain a short-circuit current gain of 4, an input resistance of 500 0003, and an output resistance of 20 k0003.
CHAPTER 8
D 8.15 Using the ideas embodied in Fig. 8.10, design a multiple-mirror circuit using power supplies of ±5 V to create source currents of 0.2 mA, 0.4 mA, and 0.8 mA and sink currents 0007 of0007 0.5 mA, 1 mA, and 2 mA. Assume that the BJTs have 0007VBE 0007 0005 0.7 V and large β. What is the total power dissipated in your circuit?
Fig. P8.21. Assume that the dc bias current I = 0.1 mA. For 2 the MOSFET, let μn Cox = 200 μA/V and W/L = 10. Neglect ro for both devices.
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PROBLEMS
580 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers
I
I
8.26 Consider the CE amplifiers of Fig. 8.13(b) for the case of I = 0.5 mA, β = 100, and VA = 100 V. Find Rin , Av o , and Ro . If it is required to raise Rin by a factor of 5 by changing I, what value of I is required, assuming that β remains unchanged? What are the new values of Av o and Ro ? If the amplifier is fed with a signal source having Rsig = 5 k0003 and is connected to a load of 100-k0003 resistance, find the overall voltage gain, v o /v sig . 8.27 Find the intrinsic gain of an NMOS transistor fabricated 0002 2 0002 in a process for which kn = 400 μA/V and VA = 10 V μm. The transistor has a 0.5-μm channel length and is operated at VOV = 0.2 V. If a 2-mA/V transconductance is required, what must ID and W be?
(a)
(b)
Figure P8.21
8.22 For the base-current-compensated mirror of Fig. 8.11, let the three transistors be matched and specified to have a collector current of 1 mA at VBE = 0.7 V. For IREF of 100 μA and assuming β = 100, what will the voltage at node x be? If IREF is increased to 1 mA, what is the change in Vx ? What is the value of IO obtained with VO = Vx in both cases? Give the percentage difference between the actual and ideal value of IO . What is the lowest voltage at the output for which proper current-source operation is maintained? D 8.23 Extend the current-mirror circuit of Fig. 8.11 to n outputs. What is the resulting current transfer ratio from the input to each output, IO /IREF ? If the deviation from unity is to be kept at 0.2% or less, what is the maximum possible number of outputs for BJTs with β = 150? *8.24 For the base-current-compensated mirror of Fig. 8.11, show that the incremental input resistance (seen by the reference current source) is approximately 2VT /IREF . Evaluate Rin for IREF = 100 μA. (Hint: Q3 is operating at a current IE3 = 2IC /β, where IC is the operating current of each of Q1 and Q2 . Replace each transistor with its T model and neglect r0 .)
8.28 An NMOS transistor fabricated in a certain process is found to have an intrinsic gain of 50 V/V when operated at an ID of 100 μA. Find the intrinsic gain for ID = 25 μA and ID = 400 μA. For each of these currents, find the factor by which gm changes from its value at ID = 100 μA. D 8.29 Consider an NMOS transistor fabricated in a 0002 2 0002 0.18-μm technology for which kn = 400 μA/V and VA = 5 V/μm. It is required to obtain an intrinsic gain of 20 V/V and a gm of 2 mA/V. Using VOV = 0.2 V, find the required values of L, W/L, and the bias current I. D 8.30 Sketch the circuit for a current-source-loaded CS amplifier that uses a PMOS transistor for the amplifying device. Assume the availability of a single dc 0007 +1.8-V 0007 supply. If the transistor is operated with 0007VOV 0007 = 0.2 V, what is the highest instantaneous voltage allowed at the drain? 8.31 An NMOS transistor operated with an overdrive voltage of 0.25 V is required to have a gm equal to that of an npn transistor operated at IC = 0.1 mA. What must ID be? What value of gm is realized?
Section 8.3: The Basic Gain Cell
8.32 For an NMOS transistor with L = 1 μm fabricated in the 0.5-μm process specified in Table J.1 in Appendix J, find gm , ro , and A0 if the device is operated with VOV = 0.5 V and ID = 100 μA. Also, find the required device width W.
8.25 Find gm , rπ , ro , and A0 for the CE amplifier of Fig. 8.13(b) when operated at I = 10 μA, 100 μA, and 1 mA. Assume β = 100 and remains constant as I is varied, and that VA = 10 V. Present your results in a table.
8.33 For an NMOS transistor with L = 0.3 μm fabricated in the 0.18-μm process specified in Table J.1 in Appendix J, find gm , ro , and A0 obtained when the device is operated at ID = 100 μA with VOV = 0.2 V. Also, find W.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 581
BJT Cell
MOSFET Cell
Bias Current
8.36 A CS amplifier utilizes an NMOS transistor with L = 0.36 μm and W/L = 8. It was fabricated in a 0.18-μm CMOS 2 0002 process for which μn Cox = 400 μA/V and VA = 5 V/μm. Find the values of gm and A0 obtained at ID = 25 μA, 250 μA, and 2.5 mA. D 8.37 An NMOS transistor is fabricated in the 0.18-μm process whose parameters are given in Table J.1 in Appendix J. The device has a channel length twice the minimum and is operated at VOV = 0.25 V and ID = 10 μA.
D 8.40 The circuit in Fig. 8.15(a) is fabricated 0007 0002in0007 a process for 2 0002 which μn Cox = 2μp Cox = 200 μA/V , VAn = 0007VAp 0007 = 20 V/μm, Vtn = −Vtp = 0.5 V, and VDD = 2.5 V. The two transistors have L = 0.5 μm and are to be operated at ID = 100 μA and |VOV | = 0.3 V. Find the required values of VG , (W/L)1 , (W/L)2 , and Av . D 8.41 The circuit in Fig. 8.15(a) is fabricated in a 0.18-μm 2 CMOS technology for which μn Cox = 400 μA/V , μ 0007 p C0002 ox0007 = 2 0002 100 μA/V , Vtn = −Vtp = 0.5 V, VAn = 5 V/μm, 0007VAp 0007 = 5 V/μm, and VDD = 1.8 V. It is required to design the circuit to obtain a voltage gain Av = −40 V/V. Use 0007 0007devices of equal length L operating at I = 100 μA and 0007VOV 0007 = 0.25 V. Determine the required values of VG , L, (W/L)1 , and (W/L)2 . 8.42 Figure P8.42 shows an IC MOS amplifier formed by cascading two common-source stages. Assuming that 0007 0007 VAn = 0007VAp 0007 and that the biasing current sources have output resistances equal to those of Q1 and Q2 , find an expression for the overall voltage gain in terms of gm and ro of Q1 and Q2 . If Q1 and Q2 are to be operated at equal overdrive voltages, |VOV |, find the required value of |VOV | if |VA | = 5 V and the gain required is 400 V/V.
(a) What values of gm , ro , and A0 are obtained? (b) If ID is increased to 100 μA, what do VOV , gm , ro , and A0 become? (c) If the device is redesigned with a new value of W so that it operates at VOV = 0.25 V for ID = 100 μA, what do gm , ro , and A0 become? (d) If the redesigned device in (c) is operated at 10 μA, find VOV , gm , ro , and A0 . (e) Which designs and operating conditions produce the lowest and highest values of A0 ? What are these values? In each of these two cases, if W/L is held at the same value but L is made 10 times larger, what gains result? D 8.38 Find A0 for an NMOS transistor fabricated in a CMOS 0002 2 0002 process for which kn = 400 μA/V and VA = 6 V/μm. The transistor has a 0.5-μm channel length and is operated with an overdrive voltage of 0.15 V. What must W be for the NMOS transistor to operate at ID = 100 μA? Also, find the values of gm and ro . D 8.39 Using a 0002 2 kn = 200 μA/V
CMOS technology for which 0002 and VA = 20 V/μm, design a
Figure P8.42
*8.43 The NMOS transistor in the circuit of Fig. P8.43 has 0002 2 Vt = 0.5 V, kn W/L = 2 mA/V , and VA = 20 V. (a) Neglecting the dc current in the feedback network and the effect of ro , find VGS . Then find the dc current in the feedback network and VDS . Verify that you were justified in neglecting the current in the feedback network when you found VGS .
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
8.35 A CS amplifier utilizes an NMOS transistor with L = 0.54 μm and W/L = 8. It was fabricated in a 0.18-μm 2 0002 CMOS process for which μn Cox = 400 μA/V and VA = 5 V/μm. What is the bias current of the transistor for which A0 = 18 V/V?
current-source-loaded CS amplifier for operation at I = 50 μA with VOV = 0.2 V. The amplifier is to have an open-circuit voltage gain of −100 V/V. Assume that the current-source load is ideal. Specify L and W/L.
CHAPTER 8
8.34 Fill in the table below. For the BJT, let β = 100 and 2 VA = 100 V. For the MOSFET, let μn Cox = 200 μA/ V , W/L = 40, and VA = 10 V.
CHAPTER 8
PROBLEMS
582 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers
200 A 3 M0007
vo
vi 2 M0007 Rin
Figure P8.43
(b) Find the small-signal voltage gain, v o /v i . What is the peak of the largest output sine-wave signal that is possible while the NMOS transistor remains in saturation? What is the corresponding input signal? (c) Find the small-signal input resistance Rin . D 8.44 Consider the CMOS amplifier of Fig. 8.16(a) when 0002 0002 2 with a 0007process for which kn = 4kp = 400 μA/V , 0007fabricated 0007 0007 0007Vt 0007 = 0.5 V, and 0007VA 0007 = 5 V. Find IREF and (W/L)1 to obtain a voltage gain of –40 V/V and an output resistance of 100 k0003. Recall that Q2 and Q3 are matched. If Q2 and Q3 are to be operated at the same overdrive voltage as Q1 , what must their W/L ratios be? 8.45 Consider the CMOS amplifier analyzed in Example 8.4. If v I consists of a dc bias component on which is superimposed a sinusoidal signal, find the value of the dc component that will result in the maximum possible signal swing at the output with almost-linear operation. What is the amplitude of the output sinusoid resulting? (Note: In practice, the amplifier would have a feedback circuit that caused it to operate at a point near the middle of its linear region.) 8.46 The power supply of the CMOS amplifier analyzed in Example 8.4 is increased to 5 V. What will the extent of the linear region at the output become? **8.47 Consider the circuit shown in 0007Fig. 0007 8.16(a), using a 3.3-V supply and transistors for which 0007Vt 0007 = 0.8 V and L = 0002 2 1 μm. For Q1 , kn = 100 μA/V , VA = 100 0007 V, 0007 and W = 20 μm. 0002 2 For Q2 and Q3 , kp = 50 μA/V and 0007VA 0007 = 50 V. For Q2 , W = 40 μm. For Q3 , W = 10 μm. (a) If Q1 is to be biased at 100 μA, find IREF . For simplicity, ignore the effect of VA .
(b) What are the extreme values of v O for which Q1 and Q2 just remain in saturation? (c) What is the large-signal voltage gain? (d) Find the slope of the transfer characteristic at v O = VDD /2. (e) For operation as a small-signal amplifier around a bias point at v O = VDD /2, find the small-signal voltage gain and output resistance. **8.48 The MOSFETs in the circuit of Fig. P8.48 0007 0007are 0002 0002 2 matched, having kn (W/L)1 = kp (W/L)2 = 1 mA/V and 0007Vt 0007 = 0.5 V. The resistance R = 1 M0003. (a) For G and D open, what are the drain currents ID1 and ID2 ? (b) For ro = ∞, what is the voltage gain of the amplifier from G to D? (Hint: Replace the transistors with their small-signal 0007models.) 0007 (c) For finite ro (0007VA 0007 = 20 V), what is the voltage gain from G to D and the input resistance at G? (d) If G is driven (through a large coupling capacitor) from a source v sig having a resistance of 20 k0003, find the voltage gain v d /v sig . (e) For what range of output signals do Q1 and Q2 remain in the saturation region?
00031.0 V
Q2 R G
D Q1
00021.0 V Figure P8.48
8.49 Transistor Q1 in the circuit of Fig. P8.49 is operating as a CE amplifier with an active load provided by transistor Q2 , which is the output transistor in a current mirror formed by Q2 and Q3 . (Note that the biasing arrangement for Q1 is not shown.) (a) Neglecting the finite base currents of Q2 and Q3 and assuming that their VBE 0005 0.7 V and that Q2 has five times the area of Q3 , find the value of I.0007 0007 (b) If Q1 and Q2 are specified to have 0007VA 0007 = 30 V, find ro1 and ro2 and hence the total resistance at the collector of Q1 .
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 583
D 8.53 It is required to design the current source in Fig. P8.53 to deliver a current of 0.2 mA with an output resistance of 500 k0003. The transistor has VA = 20 V and Vt = 0.5 V. Design for VOV = 0.2 V and specify Rs and VBIAS .
0003VCC 0004 00033 V
PROBLEMS
vi
what percentage does the current gain change? Can you see the effectiveness of the CG as a current buffer?
Q1 IO
00033 V vo
46 k0007
VBIAS
I Rs Q3
Q2
Figure P8.53 Figure P8.49
D 8.50 It is required to design the CMOS amplifier of 0002 Fig. 8.16(a) utilizing a 0.18-μm process for which kn = 2 0002 2 387 μA/V , kp = 86 μA/V , Vtn = −Vtp = 0.5 V, VDD = 1.8 V, 0002 0002 VAn = 5 V/μm, and VAp = −6 V/μm. The output voltage must be able to swing to within approximately 0.2 V of the power-supply rails (i.e., from 0.2 V to 1.6 V), and the voltage gain must be at least 10 V/V. Design for a dc bias current of 50 μA, and use devices with the same channel length. If the channel length is an integer multiple of the minimum 0.18 μm, what channel length is needed and what W/L ratios are required? If it is required to raise the gain by a factor of 2, what channel length would be required, and by what factor does the total gate area of the circuit increase?
D 8.54 Figure P8.54 shows a current source realized using a current mirror with two matched transistors Q1 and Q2 . Two equal resistances Rs are inserted in the source leads to increase the output resistance of the current source. If Q2 is operating at gm = 1 mA/V and has VA = 10 V, and if the maximum allowed dc voltage drop across Rs is 0.3 V, what is the maximum available output resistance of the current source? Assume that the voltage at the common-gate node is approximately constant.
100 A Rout Q1
Q2
Section 8.4: The CG and CB Amplifiers 8.51 A CG amplifier operating with gm = 2 mA/V and ro = 20 k0003 is fed with a signal source having Rs = 1 k0003 and is loaded in a resistance RL = 20 k0003. Find Rin , Rout , and vo /vsig . 8.52 A CG amplifier operating with gm = 2 mA/V and ro = 20 k0003 is fed with a signal source having a Norton equivalent composed of a current signal isig and a source resistance Rs = 20 k0003. The amplifier is loaded in a resistance RL = 20 k0003. Find Rin and io /isig , where io is the current through the load RL . If RL increases by a factor of 10, by
Rs
CHAPTER 8
(c) Find rπ 1 and gm1 assuming that β1 = 50. (d) Find Rin , Av , and Ro .
Rs
Figure P8.54
8.55 In the common-gate amplifier circuit of Fig. P8.55, 0002 0002 2 Q2 and Q3 are matched. kn (W/L)n = kp (W/L)p = 4 mA/V , and all transistors have |Vt | = 0.8 V and |VA | = 20 V.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
584 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers
CHAPTER 8
PROBLEMS
3.3 V
Q3
Q2 vo
100 A
RL Rout
Q1
VBIAS 50 0007 vi vsig
0003 0002
it to the collector and supplies the output collector current at a high output resistance. Figure P8.59 shows a CB amplifier fed with a signal current isig having a source resistance Rsig = 10 k0003. The BJT is specified to have β = 100 and VA = 50 V. (Note that the bias arrangement is not shown.) The output at the collector is represented by its Norton equivalent circuit. Find the value of the current gain k and the output resistance Rout . Note that k is the short-circuit current gain and should be evaluated using the T model of the transistor with the collector short-circuited to ground.
Rin 0.1 mA
Figure P8.55
C
C
The signal vsig is a small sinusoidal signal with no dc component. (a) Neglecting the effect of VA , find the dc drain current of Q1 and the required value of VBIAS . (b) Find the values of gm1 and ro for all transistors. (c) Find the value of Rin . (d) Find the value of Rout . (e) Calculate the voltage gains vo /vi and vo /vsig . (f) How large can vsig be (peak-to-peak) while maintaining saturation-mode operation for Q1 and Q2 ? 8.56 For the CB amplifier, use Eq. (8.63) to explore the variation of the input resistance Rin with the load resistance RL . Specifically, find Rin as a multiple of re for RL /ro = 0, 1, 10, 100, 1000, and ∞. Let β = 100. Present your results in tabular form.
isig
Rsig = 10 k0007
Figure P8.59
8.60 For the constant-current source circuit shown in Fig. P8.60, find the collector current I and the output resistance. The BJT is specified to have β = 100, VBE = 0.7 V, and VA = 100 V. If the collector voltage undergoes a change of 10 V while the BJT remains in the active mode, what is the corresponding change in collector current?
8.57 What value of load resistance RL causes the input resistance of the CB amplifier to be approximately double the value of re ? 8.58 Show that for the CB amplifier,
I 5V
Rout β(Re /re ) 0005 1+ ro β + 1 + (Re /re ) Generate a table for Rout as a multiple of ro versus Re as a multiple of re with entries for Re = 0, re , 2 re , 10 re , (β/2) re , β re , and 1000 re . Let β = 100. 8.59 As mentioned in the text, the CB amplifier functions as a current buffer. That is, when fed with a current signal, it passes
kisig
4.3 k0007
Figure P8.60
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Rout
Problems 585
D 8.62 In a MOS cascode amplifier, the cascode transistor is required to raise the output resistance by a factor of 50. If the transistor is operated at VOV = 0.2 V, what must its VA be? If 0002 the process technology specifies VA as 5 V/μm, what channel length must the transistor have? D 8.63 For a cascode current source such as that in Fig. 8.32, show that if the two transistors are identical, the current I supplied by the current 0007 source 00072 0007 and 0007 the output resistance Ro are related by IRo = 20007 0007V0007A 0007 /0007VOV 0007. Now consider the0007 case0007 of transistors that have 0007VA 0007 = 4 V and are operated at 0007VOV 0007 of 2 0.2 V. Also, let μp Cox = 100 μA/V . Find the W/L ratios required and the output resistance realized for the two cases: (a) I = 0.1 mA and (b) I = 0.5 mA. Assume 0007 that 0007 VSD for the two devices is the minimum required (i.e., 0007VOV 0007). D *8.64 For a cascode current source, such as that in Fig. 8.32, show that if the two transistors are identical, the current I supplied by the current source and the output resistance Ro are related by 0007 0002 00072 20007VA 0007 2 0007 0007L IRo = 0007VOV 0007
cases of L equal to the minimum channel length, twice the minimum, and three times the minimum. Complete the entries of the table at the bottom of the page. Give W/L and the area 2WL in terms of n, where n is the value of W/L for the case I = 0.01 mA. In the table, Av denotes the gain obtained in a cascode amplifier such as that in Fig. 8.33 that utilizes our current source as load and which has the same values of gm and Ro as the current-source transistors. (a) For each current value, what is price paid for the increase in Ro and Av obtained as L is increased? (b) For each value of L, what advantage is obtained as I is increased, and what is the price paid? (Hint: We will see in Chapter 10 that the amplifier bandwidth increases with gm .) (c) Contrast the performance obtained from the circuit with the largest area with that obtained from the circuit with the smallest area. D 8.65 Design the cascode amplifier of Fig. 8.30(a) to obtain gm1 = 2 mA/V and Ro = 200 k0003. Use a 0.18-μm technology 0002 0002 2 for which Vtn = 0.5 V, VA = 5 V/μm, and kn = 400 μA/V . Determine L, W/L, VG2 , and I. Use identical transistors operated at VOV = 0.25 V, and design for the maximum possible negative signal swing at the output. What is the value of the minimum permitted output voltage? 8.66 The cascode amplifier of Fig. 8.33 is0007 operated at a 0007 current of 0.2 mA with all devices operating at 0007VOV 0007 = 0.20 V.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
Section 8.5: The Cascode Amplifier
Now 0007 0002 0007 consider the case of a 0.18-μm technology for which 0007 0007 0007VA 0007 = 5 V/μm and let the transistors be operated at 0007VOV 0007 = 0.2 V. Find the figure-of-merit IRo for the three
CHAPTER 8
8.61 Find the value of the resistance Re , which, when connected in the emitter lead of a CE BJT amplifier, raises the output resistance by a factor of (a) 5, (b) 10, and (c) 50. What is the maximum possible factor by which the output resistance can be raised, and at what value of Re is it achieved? Assume the BJT has β = 100 and is biased at IC = 0.5 mA.
CHAPTER 8
PROBLEMS
586 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers 0007 0007 All devices have 0007VA 0007 = 4 V. Find gm1 , the output resistance of the amplifier, Ron , the output resistance of the current source, Rop , the overall output resistance, Ro , and the voltage gain, Av . D 8.67 Design the CMOS cascode amplifier in Fig. 8.33 for the following specifications: gm1 = 1 mA/V and Av = −280 0007 0002 0007 V/V. Assume that for the available fabrication process, 0007VA 0007 = 5 V/μm for both NMOS and PMOS devices and that 2 μn Cox = 4 μp Cox = 400 μA/V . Use the same0007channel length 0007 L for all devices and operate all four devices at 0007VOV 0007 = 0.25 V. Determine the required channel length L, the bias current I, and the W/L ratio for each of four transistors. Assume that suitable bias voltages have been chosen, and neglect the Early effect in determining the W/L ratios.
two circuits shown in Fig. P8.70(b) and (c). The circuit in Fig. P8.70(b) is a CS amplifier in which the channel length has been quadrupled relative to that of the original CS amplifier in Fig. P8.70(a) while the drain bias current has been kept constant.
vo vi
vo vi
W0002L
D 8.68 Design the circuit of Fig. 8.32 to provide an output current of 100 μA. Use VDD = 3.3 V, and assume the PMOS 2 transistors to have μp Cox = 60 μA/V , Vtp = −0.8 V, and 0007 0007 0007VA 0007 = 5 V. The current source is to have the widest possible signal swing at its output. Design for VOV = 0.2 V, and specify the values of the transistor W/L ratios and of VG3 and VG4 . What is the highest allowable voltage at the output? What is the value of Ro ? 8.69 The cascode transistor can be thought of as providing a “shield” for the input transistor from the voltage variations at the output. To quantify this “shielding” property of the cascode, consider the situation in Fig. P8.69. Here we have grounded the input terminal (i.e., reduced v i to zero), applied a small change v x to the output node, and denoted the voltage change that results at the drain of Q1 by v y . By what factor is v y smaller than v x ?
I
I
(a)
W00024L
(b)
I vo VBIAS
W0002L
vi
W0002L
(c) ix Figure P8.70
0003 vx 0002
Q2 vy Q1
Figure P8.69
*8.70 In this problem we investigate whether, as an alternative to cascoding, we can simply increase the channel length L of the CS MOSFET. Specifically, we wish to compare the
(a) Show that for this circuit VOV is double that of the original v circuit, gm is half that of the original circuit, and o is vi double that of the original circuit. (b) Compare these values to those of the cascode circuit in Fig. P8.70(c), which is operating at the same bias current and has the same minimum voltage requirement at the drain as in the circuit of Fig. P8.70(b). 8.71 Consider the cascode amplifier of Fig. 8.33 with the dc component at the input VI = 0.6 V, VG2 = 0.9 V, VG3 = 0.4 V, VG4 = 0.7 V, and VDD = 1.3 V. If all devices0007 are 0007 matched, that is, kn1 = kn2 = kp3 = kp4 , and have equal 0007Vt 0007 of 0.4 V, what is the overdrive voltage at which the four transistors are operating? What is the allowable voltage range at the output?
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 587
(a) Determine R1 , R2 , and R3 . Assume gm ro 1. (b) Determine i1 , i2 , i3 , i4 , i5 , i6 , and i7 , all in terms of v i . (Hint: Use the current-divider rule at the drain of Q1 .) (c) Determine v 1 , v 2 , and v 3 , all in terms of v i . (d) If v i is a 5-mV peak sine wave and gm ro = 20, sketch and clearly label the waveforms of v 1 , v 2 , and v 3 .
Q4
ro
i6
i7 v3
i5
R1
Q3
D 8.74 Design the double-cascode current source shown in Fig. P8.74 to provide I = 0.2 mA and the largest possible signal swing at the output; that is, design for the minimum allowable voltage across each transistor. The 0.13-μm CMOS fab0002 rication process available has Vtp = −0.4 V, VA = −6 V/μm, 2 and μp Cox = 0007 100 0007 μA/V . Use devices with L = 0.4 μm, and operate at 0007VOV 0007 = 0.2 V. Specify VG1 , VG2 , VG3 , and the W/L ratios of the transistors. What is the value of Ro achieved?
ro
VDD = 1.8 V
R2
i4
Q2
v2
ro
R3
i3
VG1
Q1
VG2
Q2
VG3
Q3 Ro
v1 i1
i2 Q1
0003
I
ro Figure P8.74
vi 0002 Figure P8.73
*8.75 Figure P8.75 shows a folded-cascode CMOS amplifier utilizing a simple current source Q2 , supplying a current 2I, and a cascoded current source (Q4 , Q5 ) supplying a current I. Assume, for simplicity, that all transistors have equal parameters gm and ro .
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
8.73 The purpose of this problem is to investigate the signal currents and voltages at various points throughout a cascode
amplifier circuit. Knowledge of this signal distribution is very useful in designing the circuit so as to allow for the required signal swings. Figure P8.73 shows a CMOS cascode amplifier with all dc voltages replaced with signal grounds. As well, we have explicitly shown the resistance ro of each of the four transistors. For simplicity, we are assuming that the four transistors have the same gm and ro . The amplifier is fed with a signal v i .
CHAPTER 8
8.72 A CMOS cascode amplifier such as that in Fig. 8.34(a) has identical CS and CG transistors that have W/L = 5.4 μm/0.36 μm and biased at I = 0.2 mA. The 2 0002 fabrication process has μn Cox = 400 μA/V , and VA = 5 V/μm. At what value of RL does the gain become –100 V/V? What is the voltage gain of the common-source stage?
(d) Find the overall voltage gain v o /v i and evaluate its value for the case gm1 = 2 mA/V and A0 = 30.
VDD
8.76 A cascode current source formed of two pnp transistors for which β = 50 and VA = 5 V supplies a current of 0.2 mA. What is the output resistance?
Q2
VG2
Ro2
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PROBLEMS
588 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers
vi
Q3
Q1
8.77 Use Eq. (8.88) to show that for a BJT cascode current source utilizing identical pnp transistors and supplying a current I, 0007 0007 0007VA 0007 IRo = 001c0007 0007
0007 VT VA 0007 + (1/β) 0007 0007 Evaluate the figure-of-merit IRo for the case 0007VA 0007 = 5 V and β = 50. Now find Ro for the cases of I = 0.1, 0.5, and 1.0 mA.
Rin3
Ro1
VG3 Ro3 Ro4
vo
Q4
VG4
Ro5 Q5
VG5
8.78 Consider the BJT cascode amplifier of Fig. 8.38 for the case all transistors have equal β and ro . Show that the voltage gain Av can be expressed in the form 0007 0007 1 001c00070007VA00070007 /VT Av = − 2 VT 0007VA 0007 + (1/β) 0007 0007 Evaluate Av for the case 0007VA 0007 = 5 V and β = 50. Note that except for the fact that β depends on I as a second-order effect, the gain is independent of the bias current I!
Ro
Figure P8.75
(a) Give approximate expressions for all the resistances indicated. (b) Find the amplifier output resistance Ro . (c) Show that the short-circuit transconductance Gm is approximately equal to gm1 . Note that the short-circuit transconductance is determined by short-circuiting vo to ground and finding the current that flows through the short circuit, Gm vi .
D *8.80 Figure P8.80 shows four possible realizations of the folded cascode amplifier. Assume that the BJTs have 0007 0007β = 100 and that both the BJTs and the MOSFETs have 0007VA 0007 = 5 V.
2I
2I
Q2 vI
8.79 A bipolar cascode amplifier has a current-source load 0007 0007 with an output resistance βro . Let β = 50, 0007VA 0007 = 100 V, and I = 0.2 mA. Find the voltage gain Av .
VBIAS vI
Q1
Q1
Q2
VBIAS
vo
vo I
I
(a)
(b)
Figure P8.80
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 589
vI
Q1
CHAPTER 8
2I
2I
Q2
VBIAS
vI
Q2
Q1
VBIAS
PROBLEMS
vo
vo I
I
(c)
(d)
Figure P8.80 continued
VDD
Let0007 I =0007100 μA, and assume that the MOSFETs are operating at 0007VOV 0007 = 0.2 V. Assume the current sources are ideal. For each circuit determine Rin , Ro , and Av o . Comment on your results. 8.81 In this problem, we will explore the difference between using a BJT as cascode device and a MOSFET as cascode device. Refer to Fig. P8.81. Given the following data, calculate Gm , Ro , and Avo for the circuits (a) and (b):
I vo VG2
Q2
vi
Q1
2
I = 100 μA, β = 125, μn Cox = 400 μA/V , W/L = 25, VA = 1.8 V
VDD
I
(b) vo
Figure P8.81 continued
Q2
VB2
Section 8.6: Current-Mirror Circuits with Improved Performance vi
Q1
(a) Figure P8.81
8.82 In a particular cascoded current mirror, such as that shown in Fig. 8.39, all transistors have Vt = 0.6 V, 2 μn Cox = 160 μA/V , L = 1 μm, and VA = 10 V. Width W1 = W4 = 4 μm, and W2 = W3 = 40 μm. The reference current IREF is 20 μA. What output current results? What are the voltages at the gates of Q2 and Q3 ? What is the lowest voltage at the output for which current-source operation is possible? What are the values of gm and
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
ro of Q2 and Q3 ? What is the output resistance of the mirror? 8.83 Find the output resistance of the double-cascode current mirror of Fig. P8.83.
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PROBLEMS
590 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers
Figure P8.85
D 8.86 Use the pnp version of the Wilson current mirror to design a 0.1-mA current source. The current source is required to operate with the voltage at its output terminal as low as –2.5 V. If the power supplies available are ±2.5 V, what is the highest voltage possible at the output terminal? Figure P8.83
8.84 Consider the Wilson current-mirror circuit of Fig. 8.40 when supplied with a reference current IREF of 1 mA. What is the change in IO corresponding to a change of +10 V in the voltage at the collector of Q3 ? Give both the absolute value and the percentage change. Let β = 100 and VA = 100 V. D 8.85 (a) The circuit in Fig. P8.85 is a modified version of the Wilson current mirror. Here the output transistor is “split” into two matched transistors, Q3 and Q4 . Find IO1 and IO2 in terms of IREF . Assume all transistors to be matched with current gain β. (b) Use this idea to design a circuit that generates currents of 0.1 mA, 0.2 mA, and 0.4 mA, using a reference current source of 0.7 mA. What are the actual values of the currents generated for β = 50?
*8.87 For the Wilson current mirror of Fig. 8.40, show that the incremental input resistance seen by IREF is approximately 2VT /IREF . (Neglect the Early effect in this derivation and assume a signal ground at the output.) Evaluate Rin for IREF = 0.2 mA. *8.88 Consider the Wilson MOS mirror of Fig. 8.41(a) for the case of all transistors identical, with W/L = 10, μn Cox = 2 400 μA/V , Vt n = 0.5 V, and VA = 18 V. The mirror is fed with IREF = 180 μA. (a) Obtain an estimate of VOV and VGS at which the three transistors are operating, by neglecting the Early effect. (b) Noting that Q1 and Q2 are operating at different VDS , obtain an approximate value for the difference in their currents and hence determine IO . (c) To eliminate the systematic error between IO and IREF caused by the difference in VDS between Q1 and Q2 , a diode-connected transistor Q4 can be added to the circuit
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 591
8.89 Show that the incremental input resistance (seen by IREF ) for the Wilson MOS mirror of Fig. 8.41(a) is 2/gm . Assume that all three transistors are identical and neglect the Early effect. Also, assume a signal ground at the output. (Hint: Replace all transistors by their T model and remember that Q1 is equivalent to a resistance 1/gm .) D 8.90 (a) Utilizing a reference current of 200 μA, design a Widlar current source to provide an output current of 20 μA. Assume β to be high. (b) If β = 200 and VA = 50 V, find the value of the output resistance, and find the change in output current corresponding to a 5-V change in output voltage. D 8.91 Design three Widlar current sources, each having a 100-μA reference current: one with a current transfer ratio of 0.8, one with a ratio of 0.10, and one with a ratio of 0.01, all assuming high β. For each, find the output resistance, and contrast it with ro of the basic unity-ratio source that is providing the desired current and for which RE = 0. Use β = ∞ and VA = 50 V. D 8.92 (a) For the circuit in Fig. P8.92, assume BJTs with high β and v BE = 0.7 V at 1 mA. Find the value of R that will result in IO = 10 μA. (b) For the design in (a), find Ro assuming β = 100 and VA = 40 V.
Ro 10 A
Section 8.7: Some Useful Transistor Pairings 8.94 Use the source-follower equivalent circuit in Fig. 8.45(b) to show that its output resistance is given by Ro = ro3 ro1
1 1 0005 gm + gmb gm + gmb 0002
IO
Q1
Q3
Q2
R
Figure P8.92
Figure P8.93
2
0002
8.95 A source follower for which kn = 200 μA/V , VA = 20 V/μm, χ = 0.2, L = 0.5 μm, W = 20 μm, and Vt = 0.6 V is required to provide a dc level shift (between input and output of 0.9 V.) What must the bias current be? Find gm , gmb , ro , Avo , and Ro . Assume that the bias current source has an output resistance equal to ro . Also find the voltage gain when a load resistance of 2 k0003 is connected to the output. 8.96 The transistors in the circuit of Fig. P8.96 have β = 100 and VA = 50 V.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
D 8.93 If the pnp transistor in the circuit of Fig. P8.93 is characterized by its exponential relationship with a scale current IS , show that the dc current I is determined by IR = VT ln(I/IS ). Assume Q1 and Q2 to be matched and Q3 , Q4 , and Q5 to be matched. Find the value of R that yields a current I = 200 μA. For the BJT, VEB = 0.7 V at IE = 1 mA.
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as shown in Fig. 8.41(c). What do you estimate IO now to be? (d) What is the minimum allowable voltage at the output node of the mirror? (e) Convince yourself that Q4 will have no effect on the output resistance of the mirror. Find Ro . (f) What is the change in IO (both absolute value and percentage) that results from 0002VO = 1 V?
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PROBLEMS
592 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers (a) Find Rin and the overall voltage gain. (b) What is the effect of increasing the bias currents by a factor of 10 on Rin , Gv , and the power dissipation?
00035V 200 A Rsig 0004 500 k0007
vo
Q1
8.98 The BJTs in the Darlington follower of Fig. P8.98 have β = 100. If the follower is fed with a source having a 100-k0003 resistance and is loaded with 1 k0003, find the input resistance and the output resistance (excluding the load). Also find the overall voltage gain, both open-circuited and with load. Neglect the Early effect.
Q2
vsig 0003 0002
(d) Noting that RG is connected between the input node where the voltage is v i and the output node where the voltage is Av v i , find Rin and hence the overall voltage gain v o /v sig . (e) To considerably reduce the effect of RG on Rin and hence on Gv , consider the effect of adding another 10 -M0003 resistor in series with the existing one and placing a large bypass capacitor between their joint node and ground. What will Rin and Gv become?
200 A Rin
Figure P8.96
D *8.97 Consider the BiCMOS amplifier shown in Fig. P8.97. The BJT has VBE = 0.7 V and β = 200. The 2 MOSFET has Vt = 1 V and kn = 2 mA/V . Neglect the Early effect in both devices. 00035 V
RG 0004 10 M0007 500 k0007 C1
∞
vi
Q1
∞ Vsig 0003 0002
3 k0007 C2
vo 1 k0007
Q2
Figure P8.98
6.8 k0007 Rin
Figure P8.97
(a) Consider the dc bias circuit. Neglect the base current in Q2 in determining the current in Q1 . Find the dc bias currents in Q1 and Q2 and show that they are approximately 100 μA and 1 mA, respectively. (b) Evaluate the small-signal parameters of Q1 and Q2 at their bias points. (c) Determine the voltage gain Av = v o /v i . For this purpose you can neglect RG .
8.99 For the amplifier in Fig. 8.48(a), let I = 0.5 mA and β = 100, and neglect ro . Assume that a load resistance of 10 k0003 is connected to the output terminal. If the amplifier is fed with a signal v sig having a source resistance Rsig = 10 k0003, find Gv . 8.100 Consider the CD–CG amplifier of Fig. 8.48(c) for the case gm = 5 mA/V, Rsig = 500 k0003, and RL = 10 k0003. Neglecting ro , find Gv . **8.101 In each of the six circuits in Fig. P8.101, let β = 100, and neglect ro . Calculate the overall voltage gain.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 593
vo
vo
vsig
(a)
PROBLEMS
vsig
vsig
(c)
(b)
vo vo vsig vo
vsig
vsig
(d)
Figure P8.101
(e)
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vo
(f )
PROBLEMS Computer Simulation Problems Problems identified by the Multisim/PSpice icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion. Instructions to assist in setting up PSpice and Multisim simulations for all the indicated problems can be found in the corresponding files on the website. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
Section 9.1: The MOS Differential Pair 9.1 For an NMOS differential pair with a common-mode voltageVCM applied,asshowninFig. 9.2,letVDD = VSS = 1.0 V, 0002 2 kn = 0.4 mA/V , (W/L)1,2 = 10, Vt n = 0.4 V, I = 0.16 mA, RD = 5 k0002, and neglect channel-length modulation. (a) (b) (c) (d) (e)
Find VOV and VGS for each transistor. For VCM = 0, find VS , ID1 , ID 2 , VD1 , and VD2 . Repeat (b) for VCM = +0.4 V. Repeat (b) for VCM = −0.1 V. What is the highest value of VCM for which Q1 and Q2 remain in saturation? (f) If current source I requires a minimum voltage of 0.2 V to operate properly, what is the lowest value allowed for VS and hence for VCM ?
9.2 For the PMOS differential amplifier shown in 0002 2 Fig. P9.2 let Vtp = −0.8 V and kp W/L = 4 mA/V . Neglect channel-length modulation. 2.5 V
(a) For v G1 = v G2 = 0 V, find |VOV | and VSG for each of Q1 and Q2 . Also find VS , VD1 , and VD2 . (b) If the current source requires a minimum voltage of 0.4 V, find the input common-mode range. 9.3 For the differential amplifier specified in Problem 9.1 let v G2 = 0 and v G1 = v id . Find the value of v id that corresponds to each of the following situations: (a) iD1 = iD2 = 0.08 mA; (b) iD1 = 0.12 mA and iD2 = 0.04 mA; (c) iD1 = 0.16 mA and iD2 = 0 (Q2 just cuts off); (d) iD1 = 0.04 mA and iD2 = 0.12 mA; (e) iD1 = 0 mA (Q1 just cuts off) and iD2 = 0.16 mA. For each case, find v S , v D1 , v D2 , and (v D2 – v D1 ). 9.4 For the differential amplifier specified in Problem 9.2, let v G2 = 0 and v G1 = v id . Find the range of v id needed to steer the bias current from one side of the pair to the other. At each end of this range, give the value of the voltage at the common-source terminal and the drain voltages. 9.5 Consider the differential amplifier specified in Problem 9.1 with G2 grounded and v G1 = v id . Let v id be adjusted to the value that causes iD1 = 0.09 mA and iD2 = 0.07 mA. Find the corresponding values of v GS2 , v S , v GS1 , and hence v id . What is the difference output voltage v D2 − v D1 ? What is the voltage gain (v D2 − v D1 )/v id ? What value of v id results in iD1 = 0.07 mA and iD2 = 0.09 mA? D 9.6 Design the circuit in Fig. P9.6 to obtain a dc voltage of +0.1 V at each of the drains of Q1 and Q2 when v G1 = v G2 = 0 V. Operate all transistors at VOV = 0.15 V
VDD
0.5 mA v
RD
vG1
v
Q
0.9 V
v
Q
RD
Q2
Q1
0.9 V 0.1 mA
v
v
R 0.4 mA
4k
4k
Q4
VSS
2.5 V
Figure P9.2
Q3
0.9 V
Figure P9.6
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
vG2
Problems 675
9.8 Use Eq. (9.23) to show that if the term involving v id is to be kept to a maximum value of k then the maximum possible fractional change in the transistor current is given by 0002 0003Imax = 2 k(1 − k) I/2 and the corresponding maximum value of v id is given by √ v idmax = 2 k VOV 2
Evaluate both expressions for k = 0.01, 0.1, and 0.2. 9.9 A MOS differential amplifier biased with a current source I = 200 μA is found to switch currents completely to one side of the pair when a difference signal vid = 0.3 V is applied. At what overdrive voltage will each of Q1 and Q2 be operating when vid = 0? If vid for full current switching is to be 0.5 V, what must the bias current I be changed to? D 9.10 Design the MOS differential amplifier of Fig. 9.5 to operate at VOV = 0.25 V and to provide a transconductance gm of 1 mA/V. Specify the W/L ratios and the bias current. The technology available provides Vt = 0.5 V and 2 μn Cox = 400 μA/V . 9.11 For the MOS differential pair in Fig. 9.5, specify the value of vid ≡ vG1 − vG2 , in terms of VOV , that (a) causes iD1 to increase by 10% above its equilibrium value of I/2. (b) makes iD1 /iD2 = 1.0; 2.0; 1.1; 1.01; 20. 9.12 An NMOS differential amplifier is operated at a bias current I of 0.2 mA and has a W/L ratio of 32, 2 μn Cox = 200 μA/V , VA = 10 V, and RD = 10 k0002. Find VOV , gm , ro , and Ad . D 9.13 It is required to design an NMOS differential amplifier to operate with a differential input voltage that
D 9.14 Design a MOS differential amplifier to operate from ±1-V power supplies and dissipate no more than 1 mW in the equilibrium state. The differential voltage gain Ad is to be 10 V/V and the output common-mode dc voltage is to be 0.2 V. (Note: This is the dc voltage at the drains.) Assume 2 μn Cox = 400 μA/V and neglect the Early effect. Specify I, RD , and W/L. D 9.15 Design a MOS differential amplifier to operate from ±1-V supplies and dissipate no more than 1 mW in its equilibrium state. Select the value of VOV so that the value of v id that steers the current from one side of the pair to the other is 0.25 V. The differential voltage 0002 2 gain Ad is to be 10 V/V. Assume kn = 400 μA/V and neglect the Early effect. Specify the required values of I, RD , and W/L. 9.16 An NMOS differential amplifier employing equal drain resistors, RD = 47 k0002, has a differential gain Ad of 20 V/V. (a) What is the value of gm for each of the two transistors? (b) If each of the two transistors is operating at an overdrive voltage VOV = 0.2 V, what must the value of I be? (c) For v id = 0, what is the dc voltage across each RD ? (d) If v id is 20-mV peak-to-peak sine wave applied in a balanced manner but superimposed on VCM = 0.5 V, what is the peak of the sine-wave signal at each drain? (e) What is the lowest value that VDD must have to ensure saturation-mode operation for Q1 and Q2 at all times? Assume Vt = 0.5 V. 9.17 A MOS differential amplifier is designed to have a differential gain Ad equal to the voltage gain obtained from a common-source amplifier. Both amplifiers utilize the same values of RD and supply voltages, and all the transistors have the same W/L ratios. What must the bias current I of the differential pair be relative to the bias current ID of the CS amplifier? What is the ratio of the power dissipation of the two circuits?
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
9.7 The table providing the answers to Exercise 9.3 shows that as the maximum input signal to be applied to the differential pair is increased, linearity is000e maintained at the 000e same level by operating at a higher VOV . If 000ev id 000emax is to be 220 mV, use the data in the table to determine the required VOV and the corresponding values of W/L and gm .
can be as high as 0.1 V while keeping the nonlinear term under the square root in Eq. (9.23) to a maximum of 0.04. A transconductance gm of 2 mA/V is needed and the amplifier is required to provide a differential output signal of 1 V when the input is at its maximum value. Find the required values of VOV , I, RD , and W/L. Assume that the technology available 2 has μn Cox = 200 μA/V and λ = 0.
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and assume that for the process technology in which the circuit 2 is fabricated, Vtn = 0.4 V and μn Cox = 400 μA/V . Neglect channel-length modulation. Determine the values of R, RD , and the W/L ratios of Q1 , Q2 , Q3 , and Q4 . What is the input common-mode voltage range for your design?
CHAPTER 9
PROBLEMS
676 Chapter 9 Differential and Multistage Amplifiers 9.18 A differential amplifier is designed to have a differential voltage gain equal to the voltage gain of a common-source amplifier. Both amplifiers use the same values of RD and supply voltages and are designed to dissipate equal amounts of power in their equilibrium or quiescent state. As well, all the transistors use the same channel length. What must the width W of the differential-pair transistors be relative to the width of the CS transistor? D 9.19 Figure P9.19 shows a MOS differential amplifer with the drain resistors RD implemented using diode-connected PMOS transistors, Q3 and Q4 . Let Q1 and Q2 be matched, and Q3 and Q4 be matched.
Rs = 0? What is the value of Rs (in terms of 1/gm ) that reduces the gain to half this value?
VDD RD
RD vod
vid 2
vid
Q2
Q1
2
Rs
VDD
I – 2
I – 2 VSS Q4
Q3
vid
Q1
2
Q2
Figure P9.20
vid 2
*9.21 The resistance Rs in the circuit of Fig. P9.20 can be implemented by using a MOSFET operated in the triode region, as shown in Fig. P9.21. Here Q3 implements Rs , with the value of Rs determined by the voltage VC at the gate of Q3 .
VDD RD
I
RD vod
Figure P9.19
(a) Find the differential half-circuit and use it to derive an expression for Ad in terms of gm1,2 , gm3,4 , ro1,2 , and ro3,4 . (b) Neglecting the effect of the output resistances ro , find Ad in terms of μn , μp , (W/L)1,2 and (W/L)3,4 . (c) If μn = 4μp and all four transistors have the same channel length, find (W1,2 /W3,4 ) that results in Ad = 10 V/V. 9.20 Find the differential half-circuit for the differential amplifier shown in Fig. P9.20 and use it to derive an expression for the differential gain Ad ≡ v od /v id in terms of gm , RD , and Rs . Neglect the Early effect. What is the gain with
vG2
Q2
Q1
vG1
Q3
I – 2
VC
I – 2
– V SS Figure P9.21
(a) With v G1 = v G2 = 0 V, and assuming that Q1 and Q2 are operating in saturation, what dc voltages appear
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 677
D *9.23 Figure P9.23 shows a circuit for a differential amplifier with an active load. Here Q1 and Q2 form the differential pair, while the current source transistors Q4 and Q5 form the active loads for Q1 and Q2 , respectively. The dc bias circuit that establishes an appropriate dc voltage at the drains of Q1 and Q2 is not shown. It is required to design the circuit to meet the following specifications:
PROBLEMS
*9.22 The circuit of Fig. P9.22 shows an effective way of implementing the resistance Rs needed for the circuit in Fig. P9.20. Here Rs is realized as the series equivalent of two MOSFETs Q3 and Q4 that are operated in the triode region, thus, Rs = rDS3 + rDS4 . Assume that Q1 and Q2 are matched and operate in saturation at an overdrive voltage VOV that corresponds to a drain bias current of I/2. Also, assume that Q3 and Q4 are matched.
and Q4 ? At what overdrive voltages are Q3 and Q4 operating? Find an expression for rDS for each of Q3 and Q4 and hence for Rs in terms of (W/L)1,2 , (W/L)3,4 , and gm1,2 . (b) Now with v G1 = v id /2 and v G2 = − v id /2, where v id is a small signal, find an expression of the voltage gain Ad ≡ v od /v id in terms of gm1,2 , RD , (W/L)1,2 , and (W/L)3,4 .
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at the sources of Q1 and Q2 ? Express these in terms of the overdrive voltage VOV at which each of Q1 and Q2 operates, and Vt . (b) For the situation in (a), what current flows in Q3 ? What overdrive voltage VOV 3 is Q3 operating at, in terms of VC , VOV , and Vt ? (c) Now consider the case v G1 = +v id /2 and v G2 = −v id /2, where v id is a small signal. Convince yourself that Q3 now conducts current and operates in the triode region with a small v DS . What resistance rDS does it have, expressed in terms of the overdrive voltage VOV 3 at which it is operating? This is the resistance Rs . Now if all three transistors have the same W/L, express Rs in terms of VOV , VOV 3 , and gm1,2 . (d) Find VOV 3 and hence VC that result in (i) Rs = 1/gm1,2 ; (ii) Rs = 0.5/gm1,2 .
(a) (b) (c) (d)
Differential gain Ad = 50 V/V. IREF = I = 200 μA. The dc voltage at the gates of Q6 and Q3 is +0.8 V. The dc voltage at the gates of Q7 , Q4 , and Q5 is −0.8 V.
The technology available is 000especified as follows: 000e μ 000e 000e n Cox = 2 2.5 μp Cox = 250 μA/V ; Vt n = 000eVtp 000e = 0.5 V, VAn = 000eVAp 000e = 10 V. Specify the required value of R and000e the000e W/L ratios for all transistors. Also specify ID and 000eVGS 000e at which each transistor is operating. For dc bias calculations you may neglect channel-length modulation.
1.5 V
VDD RD
RD Q6
Q3
vod
I
Q1
Q2
vG2
vG1
IREF R
Q3
vid00022
Q1
vid00022
Q2
Q4 vod
I – 2
I – 2
Q4
Q7 –VSS Figure P9.22
(a) With v G1 = v G2 = 0 V, what dc voltages appear at the sources of Q1 and Q2 ? What current flows through Q3
1.5 V Figure P9.23
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Q5
CHAPTER 9
PROBLEMS
678 Chapter 9 Differential and Multistage Amplifiers *9.24 A design error has resulted in a gross mismatch in the circuit of Fig. P9.24. Specifically, Q2 has twice the W/L ratio of Q1 . If v id is a small sine-wave signal, find: (a) ID1 and ID2 . (b) VOV for each of Q1 and Q2 . (c) The differential gain Ad in terms of RD , I, and VOV .
VDD
RD
RD vod Q1
vid 2
Q2
WL
2W L
β = 100. Assume that the BJTs have v BE = 0.7 V at iC = 1 mA. Find the voltage at the emitters and at the outputs. 9.27 An npn differential amplifier with I = 0.4 mA, VCC = VEE = 2.5 V, and RC = 5 k0002 utilizes BJTs with β = 100 and v BE = 0.7 V at iC = 1 mA. If v B2 = 0, find VE , VC1 , and VC2 obtained with v B1 = +0.5 V, and with v B1 = −0.5 V. Assume that the current source requires a minimum of 0.3 V for proper operation. 9.28 An npn differential amplifier with I = 0.4 mA, VCC = VEE = 2.5 V, and RC = 5 k0002 utilizes BJTs with β = 100 and v BE = 0.7 V at iC = 1 mA. Assuming that the bias current is obtained by a simple current source and that all transistors require a minimum v CE of 0.3 V for operation in the active mode, find the input common-mode range. 9.29 Repeat Exercise 9.7 for an input of –0.3 V. 9.30 An npn differential pair employs transistors for which v BE = 690 mV at iC = 1 mA, and β = 50. The transistors leave the active mode at v CE ≤ 0.3 V. The collector resistors RC = 82 k0002, and the power supplies are ±1.2 V. The bias current I = 20 μA and is supplied with a simple current source.
vid 2
(a) For v B1 = v B2 = VCM = 0 V, find VE , VC1 , and VC2 . (b) Find the input common-mode range. (c) If v B2 = 0, find the value of v B1 that increases the current in Q1 by 10%.
I
VSS Figure P9.24
D 9.25 For the cascode differential amplifier of Fig. 9.13(a), show that if all transistors 000e have 000e 0002 and 000e the same channel0002 length 000e 000eVOV 000e and assuming that VAn 000eVAp 000e = are operated at the same = 000e 0002000e 000eVA 000e, the differential gain Ad is given by 0003000e 000e0014000e 000e00042 Ad = 2 000eVA 000e 000eVOV 000e Now design the to obtain 000e amplifier 000e 000e 0002 000e a differential gain of 500 V/V. Use 000eVOV 000e = 0.2 V. If 000eVA 000e = 5 V/μm, specify the required channel length L. If gm is to be as high as possible but the power dissipation in the amplifier (in equilibrium) is to be limited to 0.5 mW, what bias current I would you use? Let VDD = VSS = 0.9 V.
Section 9.2: The BJT Differential Pair 9.26 For the differential amplifier of Fig. 9.15(a) let I = 0.4 mA, VCC = VEE = 2.5 V, VCM = −1 V, RC = 5 k0002, and
9.31 Consider the BJT differential amplifier when fed with a common-mode voltage VCM as shown in Fig. 9.15(a). As is often the case, the supply voltage VCC may not be pure dc but might include a ripple component v r of small amplitude and a frequency of 120 Hz (see Section 4.5). Thus the supply voltage becomes VCC + v r . Find the ripple component of the collector voltages, v C1 and v C2 , as well as of the difference output voltage v od ≡ v C2 − v C1 . Comment on the differential amplifier response to this undesirable power-supply ripple. D 9.32 Consider the differential amplifier of Fig. 9.14 and let the BJT β be very large: (a) What is the largest input common-mode signal that can be applied while the BJTs remain comfortably in the active region with v CB = 0? (b) If the available power supply VCC is 2.0 V, what value of IRC should you choose in order to allow a common-mode input signal of ±1.0 V? (c) For the value of IRC found in (b), select values for I and RC . Use the largest possible value for I subject to the
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 679
D 9.34 Design the circuit of Fig. 9.14 to provide a differential output voltage (i.e., one taken between the two collectors) of 1 V when the differential input signal is 10 mV. A current source of 1 mA and a positive supply of +5 V are available. What is the largest possible input common-mode voltage for which operation is as required? Assume α 0003 1. *9.35 For the circuit in Fig. 9.14, assuming α = 1 and IRC = 5 V, use Eqs. (9.48) and (9.49) to find iC1 and iC2 , and hence determine v od = v C2 − v C1 for input differential signals v id ≡ v B1 − v B2 of 2 mV, 5 mV, 10 mV, 15 mV, 20 mV, 25 mV, 30 mV, 35 mV, and 40 mV. Plot v od versus v id , and hence comment on the amplifier linearity. As another way of 0003 0004 visualizing linearity, determine the gain v o /v id versus v id . Comment on the resulting graph. 9.36 In a differential amplifier using a 1.5-mA emitter bias current source, the two BJTs are not matched. Rather, one has twice the emitter junction area of the other. For a differential input signal of zero volts, what do the collector currents become? What difference input is needed to equalize the collector currents? Assume α = 1. 9.37 This problem explores the linearization of the transfer characteristics of the differential pair achieved by including emitter-degeneration resistances Re in the emitters (see Fig. 9.17). Consider the case I = 200 μA with the transistors exhibiting v BE = 690 mV at iC = 1 mA and assume α 0003 1. (a) With no emitter resistances Re , what value of VBE results when v id = 0? (b) With no emitter resistances Re , use the large-signal model to find iC1 and iC2 when v id = 20 mV. (c) Now find the value of Re that will result in the same iC1 and iC2 as in (b) but with v id = 200 mV. Use the large-signal model.
9.38 A BJT differential amplifier uses a 400-μA bias current. What is the value of gm of each device? If β is 160, what is the differential input resistance? D 9.39 Design the basic BJT differential amplifier circuit of Fig. 9.18 to provide a differential input resistance of at least 20 k0002 and a differential voltage gain of 100 V/V. The transistor β is specified to be at least 100. Specify I and RC . 9.40 For a differential amplifier to which a total difference signal of 10 mV is applied, what is the equivalent signal to its corresponding CE half-circuit? If the emitter current source I is 200 μA, what is re of the half-circuit? For a load resistance of 10 k0002 in each collector, what is the half-circuit gain? What magnitude of signal output voltage would you expect at each collector? Between the two collectors? 9.41 A BJT differential amplifier is biased from a 0.5-mA constant-current source and includes a 400-0002 resistor in each emitter. The collectors are connected to VCC via 10-k0002 resistors. A differential input signal of 0.1 V is applied between the two bases. (a) Find the signal current in the emitters (ie ) and the signal voltage v be for each BJT. (b) What is the total emitter current in each BJT? (c) What is the signal voltage at each collector? Assume α = 1. (d) What is the voltage gain realized when the output is taken between the two collectors? D 9.42 Design a BJT differential amplifier to amplify a differential input signal of 0.1 V and provide a differential output signal of 2 V. To ensure adequate linearity, it is required to limit the signal amplitude across each base–emitter junction to a maximum of 5 mV. Another design requirement is that the differential input resistance be at least 100 k0002. The BJTs available are specified to have β ≥ 100. Give the circuit configuration and specify the values of all its components. D 9.43 Design a bipolar differential amplifier such as that in Fig. 9.18 to operate from ±2.5 V power supplies and to provide differential gain of 60 V/V. The power dissipation in the quiescent state should not exceed 1 mW.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
9.33 To provide insight into the possibility of nonlinear distortion resulting from large differential input signals applied to the differential amplifier of Fig. 9.14, evaluate the 0003 0004 normalized change in the current iE1 , 0003 iE1 /I = iE1 − (I/2) /I, for differential input signals v id of 2, 5, 8, 10, 20, 30, 0003 0004 and 40 mV. Provide a tabulation of the ratio 0003iE1 /I /v id , which represents the proportional transconductance gain of the differential pair, versus v id . Comment on the linearity of the differential pair as an amplifier.
(d) Calculate the effective transconductance Gm as the ratio of the difference current, (iC1 − iC2 ), to vid in the cases without and with the Re ’s. By what factor is Gm reduced? How does this factor relate to the increase in v id ? Comment.
CHAPTER 9
constraint that the base current of each transistor (when I divides equally) should not exceed 2 μA. Let β = 100.
CHAPTER 9
PROBLEMS
680 Chapter 9 Differential and Multistage Amplifiers (a) Specify the values of I and RC . What dc voltage appears at the collectors? (b) If β = 100, what is the input differential resistance? (c) For v id = 10 mV, what is the signal voltage at each of the collectors? (d) For the situation in (c), what is the maximum allowable value of the input common-mode voltage, VCM ? Recall that to maintain an npn BJT in saturation, v B should not exceed v C by more than 0.4 V.
9.47 For each of the emitter-degenerated differential amplifiers shown in Fig. P9.47, find the differential half-circuit and derive expressions for the differential gain Ad and differential input resistance Rid . For each circuit, what dc voltage appears across the bias current source(s) in the quiescent state (i.e., with v id = 0)? Hence, which of the two circuits will allow a larger negative VCM ?
VCC
D *9.44 In this problem we explore the trade-off between input common-mode range and differential gain in the design of the bipolar BJT. Consider the bipolar differential amplifier in Fig. 9.14 with the input voltages 0003 0004 v B1 = VCM + v id /2 0003 0004 v B2 = VCM − v id /2 (a) Bearing in mind that for a BJT to remain in the active mode, v BC should not exceed 0.4 V, show that when v id has a peak vˆ id , the maximum input common-mode voltage VCMmax is given by 0005 0006 vˆ vˆ VCMmax = VCC + 0.4 − id − Ad VT + id 2 2
RC vod
VCM
vid
Re
vid 2
Re I VEE (a) VCC
RC
RC vod
VCM
vid
VCM
2
v B1 = 1 + 0.005 sin(ωt)
2 Re
I – 2
v B2 = 1 − 0.005 sin(ωt) 9.46 Consider a bipolar differential amplifier in which the collector resistors RC are replaced with simple current sources implemented using pnp transistors. Sketch the circuit and give its differential half-circuit. If VA = 20 V for all transistors, find the differential voltage gain achieved.
VCM
2
(b) For the case VCC = 2.5 V and vˆ id = 10 mV, use the relationship above to determine VCMmax for the case Ad = 50 V/V. Also find the peak output signal vˆ od and the required value of IRC . Now if the power dissipation in the circuit is to be limited to 1 mW in the quiescent state (i.e., with v id = 0), find I and RC . (Remember to include the power drawn from the negative power supply −VEE = −2.5 V.) (c) If VCMmax is to be +1 V, and all other conditions remain the same, what maximum gain Ad is achievable? 9.45 For the differential amplifier of Fig. 9.14, let VCC = +5 V and IRC = 4 V. Find the differential gain Ad . Sketch and clearly label the waveforms for the total collector voltages v C1 and v C2 and for (v C2 − v C1 ) for the case:
RC
I – 2 VEE (b)
Figure P9.47
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
vid 2
Problems 681
9.50 A bipolar differential amplifier with emitterdegeneration resistances Re and Re is fed with the arrangement shown in Fig. P9.50. Derive an expression for the overall differential voltage gain Gv ≡ v od /v sig . If Rsig is of such a value that v id = 0.5v sig , find the gain Gv in terms of RC , re , Re , and α. Now if β is doubled, by what factor does Gv increase?
Rsig 2
5V 25 k vo vi
Q2
Q1
250 Rin
250 0.2 mA
Figure P9.52
9.53 Find the voltage gain and input resistance of the amplifier in Fig. P9.53 assuming that β = 100.
vsig – 2
5V
vid
25 k
VCM
vo vsig – 2
vi 500 Rin
0.1 mA
0.1 mA
Rsig 2 Figure P9.50
Figure P9.53
9.51 A particular differential amplifier operates from an emitter current source I = 0.4 mA. Each of the collector resistances RC = 20 k0002 and a load resistance RL = 40 k0002 is connected between the two collectors. If the amplifier is fed in the manner shown in Fig. P9.50 with Rsig = 100 k0002, find the overall voltage gain. Let β = 100.
9.54 Derive an expression for the small-signal voltage gain v o /v i of the circuit shown in Fig. P9.54 in two different ways: (a) as a differential amplifier (b) as a cascade of a common-collector stage Q1 and a common-base stage Q2
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
9.49 A bipolar differential amplifier having resistance Re inserted in series with each emitter (as in Fig. P9.47(a)) is biased with a constant current I. When both input terminals are grounded, the dc voltage measured across each Re is found to be 4 VT and that measured across each RC is found to be 60 VT . What differential voltage gain Ad do you expect the amplifier to have?
9.52 Find the voltage gain and the input resistance of the amplifier shown in Fig. P9.52 assuming β = 100.
CHAPTER 9
9.48 Consider a bipolar differential amplifier that, in addition to the collector resistances RC , has a load resistance RL connected between the two collectors. What does the differential gain Ad become?
PROBLEMS
682 Chapter 9 Differential and Multistage Amplifiers (e) Use the common-mode gain found in (d) to determine the change in VCM that results in Q1 and Q2 entering the triode region.
CHAPTER 9
VDD
5V
RD
RD vod Q1
Figure P9.54
Assume that the BJTs are matched and have a current gain α, and neglect the Early effect. Verify that both approaches lead to the same result.
Q2
vid
VCM
1 mA
RSS
1k
Section 9.3: Common-Mode Rejection 9.55 An NMOS differential pair is biased by a current source I = 0.2 mA having an output resistance RSS = 100 k0002. The amplifier has drain resistances RD = 10 k0002, 0002 2 using transistors with kn W/L = 3 mA/V , and ro that is large. If the output is taken differentially and there 000e 000eis 000ea 1% 000e mismatch between the drain resistances, find 000eAd 000e, 000eAcm 000e, and CMRR. 9.56 For the differential amplifier shown in Fig. P9.2, let Q1 0002 2 and Q2 have kp (W/L) = 4 mA/V , and assume that the000e bias000e 000e 000e current 000e 000e source 000e 000e has an output resistance of 30 k0002. Find VOV , 000e 000e 000e 000e gm , Ad , Acm , and the CMRR (in dB) obtained with the output taken differentially. The drain resistances are known to have a mismatch of 2%. D *9.57 The differential amplifier in Fig. P9.57 utilizes a resistor RSS to establish a 1-mA dc bias current. Note that this amplifier uses a single 5-V supply and thus the dc common-mode voltage VCM cannot be zero. Transistors Q1 0002 2 and Q2 have kn W/L = 2.5 mA/V , Vt = 0.7 V, and λ = 0. (a) Find the required value of VCM . (b) Find the value of RD that results in a differential gain Ad of 8 V/V. (c) Determine the dc voltage at the drains. (d) Determine the single-ended-output common-mode gain 0003VD1 /0003V CM . (Hint: You need to take 1/gm into account.)
Figure P9.57
9.58 It can be shown that if the drain resistors of a MOS differential amplifier have a mismatch 0003RD and if simultaneously the transconductances of Q1 and Q2 have a mismatch 0003gm , the common-mode gain is given by 0005 Acm 0003
RD 2RSS
00060005
0003gm 0003RD + gm RD
0006
Note that this equation indicates that RD can be deliberately varied to compensate for the initial variability in gm and RD , that is, to minimize Acm . In a MOS differential amplifier for which RD = 5 k0002 and RSS = 25 k0002, the common-mode gain is measured and found to be 0.002 V/V. Find the percentage change required in one of the two drain resistors so as to reduce Acm to zero (or close to zero). D 9.59 It is required to design a MOS differential amplifier to have a CMRR of 80 dB. The only source of mismatch in the circuit is a 2% difference between the W/L ratios of the two transistors. Let I = 100 μA and assume that all transistors are operated at VOV = 0.2 V. For the 0.18-μm CMOS fabrication 0002 process available, VA = 5 V/μm. What is the value of L required for the current-source transistor?
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 683 input resistance. For these transistors, β = 100 and VA = 100 V.
10 V RC 10 k
vod
RC 10 k
PROBLEMS
RL 20 k Q1
9.61 The differential amplifier circuit of Fig. P9.61 utilizes a resistor connected to the negative power supply to establish the bias current I. (a) For v B1 = v id /2 and v B2 = −v id /2, where v id is a small signal with zero000e average, 000e find the magnitude of the differential gain, 000ev o /v id 000e. (b) For v B1 = v B2 = v icm , where v icm has a zero000eaverage, 000e find the magnitude of the common-mode gain, 000ev o /v icm 000e. (c) Calculate the CMRR. (d) If v B1 = 0.1 sin 2π × 60t + 0.005 sin 2π × 1000t, volts, and v B2 = 0.1 sin 2π × 60t − 0.005 sin 2π × 1000t, volts, find v o .
Q2 RE 300
200 k
0.5 mA
0.5 mA
200 k
Figure P9.62
9.63 Consider the basic differential circuit in which the transistors have β = 100 and VA = 100 V, with I = 0.2 mA, REE = 500 k0002, and RC = 25 k0002. The collector resistances are matched to within 1%. Find: (a) (b) (c) (d) (e)
the differential gain the differential input resistance the common-mode gain the common-mode rejection ratio the common-mode input resistance
9.64 In a bipolar differential-amplifier circuit, the bias current generator consists of a simple common-emitter transistor operating at 200 μA. For this transistor, and those used in the differential pair, VA = 20 V and β = 50. What common-mode input resistance would result? Assume RC ro . 9.65 A bipolar differential amplifier with I = 0.5 mA utilizes transistors for which VA = 50 V and β = 100. The collector resistances RC = 5 k0002 and are matched to within 10%. Find:
Figure P9.61
9.62 For the differential amplifier shown in Fig. P9.62, identify and sketch the differential half-circuit and the common-mode half-circuit. Find the differential gain, the differential input resistance, the common-mode gain assuming the resistances RC have 1% tolerance, and the common-mode
(a) the differential gain (b) the common-mode gain and the CMRR if the bias current I is generated using a simple current mirror (c) the common-mode gain and the CMRR if the bias current I is generated using a Wilson mirror. (Refer to Eq. 8.95 for Ro of the Wilson mirror.) D 9.66 It is required to design a differential amplifier to provide the largest possible signal to a pair of 10-k0002 load
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 9
D 9.60 A MOS differential amplifier utilizing a simple current source to provide the bias current I is found to have a CMRR of 60 dB. If it is required to raise the CMRR to 100 dB by adding a cascode transistor to the current source, what must the intrinsic gain A0 of the cascode transistor be? If the cascode transistor is operated at VOV = 0.2 V, what must its VA be? If for the specific technology utilized 0002 VA = 5 V/μm, specify the channel length L of the cascode transistor.
CHAPTER 9
PROBLEMS
684 Chapter 9 Differential and Multistage Amplifiers resistances. The input differential signal is a sinusoid of 5-mV peak amplitude, which is applied to one input terminal while the other input terminal is grounded. The power supply VCC available is 5 V. To determine the required bias current I, derive an expression for the total voltage at each of the collectors in terms of VCC and I in the presence of the input signal. Then impose the condition that both transistors remain well out of saturation with a minimum v CB of approximately 0 V. Thus determine the required value of I. For this design, what differential gain is achieved? What is the amplitude of the signal voltage obtained between the two collectors? Assume α 00031. D *9.67 Design a BJT differential amplifier that provides two single-ended outputs (at the collectors). The amplifier is to have a differential gain (to each of the two outputs) of at least 100 V/V, a differential input resistance ≥ 10 k0002, and a common-mode gain (to each of the two outputs) no greater than 0.1 V/V. Use a 2-mA current source for biasing. Give the complete circuit with component values and suitable power supplies that allow for ±2 V swing at each collector. Specify the minimum value that the output resistance of the bias current source must have. If the current source is realized by a simple mirror, what must the minimum value of VA be? The BJTs available have β ≥ 100. What is the value of the input common-mode resistance when the bias source has the lowest acceptable output resistance? 9.68 When the output of a BJT differential amplifier is taken differentially, its CMRR is found to be 34 dB higher than when the output is taken single-endedly. If the only source of common-mode gain when the output is taken differentially is the mismatch in collector resistances, what must this mismatch be (in percent)? *9.69 In a particular BJT differential amplifier, a production error results in one of the transistors having an emitter– base junction area that is twice that of the other. With the inputs grounded, how will the emitter bias current split between the two transistors? If the output resistance of the current source is 500 k0002 and the resistance in each collector (RC ) is 12 k0002, find the common-mode gain obtained when the output is taken differentially. Assume α 0003 1. [Hint: The CM signal current vicm /REE will split between Q1 and Q2 in the same ratio as the bias current I does.]
0002
2
pair, kn W/L = 4 mA/V . A decision is to be made concerning the bias current I to be used, whether 160 μA or 360 μA. Contrast the differential gain and input offset voltage for the two possibilities. D 9.71 An NMOS differential amplifier for which the MOSFETs have a transconductance parameter kn and whose drain resistances RD have a mismatch RD is biased with a current I. (a) Find expressions for Ad and VOS in terms of kn , RD , RD /RD , and I. Use these expressions to relate VOS and Ad . 2 (b) If kn = 4 mA/V , RD = 10 k0002, and RD /RD = 0.02, find the maximum gain realized if VOS is to be limited to 1 mV, 2 mV, 3 mV, 4 mV, and 5 mV. For each case, give the value of the required bias current I. Note the trade-off between gain and offset voltage. D 9.72 An NMOS amplifier, whose designed operating point is at VOV = 0.3 V, is suspected to have a variability of Vt of ±5 mV, and of W/L and RD (independently) of ±1%. What is the worst-case input offset voltage you would expect to find? What is the major contribution to this total offset? If you used a variation of one of the drain resistors to reduce the output offset to zero and thereby compensate for the uncertainties (including that of the other RD ), what percentage change from nominal would you require? 9.73 An NMOS differential pair operating at a bias current 0002 2 I of 100 μA uses transistors for which kn = 200 μA/V and W/L = 10. Find the three components of input offset voltage under the conditions that 0003RD /RD = 4%, 0003(W/L)/(W/L) = 4%, and 0003Vt = 5 mV. In the worst case, what might the total offset be? For the usual case of the three effects being independent, what is the offset likely to be? 9.74 A bipolar differential amplifier uses two well-matched transistors, but collector load resistors that are mismatched by 10%. What input offset voltage is required to reduce the differential output voltage to zero? 9.75 A bipolar differential amplifier uses two transistors whose scale currents IS differ by 10%. If the two collector resistors are well matched, find the resulting input offset voltage.
Section 9.4: DC Offset
9.76 Modify Eq. (9.114) for the case of a differential amplifier having a resistance RE connected in the emitter of each transistor. Let the bias current source be I.
D 9.70 An NMOS differential pair is to be used in an amplifier whose drain resistors are 10 k0002 ± 1%. For the
9.77 A differential amplifier uses two transistors whose β values are β 1 and β 2 . If everything else is matched, show that
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 685
*9.79 A differential amplifier uses two transistors having VA values of 100 V and 200 V. If everything else is matched, find the resulting input offset voltage. Assume that the two transistors are intended to be biased at a VCE of about 10 V. *9.80 A differential amplifier is fed in a balanced or push–pull manner, and the source resistance in series with each base is Rs . Show that a mismatch 0003Rs between the values of the two source resistances gives rise to an input offset voltage of approximately (I/2β)0003Rs / [1 + (gm Rs )/β]. 9.81 One approach to “offset correction” involves the adjustment of the values of RC1 and RC2 so as to reduce the differential output voltage to zero when both input terminals are grounded. This offset-nulling process can be accomplished by utilizing a potentiometer in the collector circuit, as shown in Fig. P9.81. We wish to find the
VCC (x)
(1
x)
1k
RC1 5k
RC2 5k
(a) RC1 being 4% higher than nominal and RC2 4% lower than nominal (b) Q1 having an area 5% larger than nominal, while Q2 has area 5% smaller than nominal. 9.82 A differential amplifier for which the total emitter bias current is 400 μA uses transistors for which β is specified to lie between 80 and 200. What is the largest possible input bias current? The smallest possible input bias current? The largest possible input offset current? **9.83 In a particular BJT differential amplifier, a production error results in one of the transistors having an emitter–base junction area twice that of the other. With both inputs grounded, find the current in each of the two transistors and hence the dc offset voltage at the output, assuming that the collector resistances are equal. Use small-signal analysis to find the input voltage that would restore current balance to the differential pair. Repeat using large-signal analysis and compare results. D 9.84 A large fraction of mass-produced differentialamplifier modules employing 20-k0002 collector resistors is found to have an input offset voltage ranging from +2 mV to –2 mV. By what amount must one collector resistor be adjusted to reduce the input offset to zero? If an adjustment mechanism is devised that raises one collector resistance while correspondingly lowering the other, what resistance change is needed? If a potentiometer connected as shown in Fig. P9.81 is used, what value of potentiometer resistance (specified to 1 significant digit) is needed? Assume that the offset is entirely due to the finite tolerance of RC .
Section 9.5: The Differential Amplifier with a Current-Mirror Load Q1
Q2
1 mA
Figure P9.81
9.85 The differential amplifier of Fig. 9.32(a) is measured and found to have a short-circuit transconductance of 2 mA/V. A differential input signal is applied and the output voltage is measured with a load resistance RL connected. It is found that when RL is reduced from ∞ to 20 k0002, the magnitude of the output signal is reduced by half. What do you estimate Ro and Ad (with RL disconnected) to be? 9.86 A current-mirror-loaded NMOS differential amplifier is 0002 fabricated in a technology for which |VA | = 5 V/μm. All the
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
9.78 Two possible differential amplifier designs are considered, one using BJTs and the other MOSFETs. In both cases, the collector (drain) resistors are maintained within ±2% of nominal value. The MOSFETs are operated at VOV = 200 mV. What input offset voltage results in each case? What does the MOS VOS become if the devices are increased in width by a factor of 4 while the bias current is kept constant?
potentiometer setting, represented by the fraction x of its value connected in series with RC1 , that is required for nulling the output offset voltage that results from:
CHAPTER 9
00150003 0004 0003 00040016 the input offset voltage is approximately VT 1/β1 − 1/β2 . Evaluate VOS for β 1 = 50 and β 2 = 100.
CHAPTER 9
PROBLEMS
686 Chapter 9 Differential and Multistage Amplifiers transistors have L = 0.5 μm. If the differential-pair transistors are operated at VOV = 0.25 V, what open-circuit differential gain is realized? 9.87 The differential amplifier of Fig. 9.32(a) is biased with I = 200 μA. All transistors have L = 0.5 μm, and Q1 and Q2 have W/L = 50. The circuit is fabricated in a process for 2 0002 which μn Cox = 200 μA/V and |VA | = 5 V/μm. Find gm1,2 , ro2 , ro4 , and Ad . D 9.88 In a current-mirror-loaded differential amplifier of the form shown in Fig. 9.32(a), all are character000e transistors 000e 0002 2 ized by k W/L = 4 mA/V , and 000eVA 000e = 5 V. Find the bias current I for which the gain v o /v id = 20 V/V. D 9.89 Consider a current-mirror-loaded differential amplifier such as that shown in Fig. 9.32(a) with the bias current source implemented with the modified Wilson000e mirror of 000e Fig. P9.89 with I = 200 μA. The transistors have 000eVt 000e = 0.5V 0002 2 and k W/L = 5 mA/V . What is the lowest value of the total power000e supply 000e 000e(VDD000e + VSS ) that allows each transistor to operate with 000eVDS 000e ≥ 000eVGS 000e? *9.90 (a) Sketch the circuit of a current-mirror-loaded MOS differential amplifier in which the input transistors are cascoded and a cascode current mirror is used for the load.
I
I
(b) Show that if all transistors are operated 000eat 000ean overdrive voltage VOV and have equal Early voltages 000eVA 000e, the gain is given by 0003 00042 Ad = 2 VA /VOV Evaluate the gain for VOV = 0.20 V and VA = 10 V. 9.91 Figure P9.91 shows the current-mirror-loaded MOS differential amplifier prepared for small-signal analysis. We have “pulled out” ro of each transistor; thus, the current in the drain of each transistor will be gm vgs . To help the reader, we have already indicated approximate values for some of the node voltages. For instance, the output voltage v o = 0003 0004 1 gm ro v id , which we have derived in the text. The voltage 2 at the common sources has been found to be approximately +v id /4, which is very far from the virtual ground one might assume. Also, the voltage at the gate of the mirror is approximately −v id /4, confirming our contention that the voltage there is vastly different from the output voltage, hence the lack of balance in the circuit and the unavailability of a differential half-circuit. Find the currents labeled i1 to i13 in terms of (gm vid ). Determine their values in the sequence of their numbering and assume gm ro 1. Note that 000e all 000e transistors are assumed to be operating at the same 000eVOV 000e. Write the current values on the circuit diagram and reflect on the results.
vid 4
vg3
ro
Q3
ro
Q4
RSS i13
Q8
i2
i12
vo
Q7
i11
Q6
i8
ro
ro i10
Q2
i7 vs
Figure P9.89
i4
i6 Q1
(vid 2)
1 (g r ) v 2 m o id
i3
i9
Q5
i1
vid 4
Figure P9.91
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
(vid 2) i5
Problems 687
0003
VOS1 = VOV /2
0004 0003(W/L)A
9.98 Figure P9.98 shows a differential cascode amplifier with an active load formed by a Wilson current mirror. Utilizing the expressions derived in Chapter 8 for the output resistance of a bipolar cascode and the output resistance of the Wilson mirror, and assuming all transistors to be identical, show that the differential voltage gain Ad is given approximately by 1 Ad = βgm ro 3 Evaluate Ad for the case of β = 100 and VA = 20 V.
(W/L)A
VCC
where VOV is the overdrive voltage at which Q1 and Q2 are operating. (b) Repeat for a mismatch 0003(W/L)M in the W/L ratios of the mirror transistor Q3 and Q4 to show that the corresponding VOS is given by 0003
VOS2 = VOV /2
5
Q5
0004 0003(W/L)M
Q6
(W/L)M
where VOV is the overdrive voltage at which Q1 and Q2 are operating. (c) 000e For 000e a circuit in which all transistors are operated at 000eVOV 000e = 0.2 V and all W/L ratios are accurate to within ±1% of nominal, find the worst-case total offset voltage VOS .
Q7 vo
9.94 The differential amplifier in Fig. 9.36(a) is operated with I = 500 μA, with devices for which VA = 10 V and β = 100. What differential input resistance, output resistance, short-circuit transconductance, and open-circuit voltage gain would you expect? What will the voltage gain be if the input resistance of the subsequent stage is equal to Rid of this stage? 9.95 A bipolar differential amplifier having a simple pnp current-mirror load is found to have an input offset voltage of 2 mV. If the offset is attributable entirely to the finite β of the pnp transistors, what must βP be? 9.96 For the current-mirror-loaded bipolar differential pair, replacing the simple current-mirror load by the base-current-compensated mirror of Fig. 8.11, find the expected systematic input offset voltage. Evaluate VOS for βP = 50.
Q3
Q4 VBIAS Q2
Q1 vd
I
VEE
5V
Figure P9.98
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
9.93 This problem investigates the effect of transistor mismatches on the input offset voltage of the current-mirror-loaded MOS differential amplifier of Fig. 9.32(a). For this purpose, ground both input terminals and short-circuit the output node to ground. (a) If the amplifying transistors Q1 and Q2 exhibit a W/L mismatch of 0003(W/L)A , find the resulting short-circuit output current and hence show that the corresponding VOS is given by
9.97 For the current-mirror-loaded bipolar differential pair, replacing the simple current-mirror load by the Wilson mirror of Fig. 8.40(a), find the expected systematic input offset voltage. Evaluate VOS for βP , = 50.
CHAPTER 9
9.92 A current-mirror-loaded NMOS differential amplifier operates with a bias current I of 200 μA. The NMOS transistors 000e 000e are operated at VOV = 0.2 V and the PMOS devices at 000eVOV 000e = 0.3 V. The Early voltages are 20 V for the NMOS and 12 V for the PMOS transistors. Find Gm , Ro , and Ad . For what value of load resistance is the gain reduced by a factor of 2?
CHAPTER 9
PROBLEMS
688 Chapter 9 Differential and Multistage Amplifiers D 9.99 Consider the bias design of the Wilson-loaded cascode differential amplifier shown in Fig. P9.98. (a) What is the largest signal voltage possible at the output without Q7 saturating? Assume that the CB junction conducts when the voltage across it exceeds 0.4 V. (b) What should the dc bias voltage established at the output (by an arrangement not shown) be in order to allow for positive output signal swing of 1.5 V? (c) What should the value of VBIAS be in order to allow for a negative output signal swing of 1.5 V? (d) What is the upper limit on the input common-mode voltage v CM ? **9.100 Figure P9.100 shows a modified cascode differential amplifier. Here Q3 and Q4 are the cascode transistors. However, the manner in which Q3 is connected with its base current feeding the current mirror Q7 –Q8 results in very interesting input properties. Note that for simplicity the circuit is shown with the base of Q2 grounded. Assume that all transistors have equal β’s.
(b) With v I = 0 V (dc) + v id , find the input signal current ii and hence the input differential resistance Rid . Compare with the case without the Q7 –Q8 connection. By what factor does Rid increase? 9.101 For the folded-cascode differential amplifier of Fig. 9.38, find the value of VBIAS that results in the largest possible positive output swing, while keeping Q3 , Q4 , and the pnp transistors that realize the current sources out of saturation. Assume VCC = VEE = 5 V. If the dc level at the output is 0 V, find the maximum allowable output signal swing. For I = 0.5 mA, β P = 50, β N = 100, and VA = 100 V find Gm , Ro4 , Ro5 , Ro , and Ad . 9.102 For the BiCMOS differential amplifier in Fig. P9.102 000e 000e 0002 2 000e 000e let VDD = VSS = 3 V, I = 0.2 mA, k000ep W/L 000e = 6.4 mA/V ; VA for p-channel MOSFETs is 10 V, 000eVA 000e for npn transistors is 30 V. Find Gm , Ro , and Ad . V
I V
Q
Q v
Q
Q
Q
Q
Q
Q
v Q Q
0003V Q
v
Q
I
I
0003V
Figure P9.100
(a) With v I = 0 V dc, find the input bias current IB assuming all transistors have equal value of β. Compare with the case without the Q7 –Q8 connection.
Figure P9.102
D 9.103 It is required to design the current-mirrorloaded differential MOS amplifier of Fig. 9.32 to obtain a differential gain of 50 V/V. The technology available provides 000e 000e 000e 0002000e 2 μn Cox = 4μp Cox = 400 μA/V , 000eVt 000e = 0.5 V, and 000eVA 000e = 20 V/μm and operates from ±1 V supplies. 000e Use 000e a bias current I = 200 μA and operate all devices at 000eVOV 000e = 0.2 V. (a) Find the W/L ratios of the four transistors. (b) Specify the channel length required of all transistors. (c) If VICM = 0, what is the allowable range of v O ?
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 689
9.104 Consider the current-mirror-loaded MOS differential amplifier of Fig. 9.32(a) in two cases:
where VOV is the overdrive voltage that corresponds to a 0002 2 000edrain 000e current of I/2. For k W/L = 4 mA/ V , I = 160 μA, and 000eVA 000e = 5 V, find CMRR for both cases.
I
I
9.106 A current-mirror-loaded MOS differential amplifier is found to have a differential voltage gain Ad of 30 V/V. Its bias current source has an output resistance RSS = 45 k0002. The current mirror utilized has a current gain Am of 0.98 A/A and an output resistance Rom of 45 k0002. If the common-mode output resistances of the amplifier, Ro1 and Ro2 , are very large, find Acm and CMRR. 9.107 A current-mirror-loaded MOS differential amplifier is found to have a differential voltage gain Ad of 50 V/V and a CMRR of 60 dB. If the output resistance of the bias current source is 20 k0002 and the output resistance of the current-mirror load is 20 k0002, what is the expected magnitude of the deviation from unity of the current gain of the load mirror? D *9.108 Design the circuit of Fig. 9.36(a) using a basic current mirror to implement the current source I. It is required that the short-circuit transconductance be 5 mA/V. Use ±5-V power supplies and BJTs that have β = 100 and VA = 100 V. Give the complete circuit with component values and specify the differential input resistance Rid , the output resistance Ro , the open-circuit voltage gain Ad , the input bias current, the input common-mode range, the common-mode gain, and the CMRR.
RSS Q8
Q7
Q5
Q6
Figure P9.104
D *9.109 Repeat the design of the amplifier specified in Problem 9.108 utilizing a Widlar current source (Fig. 8.42) to supply the bias current. Assume that the largest resistance available is 2 k0002. 9.110 A bipolar differential amplifier such as that shown in Fig. 9.36(a) has I = 0.4 mA, VA = 40 V, and β = 150. Find Gm , Ro , Ad , and Rid . If the bias current source is implemented with a simple npn current mirror, find REE , Acm , and CMRR. If the amplifier is fed differentially with a source having a total of 30 k0002 resistance (i.e., 15 k0002 in series with the base lead of each of Q1 and Q2 ), find the overall differential voltage gain.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
(a) Current source I is implemented with a simple current mirror. (b) Current source I is implemented with the modified Wilson current mirror shown in Fig. P9.104. 000e Recalling that for the simple mirror RSS = ro 000eQ and for S the Wilson mirror RSS 0003 g000em7 r000eo7 ro5 , and assuming that all 0002 transistors have the same 000eVA 000e and k W/L, show that for case (a) 0005 00062 VA CMRR = 2 VOV and for case (b) 0005 00063 √ VA CMRR = 2 2 VOV
9.105 The MOS differential amplifier of Fig. 9.32(a) is biased with a simple current mirror delivering I = 200 μA. All transistors are operated at VOV = 0.2 V and have VA = 5 V. Find Gm , Ro , Ad , RSS , Gmcm , Rim , Am , Rom , Ro2 , Acm , and CMRR.
CHAPTER 9
(d) If I is delivered by a simple NMOS current source operated at the same VOV and having the same channel length as the other four transistors, determine the CMRR obtained.
PROBLEMS
9.111 For the current-mirror-loaded differential pair in Fig. P9.111, find:
CHAPTER 9
690 Chapter 9 Differential and Multistage Amplifiers
Assume β = 100, |VBE | = 0.7 V, and |VA | = 60 V.
Assume β = 100, |VBE | = 0.7 V, |VA | = 60 V, Vt = 0.7 V, and 0002 2 k (W/L) = 2 mA/V .
(a) differential input resistance, Rid (b) Ad (c) CMRR
+5V
Q3
+9V
Q4 vo
Q1 Q3
Q4
Q2
+ 15 V
vid
R = 144 k0004
vo Q1
Q2 +9V
vid
6.65 k0004
Q5
Q7
Q8
Q6
Q5
Q6 –5V Figure P9.112
–5V Figure P9.111
9.112 For the current-mirror-loaded differential amplifier in Fig. P9.112, find: (a) differential input resistance, Rid (b) Ad (c) CMRR
Section 9.6: Multistage Amplifiers 9.113 Consider the circuit in Fig. 9.40 with the device geometries (in000e μm) shown in Table P9.113. 000e Let IREF = 225 μA, 000eVt 000e = 0.75 V for 000e all devices, 2 2 000e μn Cox = 180 μA/V , μp Cox = 60 μA/V , 000eVA 000e = 9 V for all devices, VDD = VSS = 1.5 V. Determine the width of Q6 , W, that will ensure that the op amp will not have a000e systematic 000e 000e 000e offset voltage. Then, for all devices evaluate ID , 000eVOV 000e, 000eVGS 000e, gm , and ro . Provide your results in a table similar to Table 9.1. Also find A1 , A2 , the open-loop voltage gain, the input
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 691
Transistor
Q1
W/L
30/0.5
Q2
Q3
Q4
Q5
Q6
Q7
Q8
30/0.5
10/0.5
10/0.5
60/0.5
W /0.5
60/0.5
60/0.5
(d) With v A = v id /2 and v B = −v id /2, find the voltage gain v o /v id . Assume an Early voltage of 6 V.
D 9.114 The two-stage CMOS op amp in Fig. P9.114 is 0002 0002 fabricated in a 0.18-μm technology having kn = 4kp = 2 400 μA/V , Vtn = −Vtp = 0.4 V.
D *9.115 In a particular design of the CMOS op amp of Fig. 9.40 the designer wishes to investigate the effects of increasing the W/L ratio of both Q1 and Q2 by a factor of 4. Assuming that all other parameters are kept unchanged, refer to Example 9.6 to help you answer the following questions: 000e 000e (a) Find the resulting change in 000eVOV 000e and in gm of Q1 and Q2 . (b) What change results in the voltage gain of the input stage? In the overall voltage gain? (c) What is the effect on the input offset voltages? (You might wish to refer to Section 9.4).
(a) With A and B grounded, perform a dc design that will result in each of Q1 , Q2 , Q3 , and Q4 conducting a drain current of 100 μA and each of Q6 and Q7 a current of 200 μA. Design so that all transistors operate at 0.2-V overdrive voltages. Specify the W/L ratio required for each MOSFET. Present your results in tabular form. What is the dc voltage at the output (ideally)? (b) Find the input common-mode range. (c) Find the allowable range of the output voltage.
VDD
IREF
0.9 V
Q3 200 A
Q4 Q6
A
Q2
Q1
Q5
Q8
VSS
vo
B
Q7
0.9 V
Figure P9.114
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
common-mode range, and the output voltage range. Neglect the effect of VA on the bias currents.
CHAPTER 9
Table P9.113
CHAPTER 9
PROBLEMS
692 Chapter 9 Differential and Multistage Amplifiers 9.116 Consider the amplifier of Fig. 9.40, whose parameters are specified in Example 9.6. If a manufacturing error results in the W/L ratio of Q7 being 48/0.8, find the current that Q7 will now conduct. Thus find the systematic offset voltage that will appear at the output. (Use the results of Example 9.6.) Assuming that the open-loop gain will remain approximately unchanged from the value found in Example 9.6, find the corresponding value of input offset voltage, VOS . 9.117 Consider the input stage of the CMOS op amp in Fig. 9.40 with both inputs grounded. Assume that the two sides of the input stage are perfectly matched except that the threshold voltages of Q3 and Q4 have a mismatch 0003Vt . Show that a current gm3 0003Vt appears at the output of the first stage. What is the corresponding input offset voltage? 9.118 The two-stage op amp in Figure P9.114 is fabricated 0002 0002 2 in a 65-nm technology having kn = 5.4 × kp = 540 μA/V and Vt n = −Vtp = 0.35 V. The amplifier is operated with VDD = +1.2 V and VSS = 0 V.
(a) With A and B at a dc voltage of VDD /2, perform a dc design that will result in each of Q1 , Q2 , Q3 , and Q4 conducting a drain current of 200 μA and each of Q6 and Q7 conducting a current of 400 μA. Design so that all transistors operate at 0.15-V overdrive voltages. Specify the W/L ratio required for each MOSFET. Present all results in a table. (b) Find the input common-mode range. (c) Find the allowable range of the output voltage. (d) With vA = vid /2 and vB = −vid /2, find the voltage gain vo /vid . Assume an Early voltage of 1.8 V. *9.119 Figure P9.119 shows a bipolar op-amp circuit that resembles the CMOS op amp of Fig. 9.40. Here, the input differential pair Q1 –Q2 is loaded in a current mirror formed by Q3 and Q4 . The second stage is formed by the current-source-loaded common-emitter transistor Q5 . Unlike the CMOS circuit, here there is an output stage formed by the emitter follower Q6 . The function of capacitor CC will be explained 000e 000elater, in Chapter 11. All transistors have β = 100, 000eVBE 000e = 0.7 V, and ro = ∞.
5V 0.4 mA 0.5 mA Q1
Q6
CC
Q2
vo Q5
Q3
1 mA
RL
Q4
5V Figure P9.119
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 693
3.3 k 8.2 k 68 k Q2 Q1
vi
Q3 vo
33 k
5.6 k 2.4 k
4.7 k 5V
9.121 In the multistage amplifier of Fig. 9.41, emitter resistors are to be introduced—100 0002 in the emitter lead of each of the first-stage transistors and 25 0002 for each of the second-stage transistors. What is the effect on input resistance, the voltage gain of the first stage, and the overall voltage gain? Use the bias values found in Example 9.7. D 9.122 Consider the circuit of Fig. 9.41 and its output resistance. Which resistor has the most effect on the output resistance? What should this resistor be changed to if the output resistance is to be reduced by a factor of 2? What will the amplifier gain become after this change? What other change can you make to restore the amplifier gain to approximately its prior value? D 9.123 (a) If, in the multistage amplifier of Fig. 9.41, the resistor R5 is replaced by a constant-current source 0003 1 mA, such that the bias situation is essentially unaffected, what does the overall voltage gain of the amplifier become? Assume that the output resistance of the current source is very high. Use the results of Example 9.8. (b) With the modification suggested in (a), what is the effect of the change on output resistance? What is the overall gain of the amplifier when loaded by 100 0002 to ground? The original amplifier (before modification) has an output resistance of 152 0002 and a voltage gain of 8513 V/V. What is its gain when loaded by 100 0002? Comment. Use β = 100. *9.124 Figure P9.124 shows a three-stage amplifier in which the stages are directly coupled. The amplifier, however, utilizes bypass capacitors, and, as such, its frequency response falls off at low frequencies. For our purposes here, we shall assume that the capacitors are large enough to act as perfect short circuits at all signal frequencies of interest.
Figure P9.124
(a) Find the dc bias current in each of the three transistors. 000e 000e Also find the dc voltage at the output. Assume 000eVBE 000e = 0.7 V, β = 100, and neglect the Early effect. (b) Find the input resistance and the output resistance. (c) Use the current-gain method to evaluate the voltage gain v o /v i . 9.125 For the current mirror in Fig. P9.125, replace the transistors with their hybrid-π models and show that: 1 r gm1 o1 0005 0006 000e 000e 1 Ais 0003 Ais 000e 1− ideal gm1 ro1 000e 000e Ais 000e = gm2 /gm1 Ri =
ideal
Ro = ro2 where Ais denotes the short-circuit current gain.
ii i osc
Ri
Ro Q1
Figure P9.125
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Q2
PROBLEMS
9.120 A BJT differential amplifier, biased to have re = 50 0002 and utilizing two 50-0002 emitter resistors and 5-k0002 loads, drives a second differential stage biased to have re = 25 0002. All BJTs have β = 100. What is the voltage gain of the first stage? Also find the input resistance of the first stage, and the current gain from the input of the first stage to the collectors of the second stage.
CHAPTER 9
5V
(a) For inputs grounded and output held at 0 V (by negative feedback, not shown) find the emitter currents of all transistors. (b) Calculate the gain of the amplifier with RL = 1 k0002.
CHAPTER 9
PROBLEMS
694 Chapter 9 Differential and Multistage Amplifiers **9.126 The MOS differential amplifier shown in Fig. P9.126 utilizes three current mirrors for signal transmission: Q4−Q6 has a transmission factor of 2 [i.e., (W/L)6 /(W/L)4 = 2], Q3−Q5 has a transmission factor of 1, and Q7−Q8 has a transmission factor of 2. All transistors 000e 000e are 000eVOV 000e. All sized to operate at the same overdrive000e voltage, 000e transistors have the same Early voltage 000eVA 000e.
Q3
Q4
Q1
Q2
00042 0003 CMRR = 4 VA /VOV
(e) Find the input000e CM 000e range 000e and 000e the output linear range in terms of VDD , 000eVt 000e, and 000eVOV 000e. D ***9.127 For the circuit shown in Fig. P9.127, which uses a000e folded cascode involving transistor Q3 , all transistors have 000e 000eVBE 000e = 0.7 V for the currents involved, VA = 200 V, and β = 100. The circuit is relatively conventional except for Q5 , which operates in a Class B mode (we will study this in Chapter 12) to provide an increased negative output swing for low-resistance loads.
VDD Q5
VOV , show that the CMRR is given by
Q6
vo
5V I
Q7
Q8
VDD
Figure P9.126
QF 1 F
QG 2
Q3
v
(a) Provide in tabular form the values of ID , gm , and ro of each of the eight transistors in terms of I, VOV , and VA . (b) Show that the differential voltage gain Ad is given by 0003 0004 Ad = 2gm1 ro6 ro8 = VA /VOV (c) Show that the CM gain is given by
where gm and ro are the parameters of the input transistor of the mirror. (see Problem 9.125 above.)] (d) If the current source I is implemented using a simple mirror and the MOS transistor is operated at the same
Q4
Q2
Q1
D
R IREF A
B QB
QA 1
vO
Q5
C
v
000e 000e ro6 ro8 1 000eAcm 000e 0003 RSS gm7 ro7 where RSS is the output resistance of the bias current source I. [Hint: Replace each of Q1 and Q2 together with their source resistance 2RSS with a controlled current-source v icm /2RSS and an output resistance. For each current mirror, the current transfer ratio is given by 0005 0006 1 Ai 0003 Ai (ideal) 1 − gm ro
G
QE 1 E
QC
2
1
QD 10
5V Figure P9.127
000e 000e (a) Perform a bias calculation assuming 000eVBE 000e = 0.7 V, high β, VA = ∞, v + = v − = 0 V, and v O is stabilized by feedback to about 0 V. Find R so that the reference current IREF is 100 μA. What are the voltages at all the labeled nodes? (b) Provide in tabular form the bias currents in all transistors together with gm and ro for the signal transistors (Q1 , Q2 , Q3 , Q4 , and Q5 ) and ro for QC , QD , and QG . (c) Now, using β = 100, find the voltage gain v o /(v + − v − ), and in the process, verify the polarity of the input terminals.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 695
D ***9.128 In the 000eCMOS op amp shown in Fig. P9.128, all 000e 000eVt 000e = 1V, μn Cox = 2 μp Cox = 40 μA/V2 , MOS devices have 000e 000e 000eVA 000e = 50 V, and L = 5 μm. Device widths are indicated on the diagram as multiples of W, where W = 5 μm. (a) Design R to provide a 10-μA reference current. (b) Assuming v O = 0 V, as established by external feedback, perform a bias analysis, finding all the labeled node voltages, and VGS and ID for all transistors. (c) Provide in table form ID , VGS , gm , and ro for all devices. 0004 0003 (d) Calculate the voltage gain v o / v + − v − , the input resistance, and the output resistance. (e) What is the input common-mode range? (f) What is the output signal range for no load?
PROBLEMS
(g) Now consider the situation with a load resistance connected from the output to ground. At the positive and negative limits of the output signal swing, find the smallest load resistance that can be driven if one or the other of Q1 or Q2 is allowed to cut off.
(g) For what load resistance connected to ground is the output negative voltage limited to −1 V before Q7 begins to conduct? (h) For a load resistance one-tenth of that found in (g), what is the output signal swing?
5V 2W
1W QF F QE 1W E
4W Q4
Q3 G
H
10W
1W
20W
v
IREF
Q6
Q2
Q1 1W
R
Q5 2W
v
Q7
C
D
B
A QA 1W
2W
QB
1W 5V
Figure P9.128
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
QC
CHAPTER 9
(d) Find the input and output resistances. (e) Find the input common-mode range for linear operation. (f) For no load, 000e what000e is the range of available output voltages, assuming 000eVCEsat 000e = 0.3 V?
5W
QD
vO
Problems 789
in the CS (CE) amplifier alone. The key, however, is to design the cascode so that the gain obtained in the CS (CE) stage is minimized. 0002
The source and emitter followers can have complex poles. Thus, their frequency response is evaluated using the complete transfer function. Followers of both types exhibit wide bandwidths.
0002
The high-frequency response of the differential amplifier can be obtained by considering the differential and common-mode half-circuits. The CMRR falls off at
a relatively low frequency determined by the output impedance of the bias current source. 0002
The high-frequency response of the current-mirror-loaded differential amplifier is complicated by the fact that there are two signal paths between input and output: a direct path and one through the current mirror.
0002
Combining two transistors in a way that eliminates or minimizes the Miller effect can result in a much wider bandwidth. Some such configurations are presented in Section 10.8.
PROBLEMS
Computer Simulation Problems Problems identified by the Multisim/PSpice icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as gain–bandwidth trade-off. Instructions to assist in setting up PSpice and Multisim simulations for all the indicated problems can be found in the corresponding files on the website. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
10.4 The amplifier in Fig. 10.3(a) is biased to operate at gm = 5 mA/V, and has the following component values: Rsig = 100 k0004, RG1 = 47 M0004, RG2 = 10 M0004, CC1 = 0.01 μF, RS = 2 k0004, CS = 10 μF, RD = 4.7 k0004, RL = 10 k0004, and CC2 = 1 μF. Find AM , fP1 , fP2 , fZ , fP3 , and fL . D 10.5 The amplifier in Fig. P10.5 is biased to operate at gm = 2 mA/V. Neglect ro .
VDD
Section 10.1: Low-Frequency Response of Discrete-Circuit Common-Source and Common-Emitter Amplifiers D 10.1 For the amplifier in Fig. 10.3(a), if RG1 = 2 M0004, RG2 = 1 M0004, and Rsig = 200 k0004, find the value of the coupling capacitor CC1 (specified to one significant digit) that places the associated pole at 10 Hz or lower. D 10.2 For the amplifier in Fig. 10.3(a), if RD = 10 k0004, RL = 10 k0004, and ro is very large, find the value of CC2 (specified to one significant digit) that places the associated pole at 10 Hz or lower. D 10.3 The amplifier in Fig. 10.3(a) is biased to operate at gm = 5 mA/V, and RS = 1.8k0004. Find the value of CS (specified to one significant digit) that places its associated pole at 100 Hz or lower. What are the actual frequencies of the pole and zero realized?
RD Vo CS Vi
0002 0003
RS 4.5 k0006
0003VSS
Figure P10.5
(a) Determine the value of RD that results in a midband gain of −20 V/V. (b) Determine the value of CS that results in a pole frequency of 100 Hz. (c) What is the frequency of the transmission zero introduced by CS ? (d) Give an approximate value for the 3-dB frequency fL .
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 10
PROBLEMS
790 Chapter 10 Frequency Response (e) Sketch a Bode plot for the gain of this amplifier. What does the plot tell you about the gain at dc? Does this make sense? Why or why not? D 10.6 Figure P10.6 shows a CS amplifier biased by a constant-current source I. Let Rsig = 0.5 M0004, RG = 2 M0004, gm = 3 mA/V, RD = 20 k0004, and RL = 10 k0004. Find AM . Also,
design the coupling and bypass capacitors to locate the three low-frequency poles at 100 Hz, 10 Hz, and 1 Hz. Use a minimum total capacitance, with the capacitors specified only to a single significant digit. What value of fL results? D 10.7 Figure P10.7 shows a current-biased CE amplifier operating at 100 μA from ±3-V power supplies. It employs
VDD
RD
CC2 Vo
Rsig
CC1
RL CS
Vsig 0002 0003
RG I
–VSS Figure P10.6
VCC
RC
CC2 Vo
Rsig
CC1
RL CE
Vsig 0002 0003
RB I
–VEE Figure P10.7
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 791
D 10.9 For the amplifier described in Problem 10.8, design the coupling and bypass capacitors for a lower 3-dB frequency of 50 Hz. Design so that the contribution of each of CC1 and CC2 to determining fL is only 10%.
*10.12 The BJT common-emitter amplifier of Fig. P10.12 includes an emitter-degeneration resistance Re .
VCC
10.10 Consider the circuit of Fig. 10.9(a). For Rsig = 5 k0004, RB ≡ RB1 0002 RB2 = 10 k0004, rπ = 1 k0004, β 0 = 100, and RE = 1.5 k0004, what is the ratio CE /CC1 that makes their contributions to the determination of fL equal?
RC Vo
D *10.11 For the common-emitter amplifier of Fig. P10.11, neglect ro and assume the current source to be ideal.
VCC
Vsig
0002 0003
Re CE
RC
Rsig
CE Vsig
RL Figure P10.12
0002 0003 I
Figure P10.11
I
Vo
CC
(a) Assuming α 0005 1, neglecting ro , and assuming the current source to be ideal, derive an expression for the small-signal voltage gain A(s) ≡ Vo /Vsig that applies in the midband and the low-frequency band. Hence find the midband gain AM and the lower 3-dB frequency fL .
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
10.8 Consider the common-emitter amplifier of Fig. 10.9(a) under the following conditions: Rsig = 5 k0004, RB1 = 33 k0004, RB2 = 22 k0004, RE = 3.9 k0004, RC = 4.7 k0004, RL = 5.6 k0004, VCC = 5 V. The dc emitter current can be shown to be IE 0005 0.3 mA, at which β = 120. Find the input resistance Rin and the midband gain AM . If CC1 = CC2 = 1 μF and CE = 20 μF, find the three short-circuit time constants and an estimate for fL .
(a) Derive an expression for the midband gain. (b) Convince yourself that the two poles caused by CE and CC do not interact. Find expressions for their frequencies, ωPE and ωPC . (c) Give an expression for the amplifier voltage gain Vo (s)/Vsig (s) in terms of AM , ωPE , and ωPC . (d) For Rsig = RC = RL = 10 k0004, β = 100, and I = 1 mA, find the value of the midband gain. (e) Select values for CE and CC to place the two pole frequencies a decade apart and to obtain a lower 3-dB frequency of 100 Hz while minimizing the total capacitance. (f) Sketch a Bode plot for the gain magnitude, and estimate the frequency at which the gain becomes unity.
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RC = 20 k0004, RB = 200 k0004, and operates between a 20-k0004 source and a 10-k0004 load. The transistor β = 100. Select CE first, for a minimum value specified to one significant digit and providing up to 80% of fL where fL is to be 100 Hz. Then choose CC1 and CC2 , each specified to one significant digit, and each contributing about 10% of fL . What fL results? What total capacitance is needed?
CHAPTER 10
PROBLEMS
792 Chapter 10 Frequency Response (b) Show that including Re reduces the magnitude of AM by a certain factor. What is this factor? (c) Show that including Re reduces fL by the same factor as in (b) and thus one can use Re to trade off gain for bandwidth. (d) For I = 0.25 mA, RC = 10 k0004, and CE = 10 μF, find AM and fL with Re = 0. Now find the value of Re that lowers fL by a factor of 10. What will the gain become? Sketch on the same diagram a Bode plot for the gain magnitude for both cases.
Section 10.2: Internal Capacitive Effects and the High-Frequency Model of the MOSFET and the BJT 10.13 Refer to the MOSFET high-frequency model in Fig. 10.12(a). Evaluate the model parameters for an NMOS transistor operating at ID = 200 μA, VSB = 1 V, and VDS = 1.5 V. The MOSFET has W = 20 μm, L = 1 μm, 2 1/2 tox = 8 nm, μn = 450 cm /V·s, γ = 0.5 V , 2φ f = 0.65 V, −1 λ = 0.05 V , V0 = 0.7 V, Csb0 = Cd b0 = 20 fF, and Lov = 0.05 μm. [Recall that gmb = χ gm , where χ = 0014
−11 γ / 2 2φf + VSB , and that eox = 3.45 × 10 F/m.] 10.14 Find fT for a MOSFET operating at ID = 200 μA and VOV = 0.3 V. The MOSFET has Cgs = 25 fF and Cgd = 5 fF. 10.15 Starting from the expression of fT for a MOSFET, fT =
gm 2π(Cgs + Cgd )
and making the approximation that Cgs 0003 Cgd and that the overlap component of Cgs is negligibly small, show that μn ID 1.5 fT 0005 πL 2Cox WL
Transistor
IE (mA)
(a) (b) (c) (d) (e) (f) (g)
2
re (0002)
gm (mA/V)
rπ (k0002)
Thus note that to obtain a high fT from a given device, it must be operated at a high current. Also note that faster operation is obtained from smaller devices. 10.16 Starting from the expression for the MOSFET unity-gain frequency, fT =
and making the approximation that Cgs 0003 Cgd and that the overlap component of Cgs is negligibly small, show that for an n-channel device fT 0005
10 0.1 1
3μn VOV 4πL 2
Observe that for a given channel length, fT can be increased by operating the MOSFET at a higher overdrive voltage. Evaluate fT for devices with L = 0.5 μm operated at overdrive 2 voltages of 0.2 V and 0.4 V. Use μn = 450 cm /V·s. 10.17 It is required to calculate the intrinsic gain A0 and the unity-gain frequency fT of an n-channel transistor fabricated in a 0.13-μm CMOS process for which Lov = 0.1 L, μn = 2 400 cm /V·s, and VA = 5 V/μm. The device is operated at VOV = 0.2 V. Find A0 and fT for devices with L = Lmin , 2Lmin , 3Lmin , 4Lmin , and 5Lmin . Present your results in a table. (Hint: For fT , use the approximate expression 3μn VOV .) fT 0005 4πL 2 10.18 A particular BJT operating at IC = 0.5 mA has Cμ = 1 pF, Cπ = 8 pF, and β = 100. What are fT and fβ for this situation? 10.19 For the transistor described in Problem 10.18, Cπ includes a relatively constant depletion-layer capacitance
β0
fT (MHz)
100
500
100 100 100 10
500 500 150 500 800
25 2.5
gm 2π(Cgs + Cgd )
Cμ (pF) 2 2 2 2 2 1
Cπ (pF)
fβ (MHz)
10.7 10.7
4
9
80
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 793
10.21 Measurement of hfe of an npn transistor at 50 MHz shows that hfe = 10 at IC = 0.2 mA and 12 at IC = 1.0 mA. Furthermore, Cμ was measured and found to be 0.1 pF. Find fT at each of the two collector currents used. What must τF and Cje be? 10.22 A particular small-geometry BJT has fT of 10 GHz and Cμ = 0.1 pF when operated at IC = 1.0 mA. What is Cπ in this situation? Also, find gm . For β = 120, find rπ and fβ . 10.23 For a BJT whose unity-gain bandwidth is 2 GHz and β 0 = 200, at what frequency does the magnitude of hfe become 40? What is fβ ? *10.24 For a sufficiently high frequency, measurement of the complex input impedance of a BJT having (ac) grounded emitter and collector yields a real part approximating rx . For what frequency, defined in terms of ωβ , is such an estimate of rx good to within 10% under the condition that rx ≤ rπ /10? *10.25 Complete the table entries on the previous page for transistors (a) through (g), under the conditions indicated. Neglect rx .
Section 10.3: High-Frequency Response of the CS and CE Amplifiers 10.26 In a particular common-source amplifier for which the midband voltage gain between gate and drain (i.e., −gm RL ) is −39 V/V, the NMOS transistor has Cgs = 1.0 pF and Cgd = 0.1 pF. What input capacitance would you expect? For what range of signal-source resistances can you expect the 3-dB frequency to exceed 1 MHz? Neglect the effect of RG . D 10.27 In the circuit of Fig. P10.27, the voltage amplifier is ideal (i.e., it has an infinite input resistance and a zero output resistance). (a) Use the Miller approach to find an expression for the input capacitance Cin in terms of A and C. (b) Use the expression for Cin to obtain the transfer function Vo (s)/Vsig (s).
Rsig
Vsig
0002 Vi 0003
0002 0003
0003 A 0002
0002 Vo 0003
Cin Figure P10.27
(c) If Rsig = 1 k0004, and the gain Vo /Vsig is to have a dc value of 40 dB and a 3-dB frequency of 100 kHz, find the values required for A and C. (d) Sketch a Bode plot for the gain and use it to determine the frequency at which its magnitude reduces to unity. 10.28 An ideal voltage amplifier having a voltage gain of –1000 V/V has a 0.2-pF capacitance connected between its output and input terminals. What is the input capacitance of the amplifier? If the amplifier is fed from a voltage source Vsig having a resistance Rsig = 1 k0004, find the transfer function Vo /Vsig as a function of the complex-frequency variable s and hence the 3-dB frequency fH and the unity-gain frequency ft . D 10.29 A design is required for a CS amplifier for which the MOSFET is operated at gm = 5 mA/V and has Cgs = 5 pF and Cgd = 1 pF. The amplifier is fed with a signal source having Rsig = 1 k0004, and RG is very large. What is the largest value of RL for which the upper 3-dB frequency is at least 6 MHz? What is the corresponding value of midband gain and gain–bandwidth product? If the specification on the upper 3-dB frequency can be relaxed by a factor of 3, that is, to 2 MHz, what can AM and GB become? 10.30 Reconsider Example 10.3 for the situation in which the transistor is replaced by one whose width W is half that of the original transistor while the bias current remains unchanged. Find modified values for all the device parameters along with AM , fH , and the gain–bandwidth product, GB. Contrast this with the original design by calculating the ratios of new value to old for W, VOV , gm , Cgs , Cgd , Cin , AM , fH , and GB. D *10.31 In a CS amplifier, such as that in Fig. 10.3(a), the resistance of the source Rsig = 100 k0004, amplifier
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
10.20 An npn transistor is operated at IC = 1 mA and VCB = 2 V. It has β 0 = 100, VA = 50 V, τF = 30 ps, Cje0 = 20 fF, Cμ0 = 30 f F, V0c = 0.75 V, mCBJ = 0.5, and rx = 100 0004. Sketch the complete hybrid-π model, and specify the values of all its components. Also, find fT .
C
CHAPTER 10
of 2 pF. If the device is operated at IC = 0.25 mA, what does its fT become?
CHAPTER 10
PROBLEMS
794 Chapter 10 Frequency Response input resistance (which is due to the biasing network) Rin = 100 k0004, Cgs = 1 pF, Cgd = 0.2 pF, gm = 3 mA/V, ro = 50 k0004, RD = 8 k0004, and RL = 10 k0004. Determine the expected 3-dB cutoff frequency fH and the midband gain. In evaluating ways to double fH , a designer considers the alternatives of changing either RL or Rin . To raise fH as described, what separate change in each would be required? What midband voltage gain results in each case? 10.32 A discrete MOSFET common-source amplifier has RG = 2 M0004, gm = 5 mA/V, ro = 100 k0004, RD = 20 k0004, Cgs = 3 pF, and Cgd = 0.5 pF. The amplifier is fed from a voltage source with an internal resistance of 500 k0004 and is connected to a 20-k0004 load. Find: (a) the overall midband gain AM (b) the upper 3-dB frequency fH (c) the frequency of the transmission zero, fZ . 10.33 For the discrete-circuit CS amplifier in Fig. 10.3(a) let Rsig = 100 k0004, RG1 = 47 M0004, RG2 = 10 M0004, RS = 2 k0004, RD = 4.7 k0004, RL = 10 k0004, gm = 3 mA/V, ro = 100 k0004, Cgs = 1 pF, and Cgd = 0.2 pF. Find AM and fH . 10.34 Consider the integrated-circuit CS amplifier in Fig. P10.34 for the case IBIAS = 100 μA, Q2 and Q3 are 2 matched, and Rsig = 200 k0004. For Q1 : μn Cox = 90 μA/V , VA = 12.8 V, W/L = 100 μm/1.6 μm, Cgs = 0.2 pF, and Cgd = 0.015 pF. For Q2 : |VA | = 19.2 V. Neglecting the effect of the capacitance inevitably present at the output node, find the low-frequency gain, the 3-dB frequency fH , and the frequency of the zero fZ .
Q3
Q2
IBIAS
Q1 Vsig
Figure P10.34
10.36 For a CE amplifier represented by the equivalent circuit in Fig. 10.19(a), let Rsig = 10 k0004, RB = 100 k0004, rx = 100 0004, Cπ = 10 pF, Cμ = 1 pF, gm = 40 mA/V, ro = 100 k0004, RC = 10 k0004, RL = 10 k0004, and β = 100. Find the midband gain and the 3-dB frequency fH . 10.37 A designer wishes to investigate the effect of changing the bias current IE on the midband gain and high-frequency response of the CE amplifier considered in Example 10.4. Let IE be doubled to 2 mA, and assume that β 0 and fT remain unchanged at 100 and 800 MHz, respectively. To keep the node voltages nearly unchanged, the designer reduces RB and RC by a factor of 2, to 50 k0004 and 4 k0004, respectively. Assume rx = 50 0004, and recall that VA = 100 V and that Cμ remains constant at 1 pF. As before, the amplifier is fed with a source having Rsig = 5 k0004 and feeds a load RL = 5 k0004. Find the new values of AM , fH , and the gain–bandwidth product, AM fH . Comment on the results. Note that the price paid for whatever improvement in performance is achieved is an increase in power. By what factor does the power dissipation increase? *10.38 The purpose of this problem is to investigate the high-frequency response of the CE amplifier when it is fed with a relatively large source resistance Rsig . Refer to the amplifier in Fig. 10.9(a) and to its high-frequency, equivalent-circuit model and the analysis shown in Fig. 10.19. Let RB 0003 Rsig , rx Rsig , Rsig 0003 rπ , gm RL 0003 1, and gm RL Cμ 0003 Cπ . Under these conditions, show that:
(a) the midband gain AM 0005 − βRL /Rsig (b) the upper 3-dB frequency fH 0005 1/2πCμ βRL (c) the gain–bandwidth product | AM | fH 0005 1/2πCμ Rsig
Vo
Rsig
10.35 A common-emitter amplifier is measured at midband and found to have a gain of −50 V/V between base and collector. If Cπ = 10 pF, Cμ = 1 pF, and the effective source resistance Rsig = 5 k0004 [refer to Fig. 10.19(b)], find Cin and the 3-dB frequency fH .
Evaluate this approximate value of the gain–bandwidth product for the case Rsig = 25 k0004 and Cμ = 1 pF. Now, if the transistor is biased at IC = 1 mA and has β = 100, find the midband gain and fH for the two cases RL = 25 k0004 and RL = 2.5 k0004. On the same coordinates, sketch Bode plots for the gain magnitude versus frequency for the two cases. What fH is obtained when the gain is unity? What value of RL corresponds? 10.39 For a version of the CE amplifier circuit in Fig. 10.9(a), Rsig = 10 k0004, RB1 = 68 k0004, RB2 = 27 k0004,
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 795
10.41 The amplifiers listed below are characterized by the descriptor (A, C), where A is the voltage gain from input to output and C is an internal capacitor connected between input and output. For each, find the equivalent capacitances at the input and at the output as provided by the use of Miller’s theorem: (a) (b) (c) (d) (e)
–1000 V/V, 1 pF –10 V/V, 10 pF –1 V/V, 10 pF +1 V/V, 10 pF +10 V/V, 10 pF
Note that the input capacitance found in case (e) can be used to cancel the effect of other capacitance connected from input to ground. In (e), what capacitance can be canceled?
Vsig 0002 0003
A
Rin
Vi
Vo
ZL R Rin
Figure P10.42
resistance becomes infinite and the current IL into the load impedance ZL becomes Vsig /R. The circuit then functions as an ideal voltage-controlled current source with an output current IL . (c) If ZL is a capacitor C, find the transfer function Vo /Vsig and show it is that of an ideal noninverting integrator. 10.43 Use Miller’s theorem to investigate the performance of the inverting op-amp circuit shown in Fig. P10.43. Assume the op amp to be ideal except for having a finite differential gain, A. Without using any knowledge of op-amp circuit analysis, find Rin , Vi , Vo , and Vo /Vsig , for each of the following values of A: 10 V/V, 100 V/V, 1000 V/V, and 10,000 V/V. Assume Vsig = 1 V. Present your results in the table below.
10 k0006
*10.42 Figure P10.42 shows an ideal voltage amplifier with a gain of +2 V/V (usually implemented with an op amp connected in the noninverting configuration) and a resistance R connected between output and input. (a) Using Miller’s theorem, show that the input resistance Rin = −R. (b) Use Norton’s theorem to replace Vsig , Rsig , and Rin with a signal current source and an equivalent parallel resistance. Show that by selecting Rsig = R, the equivalent parallel
00022
IL
1 k0006
Vsig
0003 Vi 0002
0002 0003
0003 0002
0002 Vo 0003
Rin Figure P10.43
Vo
Vo /Vsig
10 V/V 100 V/V 1000 V/V 10,000 V/V
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
10.40 Consider an ideal voltage amplifier with a gain of 0.9 V/V, and a resistance R = 100 k0004 connected in the feedback path—that is, between the output and input terminals. Use Miller’s theorem to find the input resistance of this circuit.
Rsig
CHAPTER 10
RE = 2.2 k0004, RC = 4.7 k0004, and RL = 10 k0004. The collector current is 0.8 mA, β = 200, fT = 1 GHz, and Cμ = 0.8 pF. Neglecting the effect of rx and ro , find the midband voltage gain and the upper 3-dB frequency fH .
CHAPTER 10
PROBLEMS
796 Chapter 10 Frequency Response *10.44 The amplifier shown in Fig. P10.44 has Rsig = RL = 1 k0004, RC = 1 k0004, RB = 47 k0004, β = 100, Cμ = 0.8 pF, and fT = 600 MHz. Assume the coupling capacitors to be very large.
10.46 A CS amplifier modeled with the equivalent circuit of Fig. 10.22(a) is specified to have Cgs = 2 pF, Cgd = 0.1 pF, gm = 4 mA/V, CL = 2 pF, and RL = 20 k0004. Find AM , f3dB , fZ , and ft .
(a) Find the dc collector current of the transistor. (b) Find gm and rπ . (c) Neglecting ro , find the midband voltage gain from base to collector (neglect the effect of RB ). (d) Use the gain obtained in (c) to find the component of Rin that arises as a result of RB . Hence find Rin . (e) Find the overall gain at midband. (f) Find Cin . (g) Find fH .
D 10.47 A common-source amplifier fed with a low-resistance signal source and operating with gm = 2 mA/V has a unity-gain frequency of 2 GHz. What additional capacitance must be connected to the drain node to reduce ft to 1 GHz?
00021.5 V
RC CC1
Rsig
RB
CC2 Vo
Vsig 0002 0003
RL Rin
Figure P10.44
*10.45 Figure P10.45 shows a diode-connected transistor with the bias circuit omitted. Utilizing the BJT high-frequency, hybrid-π model with rx = 0 and ro = ∞, derive an expression for Zi (s) as a function of re and Cπ . Find the frequency at which the impedance has a phase angle of 45° for the case in which the BJT has fT = 400 MHz and the bias current is relatively high. What is the frequency when the bias current is reduced so that Cπ 0005 Cμ ? Assume α = 1.
*10.48 It is required to analyze the high-frequency response of the CMOS amplifier shown in Fig. P10.34 for the case Rsig = 0. The dc bias current is 100 μA. For Q1 , 2 μn Cox = 90 μA/V , VA = 12.8 V, W/L = 100 μm/1.6 μm, Cgs = 0.2 pF, Cgd = 0.015 pF, and Cd b = 20 fF. For Q2 , Cgd = 0.015 pF, Cd b = 36 fF, and VA = 19.2 V. For simplicity, assume that the signal voltage at the gate of Q2 is zero. Find the low-frequency gain, the frequency of the pole, and the frequency of the zero. (Hint: The total capacitance at the output mode = Cd b1 + Cd b2 + Cgd2 ). 10.49 Consider an active-loaded common-emitter amplifier. Let the amplifier be fed with an ideal voltage source Vi , and neglect the effect of rx . Assume that the load current source has a very high resistance and that there is a capacitance CL present between the output node and ground. This capacitance represents the sum of the input capacitance of the subsequent stage and the inevitable parasitic capacitance between collector and ground. Show that the voltage gain is given by
1 − s Cμ /gm Vo
= −gm ro Vi 1 + s C L + Cμ ro If the transistor is biased at IC = 200 μA and VA = 100 V, Cμ = 0.2 pF, and CL = 1 pF, find the dc gain, the 3-dB frequency, the frequency of the zero, and the frequency at which the gain reduces to unity. Sketch a Bode plot for the gain magnitude. 10.50 A particular BJT operating at 2 mA is specified to have fT = 2 GHz, Cμ = 1 pF, rx = 100 0004, and β = 120. The device is used in a CE amplifier operating from a very-low-resistance voltage source.
Figure P10.45
(a) If the midband gain obtained is −10 V/V, what is the value of fH ? (b) If the midband gain is reduced to −1 V/V (by changing RL ), what fH is obtained?
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 797
10.52 An amplifier with a dc gain of 60 dB has a single-pole, high-frequency response with a 3-dB frequency of 100 kHz. (a) (b) (c) (d) (e)
Give an expression for the gain function A(s). Sketch Bode diagrams for the gain magnitude and phase. What is the gain–bandwidth product? What is the unity-gain frequency? If a change in the amplifier circuit causes its transfer function to acquire another pole at 1 MHz, sketch the resulting gain magnitude and specify the unity-gain frequency. Note that this is an example of an amplifier with a unity-gain bandwidth that is different from its gain–bandwidth product.
10.53 Consider an amplifier whose FH (s) is given by FH (s) = 0003
s 1+ ω P1
1 00040003 0004 s 1+ ω P2
with ωP1 < ωP2 . Find the ratio ωP2 /ωP1 for which the value of the 3-dB frequency ωH calculated using the dominant-pole approximation differs from that calculated using the root-sum-of-squares formula (Eq. 10.77) by: (a) 10% (b) 1% 10.54 The high-frequency response of a direct-coupled amplifier having a dc gain of –1000 V/V incorporates zeros at 4 3 ∞ and 10 rad/s (one at each frequency) and poles at 10 rad/s 5 and 10 rad/s (one at each frequency). Write an expression for the amplifier transfer function. Find ωH using (a) the dominant-pole approximation (b) the root-sum-of-squares approximation (Eq. 10.77). If a way is found to lower the frequency of the finite zero to 3 10 rad/s, what does the transfer function become? What is the 3-dB frequency of the resulting amplifier?
10.56 An IC CS amplifier has gm = 2 mA/V, Cgs = 30 fF, Cgd = 5 fF, CL = 30 fF, Rsig = 10 k0004, and RL = 20 k0004. Use the method of open-circuit time constants to obtain an estimate for fH . Also, find the frequency of the transmission zero, fZ .
PROBLEMS
10.51 A direct-coupled amplifier has a low-frequency gain of 40 dB, poles at 2 MHz and 20 MHz, a zero on the negative real axis at 200 MHz, and another zero at infinite frequency. Express the amplifier gain function in the form of Eqs. (10.70) and (10.71), and sketch a Bode plot for the gain magnitude. What do you estimate the 3-dB frequency fH to be?
10.55 A direct-coupled amplifier has a dominant pole at 1000 rad/s and three coincident poles at a much higher frequency. These nondominant poles cause the phase lag of the amplifier at high frequencies to exceed the 90° angle due to the dominant pole. It is required to limit the excess phase at ω = 7 10 rad/s to 30° (i.e., to limit the total phase angle to –120°). Find the corresponding frequency of the nondominant poles.
CHAPTER 10
Section 10.4: Useful Tools for the Analysis of the High-Frequency Response of Amplifiers
10.57 For a particular amplifier modeled by the circuit of Fig. 10.18(a), gm = 5 mA/V, Rsig = 150 k0004, RG = 0.65 M0004, RL = 10 k0004, Cgs = 2 pF, and Cgd = 0.5 pF. There is also a load capacitance of 30 pF. Find the corresponding midband voltage gain, the open-circuit time constants, and an estimate of the 3-dB frequency. 10.58 Consider the high-frequency response of an amplifier consisting of two identical stages in cascade, each with an input resistance of 10 k0004 and an output resistance of 2 k0004. The two-stage amplifier is driven from a 10-k0004 source and drives a 1-k0004 load. Associated with each stage is a parasitic input capacitance (to ground) of 10 pF and a parasitic output capacitance (to ground) of 2 pF. Parasitic capacitances of 10 pF and 7 pF also are associated with the signal-source and load connections, respectively. For this arrangement, find the three poles and estimate the 3-dB frequency fH . 10.59 A CS amplifier that can be represented by the equivalent circuit of Fig. 10.24 has Cgs = 2 pF, Cgd = 0.1 pF, CL = 2 pF, gm = 4 mA/V, and Rsig = RL = 20 k0004. Find the midband gain AM , the input capacitance Cin using the Miller approximation, and hence an estimate of the 3-dB frequency fH . Also, obtain another estimate of fH using open-circuit time constants. Which of the two estimates is more appropriate and why? D 10.60 For a CS amplifier with gm = 5 mA/V, Cgs = 5 pF, Cgd = 1 pF, CL = 5 pF, Rsig = 10 k0004, and RL = 10 k0004, find τH and fH . What is the percentage of τH that is caused by the interaction of Rsig with the input capacitance? To what value must Rsig be lowered in order to double fH ? D 10.61 For the CS amplifier in Example 10.8, find the value of the additional capacitance to be connected at the output node in order to lower fH to 100 MHz.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
10.62 Consider the CE amplifier whose equivalent circuit is shown in Fig. 10.19(a) but with a capacitance CL connected across the output terminals. Let Rsig = 5 k0004, RB = ∞, rx = 0, gm = 20 mA/V, β = 100, Cπ = 10 pF, Cμ = 1 pF, RL = 5 k0004, and CL = 10 pF. Find AM and fH .
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798 Chapter 10 Frequency Response
10.63 A common-emitter amplifier has Cπ = 10 pF, Cμ = 0.3 pF, CL = 3 pF, gm = 40 mA/V, β = 100, rx = 100 0004, RL = 5 k0004, and Rsig = 1 k0004. Find the midband gain AM and an estimate of the 3-dB frequency fH using the Miller approximation. Also, obtain another estimate of fH using the method of open-circuit time constants. Which of the two estimates would you consider to be more realistic, and why? 10.64 Consider a CS amplifier loaded in a current source with an output resistance equal to ro of the amplifying transistor. The amplifier is fed from a signal source with Rsig = ro /2. The transistor is biased to operate at gm = 2 mA/V and ro = 20 k0004; Cgs = Cgd = 0.1 pF. Use the Miller approximation to determine an estimate of fH . Repeat for the following two cases: (i) the bias current I in the entire system is reduced by a factor of 4, and (ii) the bias current I in the entire system is increased by a factor of 4. Remember that both Rsig and RL will change as ro changes. 10.65 Use the method of open-circuit time constants to find fH for a CS amplifier for which gm = 1.5 mA/V, Cgs = Cgd = 0.2 pF, ro = 20 k0004, RL = 12 k0004, and Rsig = 100 k0004 for the following cases: (a) CL = 0, (b) CL = 10 pF, and (c) CL = 50 pF. Compare with the value of fH obtained using the Miller approximation.
Section 10.5: High-Frequency Response of the Common-Gate and Cascode Amplifiers 10.66 A CG amplifier is specified to have Cgs = 4 pF, Cgd = 0.2 pF, CL = 2 pF, gm = 5 mA/V, Rsig = 1 k0004, and RL = 10 k0004. Neglecting the effects of ro , find the low-frequency gain Vo /Vsig , the frequencies of the poles fP1 and fP2 , and hence an estimate of the 3-dB frequency fH . *10.67 Sketch the high-frequency equivalent circuit of a CB amplifier fed from a signal generator characterized by Vsig and Rsig and feeding a load resistance RL in parallel with a capacitance CL . (a) Show that for rx = 0 and ro = ∞, the circuit can be separated into two parts: an input part that produces a
pole at fP1 =
1
2πCπ Rsig 0002 re
and an output part that forms a pole at fP2 =
1 2π(Cμ + CL )RL
Note that these are the bipolar counterparts of the MOS expressions in Eqs. (10.94) and (10.95). (b) Evaluate fP1 and fP2 and hence obtain an estimate for fH for the case Cπ = 10 pF, Cμ = 1 pF, CL = 1 pF, IC = 1 mA, Rsig = 1 k0004, and RL = 10 k0004. Also, find fT of the transistor. 10.68 Consider a CG amplifier loaded in a resistance RL = ro and fed with a signal source having a resistance Rsig = ro /2. Also let CL = Cgs . Use the method of open-circuit time constants to show that for gm ro 0003 1, the upper 3-dB frequency is related to the MOSFET fT by the approximate expression
fH = fT / gm ro 10.69 For the CG amplifier in Example 10.9, how much additional capacitance should be connected between the output node and ground to reduce fH to 200 MHz? 10.70 An IC CG amplifier is fed from a signal source with Rsig = ro /2, where ro is the MOSFET output resistance. It has a current-source load with an output resistance equal to ro . The MOSFET is operated at ID = 100 μA and has gm = 1.5 mA/V, VA = 10 V, Cgs = 0.2 pF, Cgd = 0.015 pF, and Cd b = 20 fF. As well, the current-source load provides an additional 30 fF capacitance at the output node. Find fH . 10.71 Find the dc gain and the 3-dB frequency of a MOS cascode amplifier operated at gm = 2 mA/V and ro = 20 k0004. The MOSFETs have Cgs = 20 fF, Cgd = 5 fF, and Cd b = 5 fF. The amplifier is fed from a signal source with Rsig = 100 k0004 and is connected to a load resistance of 1 M0004. There is also a load capacitance CL of 20 fF. *10.72 (a) Consider a CS amplifier having Cgd = 0.2 pF, Rsig = RL = 20 k0004, gm = 4mA/V, Cgs = 2 pF, CL (including Cd b ) = 1 pF, Cd b = 0.2 pF, and ro = 20 k0004. Find the low-frequency gain AM , and estimate fH using open-circuit time constants. Hence determine the gain–bandwidth product. (b) If a CG stage utilizing an identical MOSFET is cascaded with the CS transistor in (a) to create a cascode amplifier, determine the new values of AM , fH , and gain–bandwidth product. Assume RL remains unchanged.
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Problems 799
1 Cgs + (gm ro )Cgd 2 N= Cgs + 3 Cgd Assume that the bandwidth of the cascode amplifier is primarily determined by the input circuit. (b) If Cgd = 0.1 Cgs and the dc gain of the CS amplifier is 50, what is the value of N? 2 (c) If VA = 10 V, μn Cox = 400 μA/V , and W/L = 10, find VOV and ID at which the transistors must be operating. 10.75 (a) For an integrated-circuit MOS cascode amplifier fed with a source having a very small resistance and loaded in a resistance equal to its Ro , use the expression for the unity-gain bandwidth in Fig. 10.29 to show that
ft =
0014 2μn Cox (W/L) 0014 ID 2π(CL + Cgd ) 2
(b) For μn Cox = 400 μA/V , W/L = 20, CL = 20 fF, Cgd = 5 fF, and VA = 10 V, provide in table form ft (GHz), VOV (V), gm (mA/V), ro (k0004), Ro (M0004), AM (V/V), and fH (MHz) for ID = 100 μA, 200 μA, and 500 μA. 10.76 Consider a bipolar cascode amplifier biased at a current of 1 mA. The transistors used have β = 100, ro = 100 k0004, Cπ = 10 pF, Cμ = 2 pF, Ccs = 0, and rx = 50 0004. The amplifier is fed with a signal source having Rsig = 5 k0004. The load resistance RL = 2 k0004. Find the low-frequency gain AM , and estimate the value of the 3-dB frequency fH .
(a) Refer to the circuit in Fig. 10.30, and note that the total resistance between the collector of Q1 and ground will be equal to re2 , which is usually very small. It follows that the pole introduced at this node will typically be at a very high frequency and thus will have negligible effect on fH . It also follows that at the frequencies of interest the gain from the base to the collector of Q1 will be −gm1 re2 0005 − 1. Use this to find the capacitance at the input of Q1 and hence show that the pole introduced at the input node will have a frequency fP1 0005
1
Cπ 1 + 2Cμ1 2πRsig
Then show that the pole introduced at the output node will have a frequency fP2 0005
1
2πRL CL + Ccs2 + Cμ2
(b) Evaluate fP1 and fP2 , and use the sum-of-the-squares formula to estimate fH for the amplifier with I = 1 mA, Cπ = 10 pF, Cμ = 2 pF, Ccs = CL = 0, β = 100, RL = 2 k0004, and rx = 0 in the following two cases: (i) Rsig = 1 k0004 (ii) Rsig = 10 k0004 10.78 A BJT cascode amplifier uses transistors for which β = 100, VA = 100 V, fT = 1 GHz, and Cμ = 0.1 pF. It operates at a bias current of 0.1 mA between a source with Rsig = rπ and a load RL = βro . Let CL = Ccs = 0, and rx = 0. Find the overall voltage gain at dc. By evaluating the various components of τH show that the pole introduced at the output mode is dominant. Find its frequency and hence an estimate of fH and ft .
Section 10.6: High-Frequency Response of the Source and Emitter Followers 10.79 A source follower has gm = 5 mA/V, gmb = 0, ro = 20 k0004, Rsig = 20 k0004, RL = 2 k0004, Cgs = 2 pF, Cgd = 0.1 pF, and CL = 1 pF. Find AM , Ro , fZ , the frequencies of the two poles, and an estimate of fH . 10.80 Using the expression for the source follower fH in Eq. (10.124) show that for situations in which CL = 0, Rsig
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PROBLEMS
10.74 (a) Show that introducing a cascode transistor to an IC CS amplifier whose bandwidth is limited by the interaction of Rsig and the input capacitance, and whose load resistance is equal to ro , increases the dc gain by approximately a factor of 2 and fH by the factor N,
*10.77 In this problem we consider the frequency response of the bipolar cascode amplifier in the case that ro can be neglected.
CHAPTER 10
D 10.73 It is required to design a cascode amplifier to provide a dc gain of 74 dB when driven with a low-resistance generator and utilizing NMOS transistors for which VA = 2 10 V, μn Cox = 200 μA/V , W/L = 50, Cgd = 0.1 pF, and CL = 1 pF. Assuming that RL = Ro , determine the overdrive voltage and the drain current at which the MOSFETs should be operated. Find the unity-gain frequency and the 3-dB frequency. If the cascode transistor is removed and RL remains unchanged, what will the dc gain become?
CHAPTER 10
PROBLEMS
800 Chapter 10 Frequency Response is large and RL is small, fH 0005
0003
1
2πRsig Cgd +
Cgs 1 + gm RL
0004
Find fH for the case Rsig = 100 k0004, RL = 2 k0004, ro = 20 k0004, gm = 5 mA/V, Cgd = 10 pF, and Cgs = 2 pF. 10.81 Refer to Fig. 10.31(c). In situations in which Rsig is large, the high-frequency response of the source follower is determined by the low-pass circuit formed by Rsig and the input capacitance. An estimate of Cin can be obtained by using the Miller approximation to replace Cgs with an input capacitance Ceq = Cgs (1 − K) where K is the gain from gate to source. Using the low-frequency value of K = gm RL /(1 + gm RL ) find Ceq and hence Cin and an estimate of fH . 10.82 A source follower has a maximally flat gain response with a dc gain of 0.8 and a 3-dB frequency of 1 MHz. Give its transfer function. 10.83 A discrete-circuit source follower driven with Rsig = 100 k0004 has Cgs = 10 pF, Cgd = 1 pF, CL = 10 pF, gmb = 0, and ro very large. The transfer function of the source follower is measured as RL is varied. At what value of RL will the transfer function be maximally flat? At this value of RL the dc gain is found to be 0.9 V/V. What is the 3-dB frequency? What is the value of gm at which the source follower is operating? 10.84 For an emitter follower biased at IC = 1 mA, having Rsig = RL = 1 k0004, and using a transistor specified to have fT = 2 GHz, Cμ = 0.1 pF, CL = 0, rx = 100 0004, β = 100, and VA = 20 V, evaluate the low-frequency gain AM , the frequency of the transmission zero, the pole frequencies, and an estimate of the 3-dB frequency fH .
Section 10.7: High-Frequency Response of Differential Amplifiers 10.85 A MOSFET differential amplifier such as that shown in Fig. 10.34(a) is biased with a current source I = 400 μA. 2 The transistors have W/L = 16, kn = 400 μA/V , VA = 20 V, Cgs = 40 fF, Cgd = 5 fF, and Cd b = 5 fF. The drain resistors are 10 k0004 each. Also, there is a 100-fF capacitive load between each drain and ground. (a) Find VOV and gm for each transistor. (b) Find the differential gain Ad .
(c) If the input signal source has a small resistance Rsig and thus the frequency response is determined primarily by the output pole, estimate the 3-dB frequency fH . (d) If, in a different situation, the amplifier is fed symmetrically with a signal source of 40 k0004 resistance (i.e., 20 k0004 in series with each gate terminal), use the open-circuit time-constants method to estimate fH . 10.86 A MOS differential amplifier is biased with a current source having an output resistance RSS = 100 k0004 and an output capacitance CSS = 1 pF. If the differential gain is found to have a dominant pole at 20 MHz, what is the 3-dB frequency of the CMRR? 10.87 The differential gain of a MOS amplifier is 100 V/V with a dominant pole at 10 MHz. The common-mode gain is 0.1 V/V at low frequencies and has a transmission zero at 1 MHz. Sketch a Bode plot for the CMRR. 10.88 In a particular MOS differential amplifier design, the bias current I = 100 μA is provided by a single transistor operating at VOV = 0.4 V with VA = 40 V and output capacitance CSS of 100 fF. What is the frequency of the
common-mode gain zero fZ at which Acm begins to rise above its low-frequency value? To meet a requirement for reduced power supply, consideration is given to reducing VOV to 0.2 V while keeping I unchanged. Assuming the current-source capacitance to be directly proportional to the device width, what is the impact on fZ of this proposed change? 10.89 Repeat Exercise 10.26 for the situation in which the bias current is reduced to 80 μA and RD is raised to 20 k0004. For (d), let Rsig be raised from 20 k0004 to 100 k0004. (Note: This is a low-voltage, low-power design.) 10.90 A BJT differential amplifier operating with a 0.5-mA current source uses transistors for which β = 100, fT = 500 MHz, Cμ = 0.5 pF, and rx = 100 0004. Each of the collector resistances is 10 k0004, and ro is very large. The amplifier is fed in a symmetrical fashion with a source resistance of 10 k0004 in series with each of the two input terminals. (a) Sketch the differential half-circuit and its high-frequency equivalent circuit. (b) Determine the low-frequency value of the overall differential gain. (c) Use the Miller approximation to determine the input capacitance and hence estimate the 3-dB frequency fH and the gain–bandwidth product.
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Problems 801
10.93 Consider the current-mirror-loaded CMOS differential amplifier of Fig.000b10.37(a) for the case of all transistors operated at the same VOV and having the same VA . Also let
the total capacitance at the output node CL be four times the total capacitance at the input node of the current mirror Cm . Give expressions for Ad , fP1 , fP2 , and fZ . Hence show that fP2 /fP1 = 4Ad and ft = gm /2πCL . For VA = 20 V, VOV = 0.2 V, I = 0.2 mA, CL = 100 fF, and Cm = 25 fF, find the dc value of Ad , and the value of fP1 , ft , fP2 , and fZ and sketch a Bode plot for Ad . *10.94 For the current mirror in Fig. P10.94, derive an expression for the current transfer function Io (s)/Ii (s) taking into account the BJT internal capacitances and neglecting rx and ro . Assume the BJTs to be identical. Observe that a signal ground appears at the collector of Q2 . If the mirror is biased at 1 mA and the BJTs at this operating point are characterized by fT = 500 MHz, Cμ = 2 pF, and β0 = 100, find the frequencies of the pole and zero of the transfer function.
10.95 Consider the case of a discrete-circuit CS amplifier in which a source-degeneration resistance is utilized to control the bandwidth. Assume that ro is very large and CL is negligibly small. Adapt the formulas given in the text for this case and thus give the expressions for AM and fH . Let Rsig = 100 k0004, gm = 5 mA/V, RL = 5 k0004, Cgs = 10 pF, and Cgd = 2 pF. Find |AM |, fH , and the gain–bandwidth product for these three cases: Rs = 0, 100 0004, and 200 0004. 10.96 A CS amplifier is specified to have gm = 5 mA/V, ro = 40 k0004, Cgs = 2 pF, ggd = 0.1 pF, CL = 1 pF, Rsig = 20 k0004, and RL = 40 k0004. (a) Find the low-frequency gain AM , and use open-circuit time constants to estimate the 3-dB frequency fH . Hence determine the gain–bandwidth product. (b) If a 400-0004 resistance is connected in the source lead, find the new values of AM , fH , and the gain–bandwidth product. D 10.97 (a) Use the approximate expression in Eq. (10.156) to determine the gain–bandwidth product of a CS amplifier with a source-degeneration resistance. Assume Cgd = 0.2 pF and Rsig = 100 k0004. (b) If a low-frequency gain of 20 V/V is required, what fH corresponds? (c) For gm = 5 mA/V, A0 = 100 V/V, and RL = 20 k0004, find the required value of Rs . 10.98 For the CS amplifier with a source-degeneration resistance Rs , show for Rsig 0003 Rs , ro 0003 Rs , and RL = ro that AM = and τH 0005
−A0 2+k
0003 0004 Cgs Rsig A0 + Cgd Rsig 1 + 1 + (k/2) 2+k 0004 0003
1+k + CL + Cgd ro 2+k
where k ≡ gm Rs
Figure P10.94
D *10.99 It is required to generate a table of AM , fH , and ft versus k ≡ gm Rs for a CS amplifier with a source-degeneration resistance Rs . The table should have entries for k = 0, 1, 2, . . ., 15. The amplifier is specified to have gm = 5 mA/V, ro = 40 k0004, RL = 40 k0004, Rsig = 20 k0004, Cgs = 2 pF, Cgd = 0.1 pF, and CL = 1 pF. Use the formulas
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
10.92 A current-mirror-loaded MOS differential amplifier is biased with a current source I = 0.2 mA. The two NMOS transistors of the differential pair are operating at VOV = 0.2 V, and the PMOS devices of the mirror are operating at |VOV | = 0.2 V. The Early voltage VAn = VAp = 10 V. The total capacitance at the input node of the mirror is 0.1 pF and that at the output node of the amplifier is 0.2 pF. Find the dc value and the frequencies of the poles and zero of the differential voltage gain.
Section 10.8: Other Wideband Amplifier Configurations
CHAPTER 10
10.91 A differential amplifier is biased by a current source having an output resistance of 1 M0004 and an output capacitance of 1 pF. The differential gain exhibits a dominant pole at 2 MHz. What are the poles of the CMRR?
CHAPTER 10
PROBLEMS
802 Chapter 10 Frequency Response for AM and τH given in the statement for Problem 10.98. If fH = 2 MHz is required, find the value needed for Rs and the corresponding value of AM . *10.100 In this problem we investigate the bandwidth extension obtained by placing a source follower between the signal source and the input of the CS amplifier.
(b) For the CD−CS amplifier in Fig. P10.100(b), show that
ro1 AM = − g r 1/gm1 + ro1 m2 o2 0003 0004 Rsig + ro1 1 + Cgs2 0002 ro1 τH = Cgd1 Rsig + Cgs1 1 + gm1 ro1 gm1 00060003 0004 0007
1 + Cgd2 0002 ro1 1 + gm2 ro2 + ro2 gm1
(a) First consider the CS amplifier of Fig. P10.100(a). Show that AM = −gm ro
0010
0011 τH = Cgs Rsig + Cgd Rsig 1 + gm ro + ro + CL ro
where CL is the total capacitance between the output node and ground. Calculate the value of AM , fH , and the gain–bandwidth product for the case gm = 1 mA/V, ro = 20 k0004, Rsig = 20 k0004, Cgs = 20 fF, Cgd = 5 fF, and CL = 10 fF.
+ CL ro2 Calculate the values of AM , fH , and the gain–bandwidth product for the same parameter values used in (a). Compare with the results of (a). *10.101 The transistors in the circuit of Fig. P10.101 have β 0 = 100, VA = 100 V, and Cμ = 0.2 pF. At a bias current of 100 μA, fT = 200 MHz. (Note that the bias details are not shown.)
I I Vo Rsig
Vo
Rsig Q1 Q2
Vsig

Vsig

(a)
I
(b)
Figure P10.100
100 A Rsig Vsig 100 A
Figure P10.101
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Problems 803
(Hint: Use the formulas in Example 10.13.)
VDD
where G0 =
RD
gm1 W = 1 gm2 W2
Vo Rsig Q1
Q2
Vsig 0002 0003 I
(a)
Figure P10.102
10.103 For the amplifier in Fig. 10.41(a), let I = 1 mA, β = 120, fT = 500 MHz, and Cμ = 0.5 pF, and neglect rx and ro . Assume that a load resistance of 10 k0004 is connected to the output terminal. If the amplifier is fed with a signal Vsig having a source resistance Rsig = 12 k0004, find AM and fH . 10.104 Consider the CD–CG amplifier of Fig. 10.41(c) for the case gm = 5 mA/V, Cgs = 2 pF, Cgd = 0.1 pF, CL (at the output node) = 1 pF, and Rsig = RL = 20 k0004. Neglecting ro , find AM and fH . (Hint: Evaluate fH directly from the transfer function.) D **10.105 This problem investigates the use of MOSFETs in the design of wideband amplifiers (Steininger, 1990). Such amplifiers can be realized by cascading low-gain stages. (a) Show that for the case Cgd Cgs and the gain of the common-source amplifier is low so that the Miller effect is negligible, the MOSFET can be modeled by the approximate equivalent circuit shown in Fig. P10.105(a), where ωT is the unity-gain frequency of the MOSFET.
(b) Figure P10.105
(c) For L = 0.5 μm, W2 = 25 μm, fT = 12 GHz, and 2 μn Cox = 200 μA/V , design the circuit to obtain a gain of 3 V/V per stage. Bias the MOSFETs at VOV = 0.3 V. Specify the required values of W1 and I. What is the 3-dB frequency achieved?
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PROBLEMS
10.102 Consider the circuit of Fig. P10.102 for the case: I = 200 μA and VOV = 0.2 V, Rsig = 100 k0004, RD = 50 k0004, Cgs = 4 pF, and Cgd = 0.5 pF. Find the dc gain, the high-frequency poles, and an estimate of fH .
(b) Figure P10.105(b) shows an amplifier stage suitable for the realization of low gain and wide bandwidth. Transistors Q1 and Q2 have the same channel length L but different widths W1 and W2 . They are biased at the same VGS and have the same fT . Use the MOSFET equivalent circuit of Fig. P10.105(a) to model this amplifier stage, assuming that its output is connected to the input of an identical stage. Show that the voltage gain Vo /Vi is given by Vo G0 =− s Vi
1+ ωT / G0 + 1
CHAPTER 10
(a) Find Rin and the midband gain. (b) Find an estimate of the upper 3-dB frequency fH . Which capacitor dominates? Which one is the second most significant?
PROBLEMS
*10.106 Figure P10.106 shows an amplifier formed by cascading two CS stages. Note that the input bias voltage is not shown. Each of Q000b1 and Q2 is operated at an overdrive voltage of 0.2 V, and VA = 10 V. The transistor capacitances are as follows: Cgs = 20 fF, Cgd = 5 fF, and Cd b = 5 fF. The signal-source resistance Rsig = 10 k0004.
CHAPTER 10
804 Chapter 10 Frequency Response
(a) Find the dc voltage gain. (b) Use the method of open-circuit time constants to determine an estimate for the 3-dB frequency fH .
VDD 0.1 mA Q2 Vo
Rsig Q1
0.1 mA
Vsig
**10.107 Consider the BiCMOS amplifier shown in Fig. P10.107. The BJT has VBE = 0.7 V, β = 200, Cμ = 0.8 pF, and fT = 600 MHz. The NMOS transistor has 2 Vt = 1 V, kn W/L = 2 mA/V , and Cgs = Cgd = 1 pF. (a) Consider the dc bias circuit. Neglect the base current of Q2 in determining the current in Q1 . Find the dc bias currents in Q1 and Q2 , and show that they are approximately 100 μA and 1 mA, respectively. (b) Evaluate the small-signal parameters of Q1 and Q2 at their bias points. (c) Consider the circuit at midband frequencies. First, determine the small-signal voltage gain Vo /Vi . (Note that RG can be neglected in this process.) Then use Miller’s theorem on RG to determine the amplifier input resistance Rin . Finally, determine the overall voltage gain Vo /Vsig . Assume ro of both transistors to be very large. (d) Consider the circuit at low frequencies. Determine the frequency of the poles due to C1 and C2 , and hence estimate the lower 3-dB frequency, fL . (e) Consider the circuit at higher frequencies. Use Miller’s theorem to replace RG with a resistance at the input. (The one at the output will be too large to matter.) Use open-circuit time constants to estimate fH . ***10.108 In each of the six circuits in Fig. P10.108, let β = 100, Cμ = 2 pF, and fT = 400 MHz, and neglect rx and ro . Calculate the midband gain AM and the 3-dB frequency fH .
Figure P10.106
5 V
RG 100 k
C1
3k C2
10 M
Vo 1 F
Vi
Q1
0.1 F
1k Q2
Vsig 6.8 k Rin Figure P10.107
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Problems 805
Vo
Vo
PROBLEMS
Vsig
Vsig
Vsig
(a)
(c)
(b)
Vo Vsig Vo
Vsig
(d)
(e)
Vo
Vsig
(f) Figure P10.108
CHAPTER 10
Vo
896 Chapter 11 Feedback unity; the amount by which it is less than unity, expressed in decibels, is the gain margin. Alternatively, the amplifier is stable if, at the frequency at which |Aβ| = 1, the phase angle is less than 180°; the difference is the phase margin.
desensitivity, bandwidth extension, and changes in Ri and Ro . 0002
0002
0002
The loop gain Aβ can be determined by breaking the feedback loop, as illustrated in Figs. 11.2 and 11.9. The value of Aβ can be used together with the feedback factor β to determine A and hence Af . This method, though simple, is incomplete as it does not enable the determination of the input and output resistances. For these, we utilize the systematic method for feedback analysis (refer to Table 11.2).
0002
The stability of a feedback amplifier can be analyzed by constructing a Bode plot for |A| and superimposing on it a plot for 20 log 1/|β|. Stability is guaranteed if the two plots intersect with a difference in slope no greater than 6 dB/octave.
0002
To make a given amplifier stable for a given feedback factor β, the open-loop frequency response is suitably modified by a process known as frequency compensation.
0002
A popular method for frequency compensation involves connecting a feedback capacitor across an inverting stage in the amplifier. This causes the pole formed at the input of the amplifier stage to shift to a lower frequency and thus become dominant, while the pole formed at the output of the amplifier stage is moved to a very high frequency and thus becomes unimportant. This process is known as pole splitting.
The ideal or upper-bound value of the closed-loop gain Af is 1/β and is approached when Aβ 0003 1. Since A and β are in general frequency dependent, the poles of the feedback amplifier are obtained by solving the characteristic equation 1 + A(s)β(s) = 0.
0002
For the feedback amplifier to be stable, its poles must all be in the left half of the s plane.
0002
Stability is guaranteed if at the frequency for which the phase angle of Aβ is 180° (i.e., ω180 ), |Aβ| is less than
PROBLEMS
Section 11.1: The General Feedback Structure 11.1 A negative-feedback amplifier has a closed-loop gain 4 Af = 200 and an open-loop gain A = 10 . What is the feedback factor β? If a manufacturing error results in a reduction of A 3 to 10 , what closed-loop gain results? What is the percentage change in Af corresponding to this factor of 10 reduction in A?
0002
Problems identified by the Multisim/PSpice icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion. Instructions to assist in setting up PSpice and Multisim simulations for all the indicated problems can be found in the corresponding files on the website. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
11.2 Consider the op-amp circuit shown in Fig. P11.2, where the op amp has infinite input resistance and zero output resistance but finite open-loop gain A.
0004
Computer Simulation Problems
Vs
A
0004 Vo
0004 0002
R2
0002
R1
Figure P11.2
0007 (a) Convince yourself that β = R1 / R1 + R2 . (b) If R1 = 10 k0004, find R2 that results in Af = 10 V/V for the following three cases: (i) A = 1000 V/V; (ii) A = 200 V/V; (iii) A = 15 V/V.
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Problems 897
0004 A 0002
Figure P11.3
11.4 In a particular circuit represented by the block diagram of Fig. 11.1, a signal of 1 V from the source results in a difference signal of 10 mV being provided to the amplifying element A, and 5 V appearing at the output. For this arrangement, identify the values of A and β that apply. 11.5 (a) Show that in a negative-feedback amplifier with loop gain Aβ 0003 1, the closed-loop gain Af is lower than its ideal value of 1/β by (100/Aβ)%. (b) What is the minimum loop gain required so that Af is within (i) 0.1%, (ii) 1%, and (iii) 5% of its ideal value? 11.6 In a particular amplifier design, the β network consists of a linear potentiometer for which β is 0.00 at one end, 1.00 at the other end, and 0.50 in the middle. As the potentiometer is adjusted, find the three values of closed-loop gain that result when the amplifier open-loop gain is (a) 1 V/V, (b) 10 V/V, (c) 100 V/V, (d) 1000 V/V, and (e) 10,000 V/V. Provide your results in a table in which there is a row for each value of A and a column for each value of β. 11.7 A newly constructed feedback amplifier undergoes a performance test with the following results: With the feedback connection removed, a source signal of 2 mV is required to provide a 5-V output; with the feedback connected, a 5-V output requires a 100-mV source signal. For this amplifier, identify values of A, β, Aβ, the closed-loop gain, and the amount of feedback (in dB).
11.9 The op amp in the circuit of Fig. P11.9 has an open-circuit voltage gain μ, a differential input resistance Rid , and a negligibly small output resistance. It is connected in the noninverting configuration with a feedback network consisting of a voltage divider (R1 , R2 ). While β is still determined by the divider ratio [i.e., β = R1 /(R1 + R2 )], the open-loop gain A is no longer simply equal to μ. This is because the feedback network now loads the input of the amplifier (because of the finite Rid ). To determine the value of A, use the method outlined in Section 11.1.3 to determine the loop gain Aβ. Thus show that
A=μ
Rid Rid + (R1 0006 R2 )
m
Vs R2
Vo
R1
Figure P11.9
Section 11.2: Some Properties of Negative Feedback 11.10 For the negative-feedback loop of Fig. 11.1, find the loop gain Aβ for which the sensitivity of closed-loop gain to open-loop gain [i.e., (dAf /Af )/(dA/A)] is –40 dB. For what value of Aβ does the sensitivity become 1/5?
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PROBLEMS
11.3 The noninverting buffer op-amp configuration shown in Fig. P11.3 provides a direct implementation of the feedback loop of Fig. 11.1. Assuming that the op amp has infinite input resistance and zero output resistance, what is β? If A = 1000, what is the closed-loop voltage gain? What is the amount of feedback (in dB)? For Vs = 1 V, find Vo and Vi . If A decreases by 10%, what is the corresponding percentage decrease in Af ?
D 11.8 An amplifier has an open-loop gain with a nominal value of 1000 but can vary from unit to unit by as much as ±50% of nominal. It is required to apply negative feedback to this amplifier so that the variability of the closed-loop gain of the resulting feedback amplifier is limited to ±1%. What is the largest possible nominal value of closed-loop gain that can be achieved? Now if three of these feedback amplifiers are placed in cascade, what is the nominal value of the gain of the resulting cascade amplifier? What is the expected variability of this gain?
CHAPTER 11
(c) For each of the three cases in (b), find the percentage change in Af that results when A decreases by 20%. Comment on the results.
CHAPTER 11
PROBLEMS
898 Chapter 11 Feedback D 11.11 A designer is considering two possible designs of a feedback amplifier. The ultimate goal is Af = 10 V/V. One design employs an amplifier for which A = 1000 V/V and the other uses A = 500 V/V. Find β and the desensitivity factor in both cases. If the A = 1000 amplifier units have a gain uncertainty of ±10%, what is the gain uncertainty for the closed-loop amplifiers utilizing this amplifier type? If the same result is to be achieved with the A = 500 amplifier, what is the maximum allowable uncertainty in its gain? D 11.12 A designer is required to achieve a closed-loop gain of 10 ± 0.1% V/V using a basic amplifier whose gain variation is ± 10%. What nominal value of A and β (assumed constant) are required? D 11.13 A circuit designer requires a gain of 25 ± 1% V/V using an amplifier whose gain varies by a factor of 10 over temperature and time. What is the lowest gain required? The value of β? (Hint: Since the change in the open-loop gain is very large, do not use differential analysis.) D 11.14 A power amplifier employs an output stage whose gain varies from 2 to 12 for various reasons. What is the gain of an ideal (nonvarying) amplifier connected to drive it so that an overall gain with feedback of 100 ± 5% V/V can be achieved? What is the value of β to be used? What are the requirements if Af must be held within ±0.5%? For each of these situations, what preamplifier gain and feedback factor β are required if Af is to be 10 V/V (with the two possible tolerances)? (Hint: Since the change in the open-loop gain is very large, do not use differential analysis.)
of β should be chosen? If component-value variation in the β network may produce as much as a ±1% variation in β, to what value must A be raised to ensure the required minimum gain? D 11.17 Design a feedback amplifier that has a closed-loop gain of 100 V/V and is relatively insensitive to change in basic-amplifier gain. In particular, it should provide a reduction in Af to 99 V/V for a reduction in A to one-tenth its nominal value. What is the required loop gain? What nominal value of A is required? What value of β should be used? What would the closed-loop gain become if A were increased tenfold? If A were made infinite? 11.18 Consider an amplifier having a midband gain AM and a low-frequency response characterized by a pole at s = −ωL and a zero at s = 0. Let the amplifier be connected in a negative-feedback loop with a feedback factor β. Find an expression for the midband gain and the lower 3-dB frequency of the closed-loop amplifier. By what factor have both changed? 11.19 A capacitively coupled amplifier has a midband gain of 1000 V/V, a single high-frequency pole at 10 kHz, and a single low-frequency pole at 100 Hz. Negative feedback is employed so that the midband gain is reduced to 10. What are the upper and lower 3-dB frequencies of the closed-loop gain?
D 11.15 It is required to design an amplifier with a gain of 100 that is accurate to within ±1%. You have available amplifier stages with a gain of 1000 that is accurate to within ±30%. Provide a design that uses a number of these gain stages in cascade, with each stage employing negative feedback of an appropriate amount. Obviously, your design should use the lowest possible number of stages while meeting specification.
D 11.20 Low-cost audio power amplifiers often avoid direct coupling of the loudspeaker to the output stage because any resulting dc bias current in the speaker can use up (and thereby waste) its limited mechanical dynamic range. Unfortunately, the coupling capacitor needed can be large! But feedback helps. For example, for an 8-0004 loudspeaker and fL = 100 Hz, what size capacitor is needed? Now, if feedback is arranged around the amplifier and the speaker so that a closed-loop gain Af = 10 V/V is obtained from an amplifier whose open-loop gain is 1000 V/V, what value of fLf results? If the ultimate product-design specification requires a 50-Hz cutoff, what capacitor can be used?
D *11.16 It is required to design an amplifier to have a nominal closed-loop gain of 10 V/V using a battery-operated amplifier whose gain reduces to half its normal full-battery value over the life of the battery. If only 2% drop in closed-loop gain is desired, what nominal open-loop amplifier gain must be used in the design? (Note that since the change in A is large, it is inaccurate to use differentials.) What value
D *11.21 It is required to design a dc amplifier with a low-frequency gain of 1000 and a 3-dB frequency of 1 MHz. You have available gain stages with a gain of 1000 but with a dominant high-frequency pole at 20 kHz. Provide a design that employs a number of such stages in cascade, each with negative feedback of an appropriate amount. Use identical stages.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 899
D 11.23 A feedback amplifier is to be designed using a feedback loop connected around a two-stage amplifier. The first stage is a direct-coupled, small-signal amplifier with a high upper 3-dB frequency. The second stage is a power-output stage with a midband gain of 10 V/V and upper and lower 3-dB frequencies of 8 kHz and 80 Hz, respectively. The feedback amplifier should have a midband gain of 100 V/V and an upper 3-dB frequency of 40 kHz. What is the required gain of the small-signal amplifier? What value of β should be used? What does the lower 3-dB frequency of the overall amplifier become? *11.24 The complementary BJT follower shown in Fig. P11.24(a) has the approximate transfer characteristic shown in Fig. P11.24(b). Observe that for −0.7 V ≤ v I ≤ +0.7 V, the output is zero. This “dead band” leads to crossover distortion (see Section 12.3). Consider this follower to be driven by the output of a differential amplifier of gain 100
V
1
0.7
0
0.7
vI
1
(b) Figure P11.24 continued
whose positive-input terminal is connected to the input signal source v S and whose negative-input terminal is connected to the emitters of the follower. Sketch the transfer characteristic v O versus v S of the resulting feedback amplifier. What are the limits of the dead band, and what are the gains outside the dead band? D 11.25 A particular amplifier has a nonlinear transfer characteristic that can be approximated as follows: 0005 0005 3 (a) For small input signals, 0005v I 0005 ≤ 10 mV, v O /0005v I 0005= 10 . 0005 0005 (b) For intermediate input signals, 10 mV ≤ v I ≤ 60 mV, 2 0005v O /0005v I = 10 . 0005 0005 (c) For large input signals, 0005v I 0005 ≥ 60 mV, the output saturates. If the amplifier is connected in a negative-feedback loop, find the feedback factor0005 β0005that reduces the factor-of-10 change in gain (occurring at 0005v I 0005 = 10 mV) to only a 10% change. What is the transfer characteristic v O versus v S of the amplifier with feedback?
Section 11.3: The Feedback Voltage Amplifier
vI
D 11.26 For the feedback voltage amplifier of Fig. 11.8(a), let the op amp have an infinite input resistance, a zero output resistance, and a finite open-loop gain of 1000 V/V. If R1 = 10 k0004, what value should R2 have to obtain an ideal closed-loop gain of 10? Now, calculate the loop gain Aβ and use it to find the actual value of the closed-loop gain Af . If Af is to be exactly 10, what must the value of R2 be?
vO
D 11.27 Consider the series–shunt feedback amplifier in Fig. 11.11(a), which is analyzed in Example 11.3.
V (a)
Figure P11.24
(a) If R1 = 10 k0004, find the value of R2 that results in an ideal closed-loop gain of 10.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
D 11.22 Design a supply-ripple-reduced power amplifier for which the output stage can be modeled by the block diagram of Fig. 11.5, where A1 = 0.9 V/V, and the power-supply ripple VN = ± 1 V. A closed-loop gain of 10 V/V is desired. What is the gain of the low-ripple preamplifier needed to reduce the output ripple to ±100 mV? To ±10 mV? To ±1 mV? For each case, specify the value required for the feedback factor β.
1 1
CHAPTER 11
vO
Hint: The 3-dB frequency of a cascade of N identical gain stages, each with a 3-dB frequency f3dB |stage is given by √ f3dB |cascade = f3dB |stage 21/N − 1
CHAPTER 11
PROBLEMS
900 Chapter 11 Feedback
0.1 mA Q2 R2
Q1
Vo
Rs R1
RL
1 mA
Vs Rin
Rout
Figure P11.29
(b) Use the expression for Aβ derived in Example 11.3 to find the value of the loop gain for the case μ = 1000, Rid = 100 k0004, ro = 1 k0004, Rs = 100 k0004, and RL = 10 k0004. Hence determine the value of the closed-loop gain Af . (c) By what factor must μ be increased to ensure that Af is within 1% of the ideal value of 10? D 11.28 Consider the series–shunt feedback amplifier of Fig. 11.8(b) that is analyzed in Example 11.2. (a) If R1 = 1 k0004, what value should R2 have to obtain a closed-loop gain whose ideal value is 5 V/V? (b) If gm1 = gm2 = 4 mA/V, RD1 = RD2 = 10 k0004, and the MOSFET’s ro is very large, use the expression for Aβ derived in Example 11.2 to find the value of Aβ and hence determine the closed-loop gain Af .
D 11.30 Consider the series–shunt feedback amplifier of Fig. 11.8(c), which was the subject of Exercise 11.6. Assume that the voltage divider (R1 , R2 ) is implemented with a 1-M0004 potentiometer. Assume that the MOSFET is biased so that gm = 4 mA/V and ro is large. Also, RD = 10 k0004. Find the value of R1 that results in a closed-loop gain of 5 V/V. D 11.31 Figure P11.31 shows a series–shunt feedback amplifier known as a “feedback triple.” All three MOSFETs are biased to operate at gm = 4 mA/V. You may neglect their ro ’s. (a) Select a value for RF that results in a closed-loop gain that is ideally 10 V/V.
*11.29 In the series–shunt feedback amplifier shown in Fig. P11.29, the devices operate with VBE = 0.7 V and have β1 = β2 = 100. The input signal Vs has a zero dc component. Resistances Rs = 100 0004, R1 = 1 k0004, R2 = 10 k0004, and RL = 1 k0004. (a) If the loop gain is large, what do you expect the closed-loop gain to be? Give both an expression and its value. (b) Find the dc emitter current in each of Q1 and Q2 . Also, find the dc voltage at the emitter of Q2 . (c) Calculate the value of the loop gain Aβ. (Hint: Set Vs = 0 and break the loop at the base of Q1 . Simplify the circuit by eliminating dc sources.) (d) Calculate the value of Af .
RD2 10 k RD1 10 k
Io Rout1 Q3
Q2 Q1
Vs
RF
RS1 100
Vo RS2 100 Rout2
Figure P11.31
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 901
11.32 Figure P11.32 shows a series–shunt feedback amplifier without details of the bias circuit.
D 11.33 The current-mirror-loaded differential amplifier in Fig. P11.33 has a feedback network consisting of the voltage divider (R1 , R2 ), with R1 + R2 = 1 M0004. The devices are sized to operate at |VOV | = 0.2 V. For all devices, |VA | = 10 V. The input signal source has a zero dc component.
RC 2 RC 1
Q3 Q2
Vs
(a) Find the loop gain Aβ and hence the value of A. (b) Find the values of R1 and R2 that result in a closed-loop gain of exactly 5 V/V.
Q1 Vo
Section 11.4: Systematic Analysis of Feedback Voltage Amplifiers (Series–Shunt)
RF RE
11.34 A series–shunt feedback amplifier employs a basic amplifier with input and output resistances each of 2 k0004 and gain A = 1000 V/V. The feedback factor β = 0.1 V/V. Find Figure P11.32
VDD
Q3
Q4
Vo R1 Rs Q1
Q2 Rout
Vs
R2 200 A
Figure P11.33
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
VCC
(a) If RE is selected to be 50 0004, find the value for RF that results in a closed-loop gain with an ideal value of 25 V/V. (b) If Q1 is biased at 1 mA, Q2 at 2 mA, and Q3 at 5 mA, and assuming that the transistors have hfe = 100 and large ro , and that RC1 = 2 k0004 and RC2 = 1 k0004, find the value of the loop gain Aβ and hence of the closed-loop gain Af .
CHAPTER 11
(b) Determine the loop gain Aβ and hence the value of Af . By what percentage does Af differ from the ideal value you designed for? How can you adjust the circuit to make Af equal to 10?
CHAPTER 11
PROBLEMS
902 Chapter 11 Feedback the gain Af , the input resistance Ri f , and the output resistance Rof of the closed-loop amplifier. 11.35 For a particular amplifier connected in a feedback loop in which the output voltage is sampled, measurement of the output resistance before and after the loop is connected shows a change by a factor of 200. Is the resistance with feedback higher or lower? What is the value of the loop gain Aβ ? If Rof is 100 0004, what is Ro without feedback? 11.36 The formulas for Ri f and Rof in Eqs. (11.20) and (11.23), respectively, also apply for the case in which A is a function of frequency. In this case, the resulting impedances Zi f and Zof will be functions of frequency. Consider the case of a series–shunt amplifier that has an input resistance Ri , an 0007
output resistance Ro , and open-loop gain A = A0 / 1 + s/ωH , and a feedback factor β that is independent of frequency. Find Zi f and Zof and give an equivalent circuit for each, together with the values of all the elements in the equivalent circuits. 11.37 A feedback amplifier utilizing voltage sampling and employing a basic voltage amplifier with a gain of 1000 V/V and an input resistance of 1000 0004 has a closed-loop input resistance of 10 k0004. What is the closed-loop gain? If the basic amplifier is used to implement a unity-gain voltage buffer, what input resistance do you expect? 11.38 Consider the noninverting op-amp circuit of Example 11.4 for the case R1 = ∞ and R2 = 0. (a) What is the value of β, and what is the ideal value of the closed-loop gain? (b) Adapt the expressions found in Example 11.4 to obtain expressions for A and Aβ for this case. 4 (c) For μ = 10 , Rid = 100 k0004, Rs = 10 k0004, ro = 1 k0004, and RL = 2 k0004, find A, Aβ, Af , Rin , and Rout . *11.39 This problem deals with the series–shunt feedback amplifier of Fig. P11.29 and overlaps somewhat with Problem 11.29. Thus, if you have already solved 11.29, you can use some of the results in the solution of this problem. The devices operate with VBE = 0.7 V and have β1 = β2 = 100. The input signal Vs has a zero dc component. Resistances Rs = 100 0004, R1 = 1 k0004, R2 = 10 k0004, and RL = 1 k0004. (a) If the loop gain is large, what do you expect the closed-loop gain Vo /Vs to be? Give both an expression and its approximate value.
(b) Find the dc emitter current in each of Q1 and Q2 . Also find the dc voltage at the emitter of Q2 . (c) Sketch the A circuit without the dc sources. Derive expressions for A, Ri , and Ro , and find their values. (d) Give an expression for β and find its value. (e) Find the closed-loop gain Vo /Vs , the input resistance Rin , and the output resistance Rout . By what percentage does the value of Af differ from the approximate value found in (a)? D *11.40 Figure P11.40 shows a series–shunt amplifier with a feedback factor β = 1. The amplifier is designed so that v O = 0 for v S = 0, with small deviations in v O from 0 V dc being minimized by the negative-feedback The 0005 action. 0005 0005 0005 2 0005 0005 technology utilized has k = 2k = 120 μA/V , V = 0.7 V, t n p 0005 00050005 and 0005VA 0005 = 24 V/μm. (a) Show that the feedback is negative. (b) With the feedback loop opened at the gate of Q2 , and the gate terminals of Q1 and Q2 grounded, find the dc current and the overdrive voltage at which each of Q1 to Q5 is operating. Ignore the Early effect. Also find the dc voltage at the output. (c) Find gm and ro of each of the five transistors. (d) Find expressions and values of A and Ro . Assume that the bias current sources are ideal. (e) Find the gain with feedback, Af , and the output resistance Rout . (f) How would you modify the circuit to realize a closed-loop voltage gain of 5 V/V? What is the value of output resistance obtained? *11.41 Figure P11.41 shows a series–shunt amplifier 0005 0005 in 0005VOV 0005 = which the 0005three MOSFETs are sized to operate at 0005 0005 0005 0.2 V. Let 0005Vt 0005 = 0.5 V and 0005VA 0005 = 10 V. The current sources utilize single transistors and thus have output resistances equal to ro . (a) Show that the feedback is negative. (b) Assuming the loop gain to be large, what do you expect the closed-loop voltage gain Vo /Vs to be approximately? (c) If Vs has a zero dc component, find the dc voltages at nodes S1 , G2 , S3 , and G3 . Verify that each of the current sources has the minimum required dc voltage across it for proper operation. (d) Find the A circuit. Calculate the gain of each of the three stages and the overall voltage gain, A.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 903
Q3 (40 1)
CHAPTER 11
2.5 V
Q4 (120 1) Q5 (20 1)
Q1 (20 1)
PROBLEMS
300 A
vO
Q2 (20 1)
vS
Rout
0.8 mA 200 A
2.5 V Figure P11.40
VDD I1
1.8 V
0.1 mA
Q2
G2
G3 Q1
I2
I3
S1
Vs
0.1 mA
Q3
S3
Vo
0.1 mA
R2
VDC
0.9 V
R1
18 k
Rout
2k
Figure P11.41
[Hint: A CS amplifier with a resistance Rs in the source 0007 lead has an effective transconductance gm / 1 + gm Rs and 0007 an output resistance ro 1 + gm Rs .] (e) Find β.
(f) Find Af = Vo /Vs . By what percentage does this value differ from the approximate value obtained in (b)? (g) Find the output resistance Rout .
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
904 Chapter 11 Feedback VDD
2.5 V
Q3
Q4 Q5
CHAPTER 11
80 k In
Q1
Q2
In Out
Out R1
Q7
Q6
Q8
VSS
In
100 k R2
2.5 V
(a)
(b)
Figure P11.43
D *11.42 This problem deals with the series–shunt feedback amplifier of Fig. P11.33. Certain aspects of this amplifier were considered in Problem 11.33. If you have already solved problem 11.33, you will have the opportunity to compare results. The current-mirror-loaded differential amplifier has 0007 a feedback network consisting of the voltage divider R1 , R2 , with 0005 0005 R1 + R2 = 1 M0004. The devices 0005 0005 are sized to operate at 0005VOV 0005 = 0.2 V. For all devices, 0005VA 0005 = 10 V. The input signal source has a zero dc component. (a) Show that the feedback is negative. (b) What do you expect the dc voltage at the gate of Q2 to be? At the output? (Neglect the Early effect.) (c) Find the A circuit. Derive an expression for A and find its value. (d) Select values for R1 and R2 to obtain a closed-loop voltage gain Vo /Vs = 5 V/V. (e) Find the value of Rout . (f) Utilizing the open-circuit, closed-loop gain (5 V/V) and the value of Rout found in (e), find the value of gain obtained when a resistance RL = 10 k0004 is connected to the output. (g) As an alternative approach to (f) above, redo the analysis of the A circuit including RL . Then utilize the values of
R1 and R2 found in (d) to determine β and Af . Compare the value of Af to that found in (f). D **11.43 The CMOS op amp in Fig. P11.43(a) is fabricated in a 1-μm technology for which Vtn = −Vtp = 0.75 V, μn Cox = 2 0005 2μp Cox = 100 μA/V , and VA = 10 V/μm. All transistors in the circuit have L = 1 μm. (a) It is required to perform a dc bias design of the circuit. For this purpose, let the two input terminals be at zero volts dc and neglect channel-length modulation (i.e., let VA = ∞). Design to obtain ID1 = ID2 = 50 μA, ID5 = 250 μA, and VO = 0, and operate all transistors except for the source follower Q5 at VOV = 0.25 V. Assume that Q1 and Q2 are perfectly matched, and similarly for Q3 and Q4 . For each transistor, find ID and W/L. (b) What is the allowable range of input common-mode voltage? (c) Find gm for each of Q1 , Q2 , and Q5 . (d) For each transistor, calculate ro . (e) The 100-k0004 potentiometer shown in Fig. 11.43(b) is connected between the output terminal (Out) and the inverting input terminal (–In) to provide negative
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 905
A1
A2
A3
Rout Vo
Vs R2
RL
PROBLEMS
Rin R1
Figure P11.45
feedback whose amount is controlled by the setting of the wiper. A voltage signal Vs is applied between the noninverting input (+In) and ground. A load resistance RL = 100 k0004 is connected between the output terminal and ground. The potentiometer is adjusted to obtain a closed-loop gain Af ≡ Vo /Vs 0004 10 V/V. Specify the required setting of the potentiometer by giving the values of R1 and R2 . Toward this end, find the A circuit (supply a circuit diagram), the value of A, the β circuit (supply a circuit diagram), and the value of β. (f) What is the output resistance of the feedback amplifier, excluding RL ?
D *11.44 Figure P11.32 shows a series–shunt feedback amplifier without details of the bias circuit. (a) Eliminating the dc sources, sketch the A circuit and the circuit for determining β. (b) Show that if Aβ is large then the closed-loop voltage gain is given approximately by Af ≡
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Rs
Vo R + RE 0004 F Vs RE
(c) If RE is selected equal to 50 0004, find RF that will result in a closed-loop gain of approximately 25 V/V. (d) If Q1 is biased at 1 mA, Q2 at 2 mA, and Q3 at 5 mA, and assuming that the transistors have hfe = 100, find approximate values for RC1 and RC2 to obtain gains from the stages of the A circuit as follows: a voltage gain of Q1 of about –10 and a voltage gain of Q2 of about –50.
(e) For your design, what is the closed-loop voltage gain realized? (f) Calculate the input and output resistances of the closed-loop amplifier designed. D *11.45 Figure P11.45 shows a three-stage feedback amplifier: A1 has an 82-k0004 differential input resistance, a 20-V/V open-circuit differential voltage gain, and a 3.2-k0004 output resistance. A2 has a 5-k0004 input resistance, a 20-mA/V short-circuit transconductance, and a 20-k0004 output resistance. A3 has a 20-k0004 input resistance, unity open-circuit voltage gain, and a 1-k0004 output resistance. The feedback amplifier feeds a 1-k0004 load resistance and is fed by a signal source with a 9-k0004 resistance. (a) Show that the feedback is negative. (b) If R1 = 20 k0004, find the value of R2 that results in a closed-loop gain Vo /Vs that is ideally 5 V/V. (c) Supply the small-signal equivalent circuit. (d) Sketch the A circuit and determine A. (e) Find β and the amount of feedback. (f) Find the closed-loop gain Af ≡ Vo /Vs . (g) Find the feedback amplifier’s input resistance Rin . (h) Find the feedback amplifier’s output resistance Rout . (i) If the high-frequency response of the open-loop gain A is dominated by a pole at 100 Hz, what is the upper 3-dB frequency of the closed-loop gain? (j) If for some reason A1 drops to half its nominal value, what is the percentage change in Af ?
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 11
PROBLEMS
906 Chapter 11 Feedback Section 11.5: Other Feedback-Amplifier Types D 11.46 Refer to the circuit in Fig. 11.17(a), which is analyzed in Example 11.6. Select a value for RF that results in a closed-loop transconductance Af ≡ Io /Vs 0004 10 mA/V. Use the formulas derived in Example 11.6 to find the actual value of Af realized. Let μ = 1000, Rid = 100 k0004, gm = 2 mA/V, and ro2 = 20 k0004. D 11.47 Figure P11.47 shows a feedback current amplifier. The feedback network consists of the highlighted two-port network comprising RM and RF . It is fed with the output current Io and delivers a feedback current If at its port 1 to the input node. The feedback factor β is the current ratio If /Io measured with port 1 short-circuited (because it is connected in shunt with the amplifier input). (a) Find an expression for β and hence for the ideal value of Af ≡ Io /Is . (b) Setting Is = 0, break the loop at the gate of Q2 and thus determine the loop gain Aβ. Show that A=−
VDD RD Q2 Io
Q1
VG RL
1
RF
Ii
Is
Vo
(a) If
RF
Vo
(b) Figure P11.48
(a) Show that the feedback factor β, determined as shown in Fig. P11.48(b), is given by β = −1/RF . Hence find the ideal value of the closed-loop gain Af ≡ Vo /Is . Find RF that results in Af of approximately 1 k0004. (b) By setting Is = 0 and breaking the loop at the input terminals of the op amp, show that the loop gain is given by Rid Aβ = μ Rid + RF + ro (c) For μ = 1000, Rid = 100 k0004, ro = 1 k0004, and RF having the value found in (a), what is the actual value of Af realized?
RF If
Is
If
gm2 RD 1 + 1/[gm1 (RM + RF )]
(c) For gm1 = gm2 = 4 mA/V, RD = 10 k0004, and (RM + RF ) = 1 k0004, find the value of RM that results in a closed-loop current gain of 5 A/A.
Ii
Assume that the op amp is modeled by an input resistance Rid , an open-circuit voltage gain μ, and an output resistance ro .
RM 2
Feedback Transconductance Amplifiers (Series–Series) Rin Figure P11.47
D 11.48 Figure P11.48(a) shows a feedback transresistance amplifier formed by an op amp and a feedback resistance RF .
11.49 A series–series feedback amplifier employs a transconductance amplifier having a short-circuit transconductance Gm of 0.6 A/V, input resistance of 10 k0004, and output resistance of 100 k0004. The feedback network has β = 200 0004,
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 907
(a) Determine β. (b) Find an approximate value for Af ≡ Ve3 /Vs assuming that the loop gain remains large (a safe assumption, since the loop in fact does not change). [Note: If you continue with the feedback analysis, you’ll find that Aβ in fact changes somewhat; this is a result of the different approximations made in the feedback analysis approach.] (c) If the loop gain remains at the value calculated in Example 11.8 (i.e., 246.3), find the output resistance Rout (measured between the emitter of Q3 and ground). (Neglect the effect of r03 .) D *11.51 Figure P11.31 (page 851) shows a feedback triple utilizing MOSFETs. All three MOSFETs are biased and sized to operate at gm = 4 mA/V. You may neglect their ro ’s (except for the calculation of Rout1 as indicated below). (a) Considering the feedback amplifier as a transconductance amplifier with output current Io , find the value of RF that results in a closed-loop transconductance of approximately 100 mA/V. (b) Sketch the A circuit and find the value of A ≡ Io /Vi . (c) Find 1 + Aβ and Af ≡ Io /Vs . Compare to the value of Af you designed for. What is the percentage difference? What resistance can you change to make Af exactly 100 mA/V, and in which direction (increase or decrease)? (d) Assuming that ro3 = 20 k0004, find Ro of the A circuit. For this purpose, recall that the resistance looking into the drain of a MOSFET having a resistance Rs in its source is (ro + Rs + gm ro Rs ). Hence find the output resistance Rout1 . Since the current sampled by the feedback network is exactly equal to the output current, you can use the feedback formula. (e) If the voltage Vo is taken as the output, in which case the amplifier becomes series–shunt feedback, what is
11.52 Consider the circuit in Fig. P11.52 as a transconductance amplifier with input Vs and output Io . The transistor is specified in terms of its gm and ro . (a) Sketch the small-signal equivalent circuit using the hybrid-π model of the MOSFET and convince yourself that the feedback circuit is comprised of resistor RF . (b) Find the A circuit and the β circuit. (c) Derive expressions for A, β, (1 + Aβ), Af , Ro , and Rof .
Io Rof
Vs
RF
Figure P11.52
D 11.53 The transconductance amplifier in Fig. P11.53 utilizes a differential amplifier with gain μ and a very high input resistance. The differential amplifier drives a transistor Q characterized by its gm and ro . A resistor RF senses the output current Io . (a) For Aβ 0003 1, find an approximate expression for the closed-loop transconductance Af ≡ Io /Vs . Hence, select a value for RF that results in Af 0004 5 mA/V. (b) Find the A circuit and derive an expression for A. Evaluate A for the case μ = 1000 V/V, gm = 2 mA/V, ro = 20 k0004, and the value of RF you selected in (a). (c) Give an expression for Aβ and evaluate its value and that of 1 + Aβ.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
11.50 Reconsider the circuit in Fig. 11.21(a), analyzed in Example 11.8, this time with the output voltage taken at the emitter of Q3 . In this case the feedback can be considered to be of the series–shunt type. Note that RE2 should now be considered part of the basic amplifier and not of the feedback network.
the value of the closed-loop voltage gain Vo /Vs ? Assume that RF has the original value you selected in (a). Note that in this case RS2 should be considered part of the amplifier and not the feedback network. The feedback analysis will reveal that Aβ changes somewhat, which may be puzzling given that the feedback loop did not change. The change is due to the different approximation used. (f) What is the closed-loop output resistance Rout2 of the voltage amplifier in (e) above?
CHAPTER 11
an input resistance (with port 1 open-circuited) of 200 0004, and an input resistance (with port 2 open-circuited) of 10 k0004. The amplifier operates with a signal source having a resistance of 10 k0004 and with a load resistance of 10 k0004. Find Af , Rin , and Rout .
(d) Find the closed-loop gain Af and compare to the value you designed for in (a) above. (e) Find expressions and values for Ro and Rof . [Hint: The resistance looking into the drain of a MOSFET with a resistance Rs in its source is (ro + Rs + gm ro Rs ).]
CHAPTER 11
PROBLEMS
908 Chapter 11 Feedback
Io Rof m
Q
Vs
the base, in the gm Vπ generator, and in ro , all in terms of Ix ? Show these currents on a sketch of the equivalent circuit with Re set to ∞. 11.55 As we found out in Example 11.8, whenever the feedback network senses the emitter current of the BJT, the feedback output resistance formula cannot predict the output resistance looking into the collector. To understand this issue more clearly, consider the feedback transconductance amplifier shown in Fig. P11.55(a). To determine the output resistance, we set Vs = 0 and apply a test voltage Vx to the collector, as shown in Fig. P11.55(b). Now, let μ be increased to the point where the feedback signal across RF almost equals the input to the positive terminal of the differential amplifier,
Rout
RF m Figure P11.53
Vs *11.54 It is required to show that the output resistance of the BJT circuit in Fig. P11.54 is given by 0002 0003
0007 rπ Ro = ro + Re 0006 rπ + Rb 1 + gm ro rπ + Rb
RF
(a) Rb Ro
Vs
Ix
Re Vx
m Figure P11.54
To derive this expression, set Vs = 0, replace the BJT with its small-signal, hybrid-π model, apply a test voltage Vx to the collector, and find the current Ix drawn from Vx and hence Ro as Vx /Ix . Note that the bias arrangement is not shown. For the case of Rb = 0, find the maximum possible value for Ro . Note that this theoretical maximum is obtained when Re is so large that the signal current in the emitter is nearly zero. In this case, with Vx applied and Vs = 0, what is the current in
0V 0
RF
(b) Figure P11.55
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 909
0007
Io Rout

Rout = rπ + hfe + 1 ro 0004 hfe ro
m
11.56 For the feedback transconductance amplifier of Fig. P11.56 derive expressions for A, β, Aβ, Af , Ro , and Rof . Evaluate Af and Rof for the case of gm1 = gm2 = 4 mA/V, RD = 20 k0004, ro2 = 20 k0004, RF = 100 0004, and RL = 1 k0004. For simplicity, neglect ro1 and take ro2 into account only when calculating output resistances.
RD Q2 Io Q1
RL
Vi
Vs
Vf
RF
Figure P11.56
D 11.57 For the feedback transconductance amplifier in Fig. P11.57, derive an approximate expression for the closed-loop transconductance Af ≡ Io /Vs for the case of Aβ 0003 1. Hence select a value for R2 to obtain Af = 100 mA/V. If Q is biased to obtain gm = 1 mA/V, specify the value of the gain μ of the differential amplifier to obtain an amount of feedback of 60 dB. If Q has ro = 50 k0004, find the output resistance Rout . [Hint: Recall that for a MOSFET with a resistance Rs in its source, the resistance looking into the drain is (ro + Rs + gm ro Rs ).]
R2
Vs R3 100
R1 100
Figure P11.57
11.58 All the MOS transistors in the feedback transconductance amplifier 0005 0005 (series–series) of Fig. P11.58 0005 0005are 0005VOV 0005 = 0.2 V. For all transistors, 0005Vt 0005 = sized to operate at 0005 0005 0.4 V and 0005VA 0005 = 20 V. (a) If Vs has a zero dc component, find the dc voltage at the output, at the drain of Q1 , and at the drain of Q2 . (b) Find an approximate expression and value for Af ≡ Io /Vs for the case Aβ 0003 1. (c) Use feedback analysis to obtain a more precise value for Af . (d) Find the value of Rout . (e) If the voltage at the source of Q5 is taken as the output, find the voltage gain using the value of Io /Vs obtained in (c). Also find the output resistance of this series–shunt voltage amplifier. 11.59 By setting Vs = 0 and breaking the feedback loop, show that the loop gain of the amplifier circuit in Fig. P11.58 is 0007 Aβ = gm1,2 ro2 0006 ro4 0007
RF 0006 ro5 RF 0006 ro5 + 1/gm5
where gm 1,2 is the gm of each of Q1 and Q2 .
Feedback Transresistance Amplifiers (Shunt–Shunt) 11.60 For the transresistance amplifier analyzed in Example 11.9, use the formulas derived there to evaluate Af , Rin , and Rout when μ is one-tenth the value used in the example. That is, 3 evaluate for μ = 10 V/V, Rid = ∞, ro = 100 0004, RF = 10 k0004, and Rs = RL = 1 k0004. Compare to the corresponding values obtained in Example 11.9.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
where hfe is the transistor β. Thus for large amounts of feedback, Rout is limited to a maximum of hfe ro independent of the amount of feedback. This phenomenon does not occur in the MOSFET version of this circuit, where the output resistance can be theoretically made infinite.
Q
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now zero. Thus the signal current through RF will be almost zero. By replacing the BJT with its hybrid-π model, show that
PROBLEMS
910 Chapter 11 Feedback
CHAPTER 11
Rout
Figure P11.58
11.61 Use the formulas derived in Example 11.9 to solve the problem in Exercise 11.19. Show that the results are identical to those given in the answer to Exercise 11.19. 11.62 By setting Is = 0, replacing the MOSFET with its hybrid-π model, and breaking the feedback loop, determine the loop gain of the feedback amplifier in Fig. E11.19. Hence find the open-loop gain. Evaluate Aβ, β, A, and Af for the numerical values given in Exercise 11.8. Why do the results differ somewhat from those given in the answer to Exercise 11.19?
(d) Find β and hence Aβ and 1 + Aβ. (e) Find Af , Ri f , and Rof and hence Rin and Rout . (f) What voltage gain Vo /Vs is realized? How does this value compare to the ideal value obtained if the loop gain is very large and thus the signal voltage at the base becomes almost zero (like what happens in an inverting op-amp circuit). Note that this single-transistor poor-man’s op amp is not that bad!
15 V
11.63 The CE BJT amplifier in Fig. P11.63 employs shunt–shunt feedback: Feedback resistor RF senses the output voltage Vo and provides a feedback current to the base node. (a) If Vs has a zero dc component, find the dc collector current of the BJT. Assume the transistor β = 100. (b) Find the small-signal equivalent circuit of the amplifier with the signal source represented by its Norton equivalent (as we usually do when the feedback connection at the input is shunt). (c) Find the A circuit and determine the value of A, Ri , and Ro .
RC Rf
5.6 k
56 k Vo
Rs
10 k Rout
Vs R in
Figure P11.63
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 911
VDD I Q2 Q1 Is
Vo I Rout
RF Rs 0004 0002
m
Vs
0004 0002
Rin
Vo
RF
Figure P11.65
Rout Rin
Figure P11.64
11.65 The feedback transresistance amplifier in Fig. P11.65 utilizes two identical MOSFETs biased by ideal current sources I = 0.4 mA. The MOSFETs are sized to operate at VOV = 0.2 V and have Vt = 0.5 V and VA = 16 V. The feedback resistance RF = 10 k0004. (a) If Is has a zero dc component, find the dc voltage at the input, at the drain of Q1 , and at the output. (b) Find gm and ro of Q1 and Q2 .
11.66 By setting Is = 0 and breaking the feedback loop, find the loop gain of the feedback amplifier in Fig. P11.65. If you have already solved Problem 11.65, compare results. Which result do you think is more accurate, and why? For the numerical values given in Problem 11.65, by how much (in percent) do the two values of loop gain differ?
11.67 Analyze the circuit in Fig. E11.19 from first principles (i.e., do not use the feedback approach) and hence show that 0002 0003 0007 1 0007 ro 0006 RF Rs 0006 RF gm − V RF 0002 0003 Af ≡ o = − 0007 1 0007 Is 1 + Rs 0006 RF gm − ro 0006 RF /RF RF
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
(a) If the loop gain is very large, what approximate closed-loop voltage gain Vo /Vs is realized? If Rs = 2 k0004, give the value of RF that will result in Vo /Vs 0004 − 10 V/V. 3 (b) If the amplifier μ has a dc gain of 10 V/V, an input resistance Rid = 100 k0004, and an output resistance ro = 2 k0004, find the actual Vo /Vs realized. Also find Rin and Rout (indicated on the circuit diagram). You may use formulas derived in Example 11.9. (c) If the amplifier μ has an upper 3-dB frequency of 1 kHz and a uniform −20-dB/decade 0005 gain 0005 rolloff, what is the 3-dB frequency of the gain 0005Vo /Vs 0005?
(c) Provide the A circuit and derive an expression for A in terms of gm1 , ro1 , gm2 , ro2 , and RF . (d) What is β? Give an expression for the loop gain Aβ and the amount of feedback (1 + Aβ). (e) Derive an expression for Af . (f) Derive expressions for Ri , Rin , Ro , and Rout . (g) Evaluate A, β, Aβ, Af , Ri , Ro , Rin , and Rout for the component values given.
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D 11.64 The circuit in Fig. P11.64 utilizes a voltage amplifier with gain μ in a shunt–shunt feedback topology with the feedback network composed of resistor RF . In order to be able to use the feedback equations, you should first convert the signal source to its Norton representation. You will then see that all the formulas derived in Example 11.9 apply here as well.
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PROBLEMS
912 Chapter 11 Feedback VCC
Comparing this expression to the one given in Exercise 11.19, part (b), you will note that the only difference is that gm has 0007 been replaced by gm − 1/RF . Note that −1/RF represents the forward transmission in the feedback network, which the feedback-analysis method neglects. What is the condition then for the feedback-analysis method to be reasonably accurate for this circuit? D 11.68 For the feedback amplifier in Fig. P11.68, select a value for RF that results in a closed-loop gain Af ≡ Vo /Is 0004 −10 k0004. Then, analyze the circuit to determine the actual value of Af realized. As well, determine Rin and Rout . Transistors Q1 and Q2 are operated so that gm1 = gm2 = 4 mA/V and ro1 and ro2 can be neglected. Also, RD1 = RD2 = 10 k0004.
RC Q2 Vo
Q1 Is
RE –VEE
RF
Rout
Rin Figure P11.69
VDD RD1
RD2 Vo Q2
Q1
VG RF
Rout
Is
Rin Figure P11.68
11.69 For the feedback transresistance amplifier in Fig. P11.69, let VCC = −VEE = 5 V, RC = RE = RF = 10 k0004. The transistors have VBE = 0.7 V and β = 100. (a) If Is has a zero dc component, show that Q1 and Q2 are operating at dc collector currents of approximately 0.35 mA and 0.58 mA, respectively. What is the dc voltage at the output?
(b) Find the A circuit and the value of A, Ri , and Ro . Neglect ro1 and ro2 . (c) Find the value of β, the loop gain, and the amount of feedback. (d) Find Af ≡ Vo /Is , the input resistance Rin , and the output resistance Rout .
D **11.70 (a) Show that for the circuit in Fig. P11.70(a), if the loop gain is large, the voltage gain Vo /Vs is given approximately by Rf Vo 0004− Vs Rs (b) Using three cascaded stages of the type shown in Fig. P11.70(b) to implement the amplifier μ, design a feedback amplifier with a voltage gain of approximately –100 V/V. The amplifier is to operate between a source resistance Rs = 10 k0004 and a load resistance RL = 1 k0004. Calculate the actual value of Vo /Vs realized, the input resistance (excluding Rs ), and the output resistance (excluding RL ). Assume that the BJTs have hfe of 100. [Note: In practice, the three amplifier stages are not made identical, for stability reasons.]
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 913
Rs
Vo RL
Vs Voltage amplifier
is not shown. It is required to derive expressions for Af ≡ Vo /Is , Rin , and Rout . Assume that C1 and C2 are sufficiently small that their loading effect on the basic amplifier can be neglected. Also neglect ro . Find the values of Af , Rin , and Rout for the case in which gm1 = 5 mA/V, RD = 10 k0004, C1 = 0.9 pF, C2 = 0.1 pF, and gmf = 2 mA/V.
PROBLEMS
(a) VDD 15 V RD 7.5 k
Vo
15 k Q1
VBIAS
C1
Rout
Qf
Is
10 k 4.7 k
C2 Rin
(b)
Figure P11.72
Figure P11.70
D 11.71 Negative feedback is to be used to modify the characteristics of a particular amplifier for various purposes. Identify the feedback topology to be used if: (a) input resistance is to be lowered and output resistance raised. (b) both input and output resistances are to be raised. (c) both input and output resistances are to be lowered.
11.72 The feedback amplifier of Fig. P11.72 consists of a common-gate amplifier formed by Q1 and RD , and a feedback circuit formed by the capacitive divider (C1 , C2 ) and the common-source transistor Qf . Note that the bias circuit for Qf
CHAPTER 11
Rf
D *11.73 Figure P11.73 shows a shunt–shunt feedback amplifier. The MOSFETs have Vtn = 0.6 V, VA = 20 V, and 2 μn Cox = 200 μA/V . The power supply VDD = 3.3 V, and RL = 2 k0004. The coupling capacitor CC can be assumed to be very large. (a) Perform a dc design to meet the following specifications: ID1 = 100 μA, ID2 = 1 mA, IR2, R1 = 10 μA, VOV 1 = VOV 2 = 0.2 V. Neglect the Early effect. Specify the values required for I1 , R1 , R2 , (W/L)1 , and (W/L)2 . (b) Find an expression for β and hence an expression for the ideal value of Vo /Vs . (c) Find the value of Rs that results in Vo /Vs being ideally −6 V/V.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
914 Chapter 11 Feedback VDD I1
CHAPTER 11
Q2 Q1
Rs
Vs
CC
R2 Vo
0004 0002
RL
R1 Rin
Rout
Figure P11.73
(d) Find the A circuit and use it to determine the values of A, Ri , and Ro . (e) Find the value obtained for Vo /Vs . (f) Find Rin and Rout .
Feedback Current Amplifiers (Shunt–Series) 11.74 For the feedback current amplifier in Fig. P11.47: (a) Provide the A circuit and derive expressions for Ri and A. Neglect ro of both transistors. (b) Provide the β circuit and an expression for β. (c) Find an expression for Aβ. (d) For gm1 = gm2 = 5 mA/V, RD = 20 k0004, RM = 10 k0004, and RF = 90 k0004, find the values of A, β, Aβ, Af , Ri , and Ri f . (e) If ro2 = 20 k0004 and RL = 1 k0004, find the output resistance as seen by RL . D 11.75 Design the feedback current amplifier of Fig. 11.27(a) to meet the following specifications: (i) Af ≡ Io /Is = −100 A/A (ii) amount of feedback 0004 40 dB (iii) Rin 0004 1 k0004 Specify the values of R1 , R2 , and μ. Assume that the amplifier μ has infinite input resistance and that Rs = ∞. For the
MOSFET, gm = 5 mA/V and ro = 20 k0004. What Rout is obtained?
11.76 Consider the feedback current amplifier in Fig. 11.27(a) (which was analyzed in Example 11.10). Let Rs = Rid = ∞. By setting Is = 0 and breaking the feedback loop at the gate of Q, find an expression for the loop gain Aβ. Evaluate Aβ for the component values given in Example 11.10 and hence determine A and Af . Why do the results differ somewhat from those found in Example 11.10?
11.77 The feedback current amplifier in Fig. P11.77 utilizes two identical NMOS transistors sized so that at ID = 0.2 mA they operate at VOV = 0.2 V. Both devices have Vt = 0.5 V and VA = 10 V. (a) If Is has zero dc component, show that both Q1 and Q2 are operating at ID = 0.2 mA. What is the dc voltage at the input? (b) Find gm and ro for each of Q1 and Q2 . (c) Find the A circuit and the value of Ri , A, and Ro . (d) Find the value of β. (e) Find Aβ and Af . (f) Find Rin and Rout .
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 915
0.2 mA
CHAPTER 11
I
Io
Io
Rout
Rout
m
Q2
Q2
Is R2 14 k
Is
Rs Rin
R1 3.5 k
(a)
Rin Figure P11.77
*11.78 The feedback current amplifier in Fig. P11.78(a) can be thought of as a “super” CG transistor. Note that rather than connecting the gate of Q2 to signal ground, an amplifier is placed between source and gate. (a) If μ is very large, what is the signal voltage at the input terminal? What is the input resistance? What is the current gain Io /Is ? (b) For finite μ but assuming that the input resistance of the amplifier μ is very large, find the A circuit and derive expressions for A, Ri , and Ro . (c) What is the value of β? (d) Find Aβ and Af . If μ is large, what is the value of Af ? (e) Find Rin and Rout assuming the loop gain is large. (f) The “super” CG transistor can be utilized in the cascode configuration shown in Fig. P11.78(b), where VG is a dc bias voltage. Replacing Q1 by its small-signal model, use the analogy of the resulting circuit to that in Fig. P11.78(a) to find Io and Rout .
PROBLEMS
Q1
Io Rout
VG
Q2
Q1
Vi
(b) Figure P11.78
Is Rin Io1
*11.79 Figure P11.79 shows an interesting and very useful application of feedback to improve the performance of the current mirror formed by Q1 and Q2 . Rather than connecting the drain of Q1 to the gate, as is the case in simple current mirrors, an amplifier of gain +μ is connected between the drain and the gate. Note that the feedback loop does not include transistor Q2 . The feedback loop ensures that the value of the gate-to-source voltage of Q1 is such that Io1 equals Is . This regulated Vgs is also applied to Q2 . Thus, if W/L of Q2
m
Q1
Rout Io2 Q2
VBIAS
Figure P11.79
is n times W/L of Q1 , Io2 = nIo1 = nIs . This current tracking, however, is not regulated by the feedback loop.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 11
PROBLEMS
916 Chapter 11 Feedback (a) Show that the feedback is negative. (b) If μ is very large and the input resistance of the amplifier μ is infinite, what dc voltage appears at the drain of Q1 ? If Q1 is to operate at an overdrive voltage of 0.2 V, what is the minimum value that VBIAS must have? (c) Replacing Q1 by its small-signal model, find an expression for the small-signal input resistance Rin assuming finite gain but infinite input resistance for the amplifier μ. Note that here it is much easier to do the analysis directly than to use the feedback-analysis approach. For large μ, what does Rin become? (d) What is the output resistance Rout ?
(a) If a resistance R is connected between y and ground, a voltage signal Vx is connected between x and ground, and z is short-circuited to ground. Find the current Iz through the short circuit. Show how this current is developed and its path for Vx positive and for Vx negative. (b) If x is connected to ground, a current source Iy is connected to input terminal y, and z is connected to ground, what voltage appears at y and what is the input resistance seen by Iy ? What is the current Iz that flows through the output short circuit? Also, explain the current flow through the circuit for Iy positive and for Iy negative. (c) What is the output resistance at z?
*11.80 The circuit in Fig. P11.80 is an implementation of a particular circuit building block known as second-generation current convoyer (CCII). It has three terminals besides ground: x, y, and z. The heart of the circuit is the feedback amplifier consisting of the differential amplifier μ and the complementary source follower (QN , QP ). (Note that this feedback circuit is one we have encountered a number of times in this chapter, albeit with only one source-follower transistor.) In the following, assume that the differential amplifier has a very large gain μ and infinite differential input resistance. Also, let the two current mirrors have unity current-transfer ratios.
*11.81 For the amplifier circuit in Fig. P11.81, assuming that Vs has a zero dc component, find the dc voltages at all nodes and the dc emitter currents of Q1 and Q2 . Let the BJTs have β = 100. Use feedback analysis to find Vo /Vs and Rin . Let VBE = 0.7 V.
Q1
15
μA
Vo
Q2
QN x y
m
z
Rin
QP
Figure P11.81
Q3
Figure P11.80
Q4
**11.82 Figure P11.82 shows a feedback amplifier utilizing the shunt–series topology. All transistors have β = 100 and VBE = 0.7 V. Neglect ro except in (f). (a) Perform a dc analysis to find the dc emitter currents in Q1 and Q2 and hence determine their small-signal parameters.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 917
RB 1
RC 1
100 k
RC2
10 k
8k
CHAPTER 11
12 V
Iout
Q2 Rs
10 k
RB 2
1k
RE 2 3.4 k
15 k 870
Rin
PROBLEMS
Iin
Vs
RL
Q1
Rout Rf
10 k
Figure P11.82
4
(b) Replacing the BJTs with their hybrid-π models, give the equivalent circuit of the feedback amplifier. (c) Give the A circuit and determine A, Ri , and Ro . Note that Ro is the resistance determined by breaking the emitter loop of Q2 and measuring the resistance between the terminals thus created. (d) Find the β circuit and determine the value of β. (e) Find Aβ, 1 + Aβ, Af , Ri f , and Rof . Note that Rof represents the resistance that in effect appears in the emitter of Q2 as a result of the feedback. (f) Determine Rin , Iout /Iin , and Rout . To determine Rout , use VA2 = 75 V and recall that the maximum possible output resistance looking into the collector of a BJT is approximately βro , where β is the BJT’s β (see Problem 11.55).
11.85 An op amp having a low-frequency gain of 10 3 and a single-pole rolloff at 10 rad/s is connected in a negative-feedback loop via a feedback network having a 3 transmission k and a two-pole rolloff at 10 rad/s. Find the value of k above which the closed-loop amplifier becomes unstable.
Section 11.7: The Stability Problem
Section 11.8: Effect of Feedback on the Amplifier Poles
11.83 An op amp designed to have a low-frequency gain 5 of 10 and a high-frequency response dominated by a single pole at 100 rad/s acquires, through a manufacturing error, a pair of additional poles at 20,000 rad/s. At what frequency does the total phase shift reach 180°? At this frequency, for what value of β, assumed to be frequency independent, does the loop gain reach a value of unity? What is the corresponding value of closed-loop gain at low frequencies? *11.84 For the situation described in Problem 11.83, sketch −3 Nyquist plots for β = 1.0 and 10 . (Plot for ω = 0 rad/s, 100 3 4 4 rad/s, 10 rad/s, 10 rad/s, 2 × 10 rad/s, and ∞ rad/s.)
11.86 Consider a feedback amplifier for which the open-loop gain A(s) is given by 10, 000 0007 2 1 + s/104 1 + s/105
A(s) = 0007
If the feedback factor β is independent of frequency, find the frequency at which the phase shift is 180°, and find the critical value of β at which oscillation will commence.
11.87 A dc amplifier having a single-pole response with pole frequency 10 Hz and unity-gain frequency of 1 MHz is operated in a loop whose frequency-independent feedback factor is 0.1. Find the low-frequency gain, the 3-dB frequency, and the unity-gain frequency of the closed-loop amplifier. By what factor does the pole shift? 11.88 An amplifier has dc open-loop gain of 80 dB and a single pole with 100-Hz frequency. It is utilized to design a feedback amplifier with a 3-dB frequency of 10 kHz. What β is needed? What is the dc closed-loop gain realized? Give an expression for Af (s).
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 11
PROBLEMS
918 Chapter 11 Feedback 4
*11.89 An amplifier having a low-frequency gain of 10 4 5 and poles at 10 Hz and 10 Hz is operated in a closed negative-feedback loop with a frequency-independent β. (a) For what value of β do the closed-loop poles become coincident? At what frequency? (b) What is the low-frequency, closed-loop gain corresponding to the situation in (a)? What is the value of the closed-loop gain at the frequency of the coincident poles? (c) What is the value of Q corresponding to the situation in (a)? (d) If β is increased by a factor of 10, what are the new pole locations? What is the corresponding pole Q? D 11.90 A dc amplifier has an open-loop gain of 1000 and two poles, a dominant one at 1 kHz and a high-frequency one whose location can be controlled. It is required to connect this amplifier in a negative-feedback loop that provides a dc closed-loop gain of 10 and a maximally flat response. Find the required value of β and the frequency at which the second pole should be placed. What is the 3-dB frequency of the closed-loop amplifier? 11.91 Reconsider Example 11.11 with the circuit in Fig. 11.34, modified to incorporate a so-called tapered network, in which the components immediately adjacent to the amplifier input are raised in impedance to C/10 and 10R. Find expressions for the resulting pole frequency ω0 and Q factor. For what value of K do the poles coincide? For what value of K does the response become maximally flat? For what value of K does the circuit oscillate? D 11.92 A feedback amplifier having a dc closed-loop gain of 10 and a maximally flat second-order response with a 3-dB frequency of 1 kHz is required. The open-loop amplifier utilizes a cascade of two identical amplifier stages, each having a single-pole frequency response. Find the values required for β, the 3-dB frequency, and the dc gain of each of the two amplifier stages. Give an expression for Af (s). 11.93 Three identical inverting amplifier stages, each characterized by a low-frequency gain K and a single-pole response with f3dB = 100 kHz, are connected in a feedback loop with β = 1. What is the minimum value of K at which the circuit oscillates? What would the frequency of oscillation be?
Section 11.9: Stability Study Using Bode Plots 11.94 Reconsider Exercise 11.26 for the case of the op amp wired as a unity-gain buffer. At what frequency is |Aβ| = 1? What is the corresponding phase margin? 11.95 Reconsider Exercise 11.26 for the case of a manufac3 turing error introducing a second pole at 10 Hz. What is now the frequency for which |Aβ| = 1? What is the corresponding phase margin? For what values of β is the phase margin 45° or more? 11.96 For what phase margin does the gain peaking have a value of 5%? Of 10%? Of 0.1 dB? Of 1 dB? Of 3 dB? [Hint: Use the result in Eq. (11.82).] 4
5
11.97 An amplifier has a dc gain of 10 and poles at 10 Hz, 5 6 3.16 × 10 Hz, and 10 Hz. Find the value of β, and the corresponding closed-loop gain, for which a phase margin of 45° is obtained. 3
11.98 A two-pole amplifier for which A0 = 10 and having poles at 1 MHz and 10 MHz is to be connected as a differentiator. On the basis of the rate-of-closure rule, what is the smallest differentiator time constant for which operation is stable? What are the corresponding gain and phase margins? 11.99 For the amplifier described by Fig. 11.37 and with frequency-independent feedback, what is the minimum closed-loop voltage gain that can be obtained for phase margins of 90° and 45°?
Section 11.10: Frequency Compensation D 11.100 A multipole amplifier having a first pole at 1 MHz and a dc open-loop gain of 80 dB is to be compensated for closed-loop gains as low as unity by the introduction of a new dominant pole. At what frequency must the new pole be placed? D 11.101 For the amplifier described in Problem 11.100, rather than introducing a new dominant pole we can use additional capacitance at the circuit node at which the pole is formed to reduce the frequency of the first pole. If the frequency of the second pole is 20 MHz and if it remains unchanged while additional capacitance is introduced as
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 919
11.102 For the amplifier whose A(s) is depicted in Fig. 11.38, to what value must the first pole frequency be lowered to obtain stable performance for (a) β = 0.001 and (b) β = 0.1? 11.103 Contemplate the effects of pole splitting by considering Eqs. (11.89), (11.93), and (11.94) under the conditions that R1 0004 R2 = R, C2 0004 C1 /10 = C, Cf 0003 C, and gm = 100/R, 0005 0005 by calculating ωP1 , ωP2 , and ωP1 , ωP2 . Comment on the results.
**11.106 The op amp in the circuit of Fig. P11.106 5 has an open-loop gain of 10 and a single-pole rolloff with ω 3dB = 10 rad/s.
5
D 11.104 An op amp with open-loop voltage gain of 10 and 6 7 8 poles at 10 Hz, 10 Hz, and 10 Hz is to be compensated by the addition of a fourth dominant pole to operate stably with unity feedback (β = 1). What is the frequency of the required dominant pole? The compensation network is to consist of an RC low-pass network placed in the negative-feedback path of the op amp. The dc bias conditions are such that a 1-M0004 resistor can be tolerated in series with each of the negative and positive input terminals. What capacitor is required between the negative input and ground to implement the required fourth pole? D *11.105 An op amp with an open-loop voltage gain of 5 6 6 80 dB and poles at 10 Hz, 10 Hz, and 2 × 10 Hz is to be compensated to be stable for unity β. Assume that the op amp incorporates an amplifier equivalent to that in Fig. 11.40,
(a) Sketch a Bode plot for the loop gain. (b) Find the frequency at which |Aβ| = 1, and find the corresponding phase margin. (c) Find the closed-loop transfer function, including its zero and poles. Sketch a pole-zero plot. Sketch the magnitude of the transfer function versus frequency, and label the important parameters on your sketch.
0004 0002
0006
Figure P11.106
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PROBLEMS
with C1 = 150 pF, C2 = 5 pF, and gm = 40 mA/V, and that fP1 is caused by the input circuit and fP2 by the output circuit of this amplifier. Find the required value of the compensating Miller capacitance and the new frequency of the output pole.
CHAPTER 11
mentioned, find the frequency to which the first pole must be lowered so that the resulting amplifier is stable for closed-loop gains as low as unity. By what factor is the capacitance at the controlling node increased?
PROBLEMS Computer Simulation Problems Problems identified by the Multisim/PSpice icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion. Instructions to assist in setting up PSpice and Multisim simulations for all the indicated problems can be found in the corresponding files on the website. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
Section 12.2: Class A Output Stage 12.1 A class A emitter follower, biased using the circuit shown in Fig. 12.2, uses VCC = 10 V, R = RL = 1 k0003, with all transistors (including Q3 ) identical. Assume VBE = 0.7 V, VCE sat = 0.3 V, and β to be very large. For linear operation, what are the upper and lower limits of output voltage, and the corresponding inputs? How do these values change if the emitter–base junction area of Q3 is made twice as big as that of Q2 ? Half as big? 12.2 A source-follower circuit using NMOS transistors is constructed following the pattern shown in Fig. 12.2. All three transistors used are identical, with Vt = 0.5 V and μn Cox W/L = 2 20 mA/V ; VCC = 2.5 V, R = RL = 1 k0003. For linear operation, what are the upper and lower limits of the output voltage, and the corresponding inputs? D 12.3 Using the follower configuration shown in Fig. 12.2 with ± 5-V supplies, provide a design capable of ±3-V outputs with a 1-k0003 load, using the smallest possible total supply current. You are provided with four identical, high-β BJTs and a resistor of your choice. Select a standard resistor value of 5% tolerance, and specify the maximum power drawn from the negative supply. D 12.4 An emitter follower using the circuit of Fig. 12.2, for which the output voltage range is ±5 V, is required using VCC = 10 V. The circuit is to be designed such that the current variation in the emitter-follower transistor is no greater than a factor of 15, for load resistances as low as 100 0003. What is the value of R required? Find the incremental voltage gain of the resulting follower at v O = +5, 0, and –5 V, with a 100-0003 load. What is the percentage change in gain over this range of v O ?
*12.5 Consider the operation of the follower circuit of Fig. 12.2 for which RL = VCC /I, when driven by a square wave such that the output ranges from +VCC to −VCC (ignoring VCE sat ). For this situation, sketch the equivalent of Fig. 12.4 for v O , iC 1 , and pD 1 . Repeat for a square-wave output that has peak levels of ±VCC /2. What is the average power dissipation in Q1 in each case? Compare these results to those for sine waves of peak amplitude VCC and VCC /2, respectively. 12.6 Consider the situation described in Problem 12.5. For square-wave outputs having ±VCC levels and ± 21 VCC levels, and for sine waves of the same peak-to-peak values, find the average power loss in the current-source transistor Q2 . 12.7 Reconsider the situation described in Exercise 12.3 for variation in VCC —specifically for VCC = 16 V, 12 V, 10 V, and 8 V. Assume VCE sat is nearly zero. What is the power-conversion efficiency in each case? D 12.8 The emitter-follower output stage of Fig. 12.2 is designed to provide a maximum output swing of ±Vˆ volts, across the load RL . Neglecting the saturation voltage, what are the minimum required values of VCC and I? Now, if the output voltage is a sine wave of peak amplitude (Vˆ /2), what is the power-conversion efficiency realized?
Section 12.3: Class B Output Stage 12.9 Consider the circuit of a complementary-BJT class B output stage. For what amplitude of input signal does the crossover distortion represent a 10% loss in peak amplitude? 12.10 Consider the feedback configuration with a class B output stage shown in Fig. 12.9. Let the amplifier gain A0 = 100 0004 0004V/V. Derive an expression for v O versus v I , assuming that 0004VBE 0004 = 0.7 V. Sketch the transfer characteristic v O versus v I , and compare it with that without feedback. 12.11 Consider the class B output stage, 0004using 0004 MOSFETs, shown in Fig. P12.11. Let the devices have 0004Vt 0004 = 2 0.5 V and μCox W/L = 2 mA/V . With a 10-kHz sine-wave input of 5-V peak and a high value of load resistance, what peak output would you expect? What fraction of the sine-wave period does the crossover interval represent? For what value of load resistor is the peak output voltage reduced to half the input?
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PROBLEMS
984 Chapter 12 Output Stages and Power Amplifiers ⫹5 V
⫺5 V
RL and employing power supplies ±VSS . Neglecting the effects of finite VBE and VCE sat , determine the load power, the supply power, the power-conversion efficiency, the maximum attainable power-conversion efficiency and the corresponding value of Vˆ o , and the maximum available load power. Also find the value of Vˆ o at which the power dissipation in the transistors reaches its peak, and the corresponding value of power-conversion efficiency. 12.16 Sketch a graph for the small-signal voltage gain of the class B circuit of Fig. 12.5 as a function of vI , for vI both positive and negative.
Figure P12.11
Section 12.4: Class AB Output Stage
12.12 Consider the complementary-BJT class B output stage and neglect the effects of finite VBE and VCE sat . For ±10-V power supplies and an 8-0003 load resistance, what is the maximum sine-wave output power available? What supply power corresponds? What is the power-conversion efficiency? For output signals of half this amplitude, find the output power, the supply power, and the power-conversion efficiency.
12.17 A class AB output stage, such as that in Fig. 12.11, −14 utilizing transistors with IS = 10 A, is biased at a quiescent current IQ = 1 mA. Find VBB , the output resistance Rout at vI = 0, and the corresponding small-signal voltage gain. The load resistance RL = 100 0003. What does the incremental gain become when vO = 10 V?
D 12.13 A class B output stage operates from ±10-V supplies. Assuming relatively ideal transistors, what is the output voltage for maximum power-conversion efficiency? What is the output voltage for maximum device dissipation? If each of the output devices is individually rated for 2-W dissipation, and a factor-of-2 safety margin is to be used, what is the smallest value of load resistance that can be tolerated, if operation is always at full output voltage? If operation is allowed at half the full output voltage, what is the smallest load permitted? What is the greatest possible output power available in each case? D 12.14 A class B output stage is required to deliver an average power of 50 W into an 8-0003 load. The power supply should be 4 V greater than the corresponding peak sine-wave output voltage. Determine the power-supply voltage required (to the nearest volt in the appropriate direction), the peak current from each supply, the total supply power, and the power-conversion efficiency. Also, determine the maximum possible power dissipation in each transistor for a sine-wave input. 12.15 Consider the class B BJT output stage with a square-wave output voltage of amplitude Vˆ o across a load
D 12.18 Design the quiescent current of a class AB BJT output stage so that the incremental voltage gain for v I in the vicinity of the origin is in excess of 0.97 V/V for loads larger than 100 0003. Assume that the BJTs have VBE of 0.7 V at a current of 100 mA and determine the value of VBB required. D 12.19 A class AB output stage, such as that in Fig. 12.11, drives a load resistance RL of 100 0003. What bias current IQ will serve to limit the variation in the small-signal voltage gain to 5% as iL changes from 0 to 50 mA? 12.20 For the class AB output stage considered in Example 12.3, add two columns to the table of results as follows: the total input current drawn from v I ( iI , mA); and the large-signal input resistance Rin ≡ v I /iI . Assume βN = βP = β = 49. Compare the values of Rin to the approximate value obtained using the resistance-reflection rule, Rin 0003 βRL . 12.21 In this problem we investigate an important trade-off in the design of the class AB output stage of Fig. 12.11: Increasing the quiescent current IQ reduces the nonlinearity of the transfer characteristic at the expense of increased quiescent power dissipation. As a measure of nonlinearity, we use the maximum deviation of the stage incremental gain, which occurs at v O = 0, namely, 0004 e = 1 − v o /v i 0004v =0
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O
Problems 985
VT /2IQ 0003 0002 RL + VT /2IQ
which for 2IQ RL VT can be approximated by e 0003 VT /2IQ RL (b) If the stage is operated from power supplies of ±VCC , find the quiescent power dissipation, PD . (c) Show that for given VCC and RL , the product of the quiescent power dissipation and the gain error is a constant given by
VCC ePD 0003 VT RL (d) For VCC = 10 V and RL = 100 0003, find the required values of PD and IQ if e is to be 5%, 2%, and 1%. *12.22 A class AB output stage, resembling that in Fig. 12.11 but utilizing a single supply of +10 V and biased at VI = 6 V, is capacitively 0004 0004 coupled to a 100-0003 load. For transistors for which 0004VBE 0004 = 0.7 V at 1 mA and for a bias voltage VBB = 1.4 V, what quiescent current results? For a step change in output from 0 to –1 V, what input step is required? Assuming transistor-saturation voltages of zero, find the largest possible positive-going and negative-going steps at the output.
RL vo = vi RL + (reN reP )
PROBLEMS
e=
output stage in Fig. 12.14. To simplify matters, assume the small-signal resistances of D1 and D2 to be negligibly small. Replace each of QN and QP with its hybrid-π model and neglect ro . Hence show that the class AB stage is equivalent, from a small-signal point of view, to an emitter-follower transistor whose rπ = rπ N rπ P and gm = gmN + gmP , and hence re = reN reP and β = (gmN + gmP )(rπ N rπ P ). Now show that
CHAPTER 12
(a) Show that e is given by
and Rin 0003 β[RL + (reN reP )] 12.26 Figure P12.26 shows a class AB output stage with a common-emitter transistor added to increase the voltage gain and reduce the current that vI has to supply. Neglecting the small-signal resistances of D1 and D2 , find the small-signal voltage gain vo /vi . (Hint: Use the expressions for voltage gain and input resistance of the class AB stage without Q3 , given in the statement for Problem 12.25.)
⫹VCC IBIAS
Section 12.5: Biasing the Class AB Circuit
QN
D 12.23 Consider the diode-biased class AB circuit of Fig. 12.14. For IBIAS = 200 μA, find the relative size (n) that should be used for the output devices (in comparison to the biasing devices) to ensure that an output resistance of 8 0003 or less is obtained in the quiescent state. Neglect the resistance of the biasing diodes. D*12.24 A class AB output stage using a two-diode bias network as shown in Fig. 12.14 utilizes diodes having the same junction area as the output transistors. For 0004 0004 VCC = 10 V, IBIAS = 1 mA, RL = 100 0003, β N = 50, and 0004VCEsat 0004 = 0 V, what is the quiescent current? What are the largest possible positive and negative output signal levels? To achieve a positive peak output level equal to the negative peak level, what value of β N is needed if IBIAS is not changed? What value of IBIAS is needed if β N is held at 50? For this value, what does IQ become? D 12.25 It is required to evaluate the small-signal input resistance and small-signal voltage gain of the class AB
D1 vO D2
RL QP
vI
Q3 ⫺VCC
Figure P12.26
12.27 It is required to find an expression for the output resistance Rout of the class AB output stage in Fig. P12.26. Toward that end, neglect the small-signal resistance of each of D1 and D2 and assume the current source supplying IBIAS has an
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PROBLEMS
986 Chapter 12 Output Stages and Power Amplifiers output resistance RBIAS . Transistors QN and QP are equivalent to a single transistor with rπ = rπ N rπ P , re = reN reP , and gm = gmN + gmP . **12.28 A class AB output stage using a two-diode bias network as shown in Fig. 12.14 utilizes diodes having the same junction area as the output transistors. At a room temperature of about 20°C the quiescent current is 1 mA and 0004 0004 0004VBE 0004 = 0.6 V. Through a manufacturing error, the thermal coupling between the output transistors and the biasing diode-connected transistors is omitted. After some output activity, the output devices heat up to 70°C while the biasing devices remain at 20°C. Thus, while the VBE of each device remains unchanged, the quiescent current in the output devices increases. To calculate the new current value, recall that there are two effects: IS increases by about 14%/°C and VT = kT /q changes, where T = 273° + temperature in °C, and VT = 25 mV only at 20°C. However, you may assume that β N remains almost constant. This assumption is based on the fact that β increases with temperature but decreases with current. What is the new value of IQ ? If the power supply is ±20 V, what additional power is dissipated? If thermal runaway occurs, and the temperature of the output transistors increases by 10°C for every watt of additional power dissipation, what additional temperature rise and current increase result? D 12.29 Repeat Example 12.5 for the situation in which the peak positive output current is 250 mA. Use the same general approach to safety margins. What are the values of R1 and R2 you have chosen? **12.30 A VBE multiplier is designed with equal resistances for nominal operation at a terminal current of 1 mA, with half the current flowing in the bias network. The initial design is based on β = ∞ and VBE = 0.7 V at 1 mA. (a) Find the required resistor values and the terminal voltage. (b) Find the terminal voltage that results when the terminal current increases to 2 mA. Assume β = ∞. (c) Repeat (b) for the case the terminal current becomes 10 mA. (d) Repeat (c) using the more realistic value of β = 100. *12.31 By replacing the transistor in the VBE multiplier by its hybrid-π, small-signal model (with ro neglected), show that the incremental resistance between the two terminals of the multiplier is given by
r=
R2 + (R1 rπ ) 1 + gm (R1 rπ )
Evaluate r for the case R1 = R2 = 1.2 k0003, with the transistor operating at IC = 1 mA and having β = 100.
Section 12.6: Variations on the Class AB Configuration 12.32 Use the results given in the answer to Exercise 12.9 to determine the input current of the circuit in Fig. 12.17 for v I = 0 and ±10 V with infinite and 100-0003 loads. 12.33 For the circuit in Fig 12.17, operated near v I = 0 and fed with a signal source having zero resistance, show that the output resistance is given by Rout =
00030002 0002 00030016 10015 R + re3 + R1 re1 / β3 + 1 2 3
Assume that the top and bottom halves of the circuit are perfectly matched. D ***12.34 Consider the circuit of Fig. 12.17 in which Q1 and Q2 are matched, and Q3 and Q4 are matched but have three times the junction area of the others. Resistors R3 and R4 also are matched. For VCC = 10 V, find values for resistors R1 through R4 that allow for a base current of at least 10 mA in Q3 (and Q4 ) at v I = +5 V (vI = −5 V), when a load demands it, with at most a 2-to-1 variation in currents in Q1 (and Q2 ). The quiescent current in Q3 is to be 40 mA. Let β1,2 ≥ 150 and β3,4 ≥ 50. For input voltages around 0 V, estimate the output resistance of the overall follower driven by a source having zero resistance. For an input voltage of +1 V and a load resistance 0004 0004 of 2 0003, what output voltage results? Q1 and Q2 have 0004VBE 0004 of 0.7 V at a current of 10 mA. 12.35 Figure P12.35 shows a variant of the class AB circuit of Fig. 12.17. Assume that all four transistors are matched and have β = 100. (a) For v I = 0, find the quiescent current in Q3 and Q4 , the input current iI , and the output voltage v O . (b) Since the circuit has perfect symmetry, the small-signal performance around v I = 0 can be determined by considering either the top or bottom half of the circuit only. In this case, the load on the half-circuit must be 2RL , the input resistance found is 2Rin , and the output resistance
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Problems 987
(b) Find the small-signal current ic that results from an input signal v i , and hence find the voltage gain v o /v i . (c) Find the input resistance Rin .
⫹5 V
⫹VCC
2 M⍀
Q3 Q1 iI vI
vo
⬁
⫺VCC
vO
⫹VCC
RL ⫽ 200 ⍀
Q2
ic
Q1
vi
Q2 Rin
Q4
Figure P12.37 1 mA
⫺VCC
Figure P12.35
12.36 For the Darlington configuration shown in Fig. 12.18, show that for β1 1 and β2 1: (a) The equivalent composite transistor has β 0003 β1 β2 . (b) If the composite transistor is operated at a current IC , then Q2 will be operating at a collector current approximately equal to IC , and Q1 will be operating at a collector current approximately equal to IC /β2 . (c) The composite transistor has a base–emitter voltage 0003 0002 0002 0003 VBE 0003 2VT ln IC /IS − VT ln β2 , where IS is the saturation current of each of Q1 and Q2 . (d) The composite transistor has an equivalent rπ 0003 0002 0003 2β1 β2 VT /IC . (e) The composite transistor has an equivalent gm 0003 0002 0003 1 I /VT . 2 C
**12.38 The0004 BJTs 0004 in the circuit 0004 of 0004 Fig. P12.38 have β P = 10, β N = 100, 0004VBE 0004 = 0.7 V, and 0004VA 0004 = 100 V. (a) Find the dc collector current of each transistor and the value of VC . (b) Replacing each BJT with its hybrid-π model, show that 0015 0016 vo 0003 gm1 ro1 β N (ro2 Rf )
vi
(c) Find the values of v o /v i and Rin .
*12.37 For the circuit in Fig. P12.37 in which the transistors have VBE = 0.7 V and β = 100: (a) Find the dc collector current for each of Q1 and Q2 .
Figure P12.38
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PROBLEMS
2 k⍀ ⬁
1 mA
CHAPTER 12
found is 2Rout . Using this approach, find Rin , v o /v i , and Rout (assuming that the circuit is fed with a zero-resistance source).
CHAPTER 12
PROBLEMS
988 Chapter 12 Output Stages and Power Amplifiers D **12.39 Consider the compound-transistor class AB output stage shown in Fig. 12.20 in which Q2 and Q4 are matched transistors with VBE = 0.7 V at 10 mA and β = 100, Q1 and Q5 have VBE = 0.7 V at 1-mA currents and β = 100, and Q3 has VEB = 0.7 V at a 1-mA current and β = 10. Design the circuit for a quiescent current of 2 mA in Q2 and Q4 , IBIAS that is 100 times the standby base current in Q1 , and a current in Q5 that is nine times that in the associated resistors. Find the values of the input voltage required to produce outputs of ±10 V for a 1-k0003 load. Use VCC of 15 V. *12.40 Figure P12.40 shows a variant on the class AB amplifier known as class G. Here, in addition to the
the threshold value, Q3 is turned off and D1 turns on, thus connecting Q1 to its normal supply VCC1 . A similar process happens in the negative direction, with D2 and Q4 taking the place of D1 and Q3 . Let VCC1 = 35 V, VCC2 = 70 V, VZ1 = 3.3 V, and the voltage of the VBE multiplier VBB = 1.2 V. (a) Find the positive threshold value of vI at which Q3 is turned on. (b) If for 95% of the time vI is in the vicinity of 30 V and only 5% of the time it is in the vicinity of 65 V, use Eq. (12.19) to estimate the average power dissipated in the transistors, PD . Compare to the value of PD dissipated in a class AB stage operated from a ±70 V supply. 12.41 Repeat Exercise 12.11 for a design variation in which transistor Q5 is increased in size by a factor of 20, all other conditions remaining the same.
VCC2 IBIAS Q3 VCC1 Z1
12.42 Repeat Exercise 12.11 for a design in which the limiting output current and normal peak current are 100 mA and 75 mA, respectively. D 12.43 The circuit shown in Fig. P12.43 operates in a manner analogous to that in Fig. 12.21 to limit the output
D1 Q1 R2 Q5
vO
R1
RL Q2
vI Z2
D2 Q4
–VCC1 IBIAS
IBIAS ⫺VCC2 Figure P12.40
normal power supply ±VCC1 , the circuit is equipped with a higher voltage supply ±VCC2 . The latter supply is utilized only infrequently. The circuit operates as follows. Normally, D1 and D2 are turned on and thus connect the ±VCC1 supply to the class AB stage transistors Q1 and Q2 . Simultaneously, Q3 and Q4 are off. For vI positive and exceeding a certain threshold, Q3 turns on, D1 turns off, and Q1 is then effectively operating from the higher voltage supply VCC2 . This continues as long as vI is larger than the specified threshold. As vI decreases below
Figure P12.43
current from Q3 in the event of a short circuit or other mishap. It has the advantage that the current-sensing resistor R does
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Problems 989
Section 12.7: CMOS Class AB Output Stages D 12.45 (a) Show that for the class AB circuit in Fig. 12.23, the small-signal output resistance in the quiescent state is given by Rout 0003
1 gmn + gmp
which for matched devices becomes 1 Rout = 2gm
0004 0004 (b) For a circuit that utilizes MOSFETs with 0004Vt 0004 = 0.5 V and 2 k (W/L) = 200 mA/V , find the voltage VGG that results in Rout = 20 0003. Also, find IQ . D 12.46 (a) For the circuit in Fig. 12.23 in which Q1 and Q2 are matched, QN and QP are matched, and all devices have the same |Vt |, show that the small-signal voltage gain at the quiescent condition is given by RL vo 0003 0002 = v i RL + 2/gm where gm is the transconductance of each of QN and QP and where channel-length modulation is neglected. (b) For the case IBIAS = 0.2 mA, RL = 1 k0003, kn = kp = nk1 = 2 nk2 , where k = μCox (W/L), and k1 = 20 mA/V , find the ratio n that results in an incremental gain of 0.98. Also find the quiescent current IQ . D 12.47 Design the circuit of Fig. 12.23 to operate at IQ 2 = 1 mA with IBIAS = 0.1 mA. Let μn Cox = 250 μA/V , 2 μp Cox = 100 μA/V , Vtn = − Vtp = 0.45 V, and VDD = VSS = 2.5 V. Design so that Q1 and Q2 are matched and QN and QP are matched, and that in the quiescent state each operates at an overdrive voltage of 0.15 V.
D 12.48 Consider the design of the class AB output stage of Fig. 12.23 for the following conditions. The stage is operated from ±2.5-V power supplies and is required to provide a minimum output voltage swing of ±1.5 V while supplying a maximum current equal to 10 times the quiescent current IQ . Assume that QN and QP are matched and Q1 and Q2 are matched, that all devices have |Vt | = 0.5 V, and that in the quiescent state all transistors are operated at the same overdrive voltage. What is the value of VOV required, and what VGG is needed?
PROBLEMS
D 12.44 Consider the thermal shutdown circuit shown in Fig. 12.22. At 25°C, Z1 is a 6.8-V zener diode with a TC of 2 mV/°C, and Q1 and Q2 are BJTs that display VBE of 0.7 V at a current of 100 μA and have a TC of –2 mV/°C. Design the circuit so that at 125°C, a current of 200 μA flows in each of Q1 and Q2 . What is the current in Q2 at 25°C?
(a) Specify the W/L ratio for each of the four transistors. (b) In the quiescent state with v O = 0, what must v I be? (c) If QN is required to supply a maximum load current of 10 mA, find the maximum allowable output voltage. Assume that the transistor supplying IBIAS needs a minimum of 0.2 V to operate properly.
CHAPTER 12
not appear directly at the output. Find the value of R that causes Q5 to turn on and absorb all of IBIAS = 2 mA, when the −14 current being sourced reaches 100 mA. For Q5 , IS = 10 A. If the normal peak output current is 75 mA, find the voltage drop across R and the collector current in Q5 .
12.49 The class AB output stage in Fig. 12.24 utilizes two 2 matched transistors with kn = kp = 200 mA/V and is operated from ±2.5-V power supplies. If the stage is required to supply a maximum current of ±20 mA, what is the output voltage swing realized? 12.50 0004For 0004the CMOS output stage of Fig. 12.25 with IQ = 2 mA, 0004VOV 0004 = 0.2 V for each of QP and QN at the quiescent point, and μ = 5, find the output resistance at the quiescent point. 12.51 (a) Show that for the CMOS output stage of Fig. 12.25, |Gain error| =
Rout RL
(b) For a stage that drives a load resistance of 100 0003 with a gain error of less than 3%, find the overdrive voltage at which QP and QN should be operated. Let IQ = 2.5 mA and μ = 5. 12.52 Show that in the CMOS class AB common-source output stage (Fig. 12.25), QN turns off when v O = 4IQ RL and QP turns off when v O = −4IQ RL . This is equivalent to saying 0004 0004 that one of the transistors turns off when 0004iL 0004 reaches 4IQ . D *12.53 It is required to design the circuit of Fig. 12.25 to drive a load resistance of 50 0003 while exhibiting an output resistance, around the quiescent point, of 2.5 0003.
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CHAPTER 12
PROBLEMS
990 Chapter 12 Output Stages and Power Amplifiers 0004 0004 Operate QN and QP at IQ = 1.5 mA and 0004VOV 0004 = 0.15 V. The 2 technology utilized is specified to have kn = 250 μA/V , 2 kp = 100 μA/V , Vtn = − Vtp = 0.5 V, and VDD = VSS = 2.5 V. Specify (W/L) for each of QN and QP . Specify the required value of μ. What is the expected error in the stage gain? In the quiescent state, what dc voltage must appear at the output of each of the error amplifiers? (e) At what value of positive v O will QP be supplying all the load current? Repeat for negative v O and QN supplying all the load current. (f) What is the linear range of v O ?
(a) (b) (c) (d)
*12.54 Figure P12.54 shows a class AB output stage utilizing a pair of complementary MOSFETs (QN , QP ) and
employing BJTs for biasing and in the driver stage. The latter consists of complementary Darlington emitter followers formed by Q1 through Q4 and has the low output resistance necessary for driving the output MOSFETs at high speeds. Of special interest is the bias circuit utilizing two VBE multipliers formed by Q5 and Q6 and their associated resistors. Transistor Q6 is placed in direct thermal contact with the output transistors and thus has the same temperature as that of QN and QP . (a) Show that VGG is given by
R R VGG = 1 + 3 VBE6 + 1 + 1 VBE5 − 4VBE R4 R2 (b) Noting that VBE6 is thermally coupled to the output devices while the other BJTs remain at constant temperature, show that
IBIAS
Figure P12.54
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 991
CHAPTER 12
∂VGG R ∂VBE6 = 1+ 3 ∂T R4 ∂T
Section 12.8: IC Power Amplifiers D 12.55 In the power-amplifier circuit of Fig. 12.29, two resistors are important in controlling the overall voltage gain. Which are they? Which controls the gain alone? Which affects both the dc output level and the gain? A new design is being considered in which the output dc level is approximately 23 VS (rather than approximately 21 VS ) with a gain of 50 (as before). What changes are needed? 12.56 Consider the front end of the circuit in Fig. 12.29. For VS = 22 V, calculate approximate values for the bias currents 0004 0004 in Q1 through Q6 . Assume β npn = 100, β pnp = 20, and 0004VBE 0004 = 0.7 V. Also find the dc voltage at the output.
PROBLEMS
(c) To keep the overdrive voltages of QN and QP , and hence their quiescent current, constant with temperature variation, ∂VGG /∂T is made equal to ∂(VtN + VtP )/∂T . Find R3 /R4 that provides this temperature stabiliza◦ tion when |Vt | changes by −3 mV/ C and ∂VBE /∂T = ◦ − 2 mV/ C. (d) Using the value of R3 /R4 found in (c) and assuming that the nominal value of VBE is 0.7 V and that the MOSFETs 2 have |Vt | = 3 V and μCox (W/L) = 2 A/V , find |VGS |, VGG , R, and R1 /R2 to establish a quiescent current of 100 mA in the output transistors and 20 mA in the driver stage. Figure P12.58
D 12.59 For the bridge amplifier of Fig. 12.32, let R1 = R3 = 10 k0003. Find R2 and R4 to obtain an overall gain of 8 V/V. D 12.60 An alternative bridge amplifier configuration, with high input resistance, is shown in Fig. P12.60. [Note the similarity of this circuit to the front end of the instrumentation amplifier circuit shown in Fig. 2.20(b).] What is the gain v O /v I ? For op amps (using ±15-V supplies) that limit at ±13 V, what is the largest sine wave you can provide across RL ? Using 1 k0003 as the smallest resistor, find resistor values that make v O /v I = 8 V/V. Make sure that the signals at the outputs of the two amplifiers are complementary.
D 12.57 It is required to use the LM380 power amplifier to drive an 8-0003 loudspeaker while limiting the maximum possible device dissipation to 2 W. Use the graph of Fig. 12.31 to determine the maximum possible power-supply voltage that can be used. (Use only the given graphs; do not interpolate.) If the maximum allowed THD is to be 3%, what is the maximum possible load power? To deliver this power to the load what peak-to-peak output sinusoidal voltage is required? 12.58 For the circuit in Fig. P12.58, assuming all transistors to have large β, show that iO = v I /R. [This voltage-to-current converter is an application of a versatile circuit building block known as the current conveyor; see Sedra and Roberts (1990).] For β = 100, by what approximate percentage is iO actually lower than this ideal value?
Figure P12.60
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CHAPTER 12
PROBLEMS
992 Chapter 12 Output Stages and Power Amplifiers VDD
Section 12.9 Class D Power Amplifiers 12.61 Sketch diagrams resembling those in Figs. 12.33(a), (b). Let vT have ±10 V peaks and assume vA is a sine wave with 5-V peak amplitude. Let the frequency of vT be 5 times that of vA . The comparator output levels are ±10 V.
ID
R
⫹ 12.62 A pulse waveform swinging between ±10 V has a duty ratio of 0.65. What is its average value? If the duty ratio is changed to 0.35, what does the average value become? 12.63 For the circuit in Fig. 12.34(b): (a) If vA is a sine wave, what is the maximum power supplied to a load of resistance R, in terms of VDD ? (b) The power loss is mostly due to the repeated charging and discharging of a capacitance C across the load. It can 2 be shown that this switching power is given by 4fs C VDD . Find an expression for the power-conversion efficiency η and evaluate the value of η for the case fs = 250 kHz and C = 1000 pF.
Section 12.10 Power Transistors 12.64 A power MOSFET is specified to have IDmax = 5 A, VDSmax = 50 V, and PDmax = 50 W. (a) Sketch the SOA boundaries. (b) If the MOSFET is used in the common-source configuration as shown in Fig. P12.64, show that the maximum current occurs when VDS = 0, the maximum VDS occurs when ID = 0, and the maximum power dissipation occurs when VDS = VDD /2. (c) For VDD = 40 V, find the smallest resistance R for which the operating point is always within the SOA. What are the corresponding values of IDmax and PDmax ? (d) Repeat (c) for VDD = 30 V. (e) Repeat (c) for VDD = 15 V.
⫹ VGS
VGS ⫺
⫺ Figure P12.64
D 12.65 A particular transistor having a thermal resistance θJA = 2.5°C/W is operating at an ambient temperature of 30°C with a collector–emitter voltage of 20 V. If long life requires a maximum junction temperature of 130°C, what is the corresponding device power rating? What is the greatest average collector current that should be considered? 12.66 A particular transistor has a power rating at 25°C of 10 W, and a maximum junction temperature of 150°C. What is its thermal resistance? What is its power rating when operated at an ambient temperature of 50°C? What is its junction temperature when dissipating 5 W at an ambient temperature of 50°C? 12.67 A power transistor operating at an ambient temperature of 50°C, and an average emitter current of 3 A, dissipates 20 W. If the thermal resistance of the transistor is known to be less than 3°C/W, what is the highest junction temperature you would expect? If the transistor VBE measured using a pulsed emitter current of 3 A at a junction temperature of 25°C is 0.80 V, what average VBE would you expect under normal operating conditions? (Use a temperature coefficient of –2 mV/°C.) 12.68 For a particular application of the transistor specified in Example 12.7, extreme reliability is essential. To improve reliability, the maximum junction temperature is to be limited to 100°C. What are the consequences of this decision for the conditions specified?
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 993
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
12.70 A power transistor for which TJmax = 180°C can dissipate 50 W at a case temperature of 30°C. If it is connected to a heat sink using an insulating washer for which the thermal resistance is 0.6°C/W, what heat-sink temperature is necessary to ensure safe operation at 30 W? For an ambient temperature of 27°C, what heat-sink thermal resistance is required? If, for a particular extruded-aluminum-finned heat sink, the thermal resistance in still air is 6°C/W per centimeter of length, how long a heat sink is needed?
CHAPTER 12
12.69 A power transistor is specified to have a maximum junction temperature of 150°C. When the device is operated at this junction temperature with a heat sink, the case temperature is found to be 97°C. The case is attached to the heat sink with a bond having a thermal resistance θCS = 0.5°C/W and the thermal resistance of the heat sink θSA = 0.1°C/W. If the ambient temperature is 25°C, what is the power being dissipated in the device? What is the thermal resistance of the device, θJC , from junction to case?
1074 Chapter 13 Operational-Amplifier Circuits 0002
To obtain low input offset voltage and current, and high CMRR, the 741 input stage is designed to be perfectly balanced. The CMRR is increased by common-mode feedback, which also stabilizes the dc operating point.
0002
Operation from a single low-voltage supply gives rise to a number of new important specifications including a common-mode input range that extends beyond the supply rails (i.e., more than rail-to-rail operation) and a near rail-to-rail output voltage swing.
0002
To obtain high input resistance and low input bias current, the input stage of the 741 is operated at a very low current level.
0002
The rail-to-rail input common-mode range is achieved by using resistive loads (instead of current-mirror loads) for the input differential pair as well as utilizing two complementary differential amplifiers in parallel.
0002
In the 741, output short-circuit protection is accomplished by turning on a transistor that takes away most of the base current drive of the output transistor.
0002
To increase the gain of the input stage above that achieved with resistive loads, the folded-cascode configuration is utilized.
0002
The use of Miller frequency compensation in the 741 circuit enables locating the dominant pole at a very low frequency while utilizing a relatively small compensating capacitance.
0002
To regulate the dc bias voltages at the outputs of the differential folded-cascode stage so as to maintain active-mode operation at all times, common-mode feedback is employed.
0002
Two-stage op amps can be modeled as a transconductance amplifier feeding an ideal integrator with CC as the integrating capacitor.
0002
0002
The slew rate of a two-stage op amp is determined by the first-stage bias current and the frequency-compensation capacitor.
The output stage of a low-voltage op amp utilizes a complementary pair of common-emitter transistors. This allows v O to swing to within 0.1 V or so from each of the supply rails. The disadvantage is a high open-loop output resistance. This, however, is substantially reduced when negative feedback is applied around the op amp.
0002
0002
While the 741 and its generation of op amps nominally operate from ±15-V power supplies, modern BJT op amps typically utilize a single ground-referenced supply of only 2 V to 3 V.
Modern output stages operate in the class AB mode and utilize interesting feedback techniques to set the quiescent current as well as to ensure that the inactive output transistor does not turn off, a precaution that avoids increases in crossover distortion.
PROBLEMS Computer Simulation Problems
Section 13.1: The Two-Stage CMOS Op Amp
Problems identified by the Multisim/PSpice icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion. Instructions to assist in setting up PSpice and Multisim simulations for all the indicated problems can be found in the corresponding files on the website. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
13.1 A particular design of the two-stage CMOS operational amplifier of Fig. 13.1 utilizes ±1-V power supplies. All transistors are operated at overdrive voltages of 0.2-V magnitude. 0002 0002 The process technology provides devices with Vtn = 0002Vtp 0002 = 0.4 V. Find the input common-mode range and the range allowed for v O . 13.2 The CMOS op amp of Fig.0002 13.1 is fabricated in a process 0006 0006 0002 for which VAn = 25 V/μm and 0002VAp 0002 = 20 V/μm. Find A1 , A2 ,
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 1075
W/L (μm/μm)
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
36/0.3
36/0.3
6/0.3
6/0.3
30/0.3
W /0.3
45/0.3
6/0.3
D 13.3 The CMOS op0002 amp of Fig. 13.1 is fabricated in 00060002 a process for which 0002VA 0002 for all devices is 20 V/μm. If all transistors have L = 0.3 μm and are operated at equal overdrive voltages, find the magnitude of the overdrive voltage required to obtain a dc open-loop gain of 1600 V/V. 13.4 Consider the circuit in Fig. 13.1 with the device geometries shown at the top of this page. Let IREF = 40 μA, 0002 0002 0002Vt 0002 for all devices = 0.45 V, μn Cox = 270 μA/V2 , μp Cox = 0002 0002 2 70 μA/V , 0002VA 0002 for all devices = 15 V, VDD = VSS = 1 V. Determine the width of Q6 , W, that will ensure that the op amp will not have a systematic 0002 0002 offset 0002 0002voltage. Then, for all devices, evaluate ID , 0002VOV 0002, 0002VGS 0002, gm , and ro . Provide your results in a table. Also find A1 , A2 , the dc open-loop voltage gain, the input common-mode range, and the output voltage range. Neglect the effect of VA on the bias currents.
100 k0003, C1 = 0.1 pF, Gm2 = 2 mA/V, R2 = 50 k0003, and C2 = 2 pF. (a) Find the dc gain. (b) Without CC connected, find the frequencies of the two poles in radians per second and sketch a Bode plot for the gain magnitude. (c) With CC connected, find ωP2 . Then find the value of CC that will result in a unity-gain frequency ωt at least two octaves below ωP2 . For this value of CC , find ωP1 and ωZ and sketch a Bode plot for the gain magnitude. 13.8 A CMOS op amp with the topology in Fig. 13.1 has gm1 = gm2 = 1 mA/V, gm6 = 3 mA/V, the total capacitance between node D2 and ground is 0.2 pF, and the total capacitance between the output node and ground is 3 pF. Find the value of CC that results in ft = 50 MHz, and verify that ft is lower than fZ and fP2 . 13.9 A particular design of the two-stage CMOS op amp of Fig. 13.1 has Gm1 = 1 mA/V and Gm2 = 2 mA/V. The total capacitance at the output node is 1 pF. While utilizing a Miller compensation capacitor CC without a series resistance R, the amplifier is made to have a uniform −20-dB/decade gain rolloff with a unity-gain frequency ft of 100 MHz.
13.6 A two-stage CMOS op amp has Gm1 = 0.8 mA/V, Gm2 = 2.4 mA/V, C1 = 0.1 pF, and C2 = 1.2 pF. Find the value of CC that will provide a unity-gain frequency of 120 MHz. Also, determine the values of fP2 and fZ .
(a) What must the value of CC be? (b) What do you estimate the frequencies of the poles, fP1 and fP2 , and of the right-half-plane zero, fZ , to be? (c) What is the phase margin obtained? (d) To increase the phase margin, a resistance R is connected in series with CC . What is the value of R that results in fZ = ∞, and what is the resulting phase margin? (e) If R is increased further, until it moves the zero into the left half-plane and thus turns the phase it introduces into phase lead, what value of R is needed to obtain a phase ◦ margin of 85 ?
13.7 For the CMOS amplifier in Fig. 13.1, whose equivalent circuit is shown in Fig. 13.2, let Gm1 = 1 mA/V, R1 =
D 13.10 A particular implementation of the CMOS amplifier of Figs. 13.1 and 13.2 provides Gm1 = 0.3 mA/V,
D 13.5 Design the two-stage CMOS op amp in Fig. 13.1 to provide a CMRR of about 72 dB. If all the transistors are operated at equal overdrive voltages of 0.15 V and have equal channel lengths, find 0002the0002minimum required channel length. 0006 For this technology, 0002VA 0002 = 15 V/μm. What is the dc gain realized?
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PROBLEMS
and Av if all devices are 0.3 μm long, Q1 and Q2 are operated at overdrive voltages of 0.15-V magnitude, and Q6 is operated at VOV = 0.2 V. Also, determine the op-amp output resistance obtained when the second stage is biased at 0.3 mA. What do you expect the output resistance of a unity-gain voltage amplifier to be, using this op amp?
CHAPTER 13
Transistor
CHAPTER 13
PROBLEMS
1076 Chapter 13 Operational-Amplifier Circuits Gm2 = 0.6 mA/V, ro2 = ro4 = 222 k0003, ro6 = ro7 = 111 k0003, and C2 = 1 pF. (a) Find the dc gain. (b) Find the frequency of the second pole, fP 2 . (c) Find the value of the resistance R that, when placed in series with CC , causes the transmission zero to be located at s = ∞. (d) With R in place, as in (c), find the value of CC that results in the highest possible value of ft while providing a phase margin of 80°. What value of ft is realized? What is the corresponding frequency of the dominant pole? (e) To what value should CC be changed to double the value of ft ? At the new value of ft , what is the phase shift introduced by the second pole? To reduce this excess phase shift to 10° and thus obtain an 80° phase margin, as before, what value should R be changed to? 13.11 A two-stage CMOS op amp has each of its first-stage transistors Q1 and Q2 operating at an overdrive voltage of 0.2 V. The op amp has a uniform −20-dB/decade frequency response with a unity-gain frequency of 100 MHz. What do you expect the slew rate of this amplifier to be? If each of Q1 and Q2 is biased at 50 μA, what must the value of CC be? D 13.12 A two-stage CMOS op amp similar to that in Fig. 13.1 is found to have a capacitance between the output node and ground of 0.7 pF. If it is desired to have a unity-gain bandwidth ft of 100 MHz with a phase margin of 72° what must gm 6 be set to? Assume that a resistance R is connected in series with the frequency-compensation capacitor CC and adjusted to place the transmission zero at infinity. What value 0002 0002 should R have? If the first stage is operated at 0002VOV 0002 = 0.15 V, what is the value of slew rate obtained? If the first-stage bias current I = 100 μA, what is the required value of CC ? D 13.13 A CMOS op amp with the topology shown in Fig. 13.1 is designed to provide Gm1 = 1 mA/V and Gm2 = 5 mA. (a) Find the value of CC that results in ft = 80 MHz. (b) What is the maximum value that C2 can have while achieving a 70° phase margin?
D 13.14 A CMOS op amp with the topology shown in Fig. 13.1 but with a resistance R included in series with CC is designed to provide Gm 1 = 0.8 mA/V and Gm2 = 2 mA/V. (a) Find the value of CC that results in ft = 100 MHz. (b) For R = 500 0003, what is the maximum allowed value of C2 for which a phase margin of at least 60° is obtained? 13.15 A two-stage CMOS op amp resembling that in Fig. 13.1 is found to have a slew rate of 60 V/μs and a unity-gain bandwidth ft of 60 MHz. (a) Estimate the value of the overdrive voltage at which the input-stage transistors are operating. (b) If the first-stage bias current I = 120 μA, what value of CC must be used? 2 (c) For a process for which μp Cox = 60 μA/V , what W/L ratio applies for Q1 and Q2 ? D 13.16 Sketch the circuit of a two-stage CMOS amplifier having the structure of Fig. 13.1 but utilizing NMOS transistors in the input stage (i.e., Q1 and Q2 ). −
D 13.17 (a) Show that the PSRR of a CMOS two-stage op amp for which all transistors 0002 0002have the same channel length and are operated at equal 0002VOV 0002 is given by 0002 0002V PSRR = 200020002 A V −
OV
00022 0002 0002 0002
0002 0002 (b) For 0002VOV 0002 = 0.15 V, what is the minimum channel length − required to0002 obtain a PSRR of 72 dB? For the technology 00060002 available, 0002VA 0002 = 15 V/μm. D 13.18 It is required to design the circuit of Fig. 13.8 to provide a bias current IREF of 225 μA with Q8 and Q9 as matched devices having W/L = 60/0.5. Transistors Q10 , Q11 , and Q13 are to be identical and must have the same gm as Q8 and Q9 . Transistor Q12 is to be four times as wide as Q13 . Let 0006 0006 2 kn = 3kp = 180 μA/V , and Vtn =|Vtp |= 0.5 V; let all channel lengths be equal; and let VDD = VSS = 1.5 V. Find the required value of RB . What is the voltage drop across RB ? Also specify the W/L ratios of Q10 , Q11 , Q12 , and Q13 and give the expected dc voltages at the gates of Q12 , Q10 , and Q8 .
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Problems 1077
D 13.20 For the folded-cascode op amp in Fig. 13.10 utilizing power supplies of ±1 V, find the values of VBIAS1 ,VBIAS2 , and VBIAS3 to maximize the allowable range of VICM and v O . Assume that all transistors0002are0002 operated at equal overdrive voltages of 0.15 V. Assume 0002Vt 0002 for all devices is 0.4 V. Specify the maximum range of VICM and of v O . D 13.21 For the folded-cascode op-amp circuit of Figs. 13.9 and 13.10 with bias currents I = 400 μA and IB = 250 μA, and with all transistors operated at overdrive voltages of 0.2 V, find the W/L ratios for all devices. Assume that the 0006 2 technology available is characterized by kn = 400 μA/V and 0006 2 kp = 100 μA/V . 13.22 Consider a design of the cascode op amp of Fig. 13.10 for which I = 400 μA and 0002IB =0002 250 μA. Assume that all 0002 0002 transistors0002 are 0002 operated at VOV = 0.2 V and that for all devices, 0002VA 0002 = 10 V. Find Gm , Ro , and Av . Also, if the op amp is connected in the feedback configuration shown in Fig. P13.22, find the voltage gain and output resistance of the closed-loop amplifier.
C 9C 0003 Vo Vi
0002 Rof
Figure P13.22
D 13.23 Consider the folded-cascode op amp of Fig. 13.9 when loaded with a 10-pF capacitance. What should the bias current IB be to obtain a slew rate of at least 10 V/μs? If the input-stage transistors are biased at a current three times that at which each of Q3 and Q4 is biased, find the value of I. If the
13.24 For a particular design of the folded-cascode op amp in Fig. 13.9, I < IB . What slew rate is obtained? D *13.25 Design the folded-cascode circuit of Fig. 13.10 to provide voltage gain of 80 dB and a unity-gain frequency of 20 MHz when CL = 100002 pF. 0002Design for IB = I, and operate 0002 all devices at the same 0002V 0002 OV0002 . Utilize transistors with 1-μm channel length for which 0002VA 0002 is specified to be 12 V. Find the required overdrive voltages and bias currents. What slew rate 0006 0006 2 is achieved? Also, for kn = 2.5kp = 400 μA/V , specify the required width of each of the 11 transistors used. D 13.26 Sketch the circuit that is complementary to that in Fig. 13.10, that is, one that uses an input p-channel differential pair. **13.27 This problem presents a very interesting addition to the folded-cascode op-amp circuit of Fig. 13.10, designed to deal with the situation during amplifier slewing. In particular, the additional circuitry does two things: It prevents Q1 and Q11 from going into the triode region, and it increases the current available to charge CL and thus increases the slew rate. The circuit is shown in Fig. P13.27 (with the current-mirror circuit omitted, for simplicity). Observe that three transistors are added: Q14 , which is biased by a constant-current source (20 μA), establishes the dc currents in Q9 and Q10 . Assume with respect to Q9 and Q10 that each has a W/L ratio 10 times that of Q14 . The other two additional transistors are Q12 and Q13 , which are diode connected and are normally cut off. (a) For Vid = 0, find the bias current in each of Q1 , Q2 , Q3 , Q4 , Q14 , Q9 , and Q10 . Also, for the dc voltages shown, and assuming Vtn =|Vtp |= 0.45 V and that all conducting devices are operating at |VOV | = 0.15 V, show that Q12 and Q13 will be cut off. (b) For an input differential signal that causes Q2 to turn off and Q1 to conduct the entire bias current (320 μA), Q12 turns on (while Q13 remains off). Noting that the drain current of Q12 adds to the 20 μA flowing through Q14 , find the current that now flows through Q10 and onto CL .
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PROBLEMS
D 13.19 The op-amp circuit of Fig. 13.10 is operated from ±1-V power supplies. If the power dissipated in the circuit is to be limited to 1 mW, find the maximum value of IB allowed. If this value is used, and each of Q1 and Q2 is to be biased at a current four times that used for each of Q3 and Q4 , find the value of I, ID1,2 , and ID3,4 .
input-stage transistors are operated at overdrive voltages of 0.15 V, what is the unity-gain bandwidth realized? If the two nondominant poles have the same frequency of 50 MHz, what is the phase margin obtained? If it is required to have a phase margin of 75°, what must ft be reduced to? By what amount should CL be increased? What is the new value of SR?
CHAPTER 13
Section 13.2: The Folded-Cascode CMOS Op Amp
CHAPTER 13
PROBLEMS
1078 Chapter 13 Operational-Amplifier Circuits 00021 V Q9 Q14
Q10 Q13
Q12
Q3
20 A 0002
Q1
Q2
0003
Q4 00020.25 V CL
320 A 00030.4 V
Q11
–1 V Figure P13.27
By what factor does the slew rate increase relative to the value without Q12 present? Also give an approximate estimate of the voltage at the drain of Q1 during the slewing transient. 13.28 For the circuit in Fig. 13.12, assume that all transistors are operating 0002 0002at equal overdrive voltages of 0.15-V magnitude and have 0002Vt 0002 = 0.45 V and that VDD = VSS = 1 V. Find (a) the range over which the NMOS input stage operates, (b) the range over which the PMOS input stage operates, (c) the range over which both operate (the overlap range), and (d) the input common-mode range. Assume that all current sources require a minimum voltage of |VOV | to operate properly. 13.29 A particular design of the wide-swing current mirror of Fig. 13.13(b) utilizes devices having W/L = 20, 0006 2 kn = 400 μA/V , and Vt = 0.45 V. For IREF = 90 μA, what value of VBIAS is needed? Also give the voltages that you expect to appear at all nodes and specify the minimum voltage allowable at the output terminal. If VA is specified to be 10 V, what is the output resistance of the mirror?
D 13.30 For the folded-cascode circuit of Fig. 13.9, let the total capacitance to ground at each of the source nodes of Q3 and Q4 be denoted CP . Assuming that the incremental resistance between the drain of Q3 and ground is small, show that the pole that arises at the interface between the first and second stages has a frequency fP 0007 gm3 /2π CP . Now, if this is the only nondominant pole, what is the largest value that CP can be (expressed as a fraction of CL ) while a phase margin of 80° is achieved? Assume that all transistors are operated at the same bias current and overdrive voltage.
Section 13.3: The 741 BJT Op Amp 13.31 In the 741 op-amp circuit of Fig. 13.14, Q1 , Q2 , Q5 , and Q6 are biased at collector currents of 9.5 μA; Q16 is biased at a collector current of 16.2 μA; and Q17 is biased at a collector current of 550 μA. All these devices are of the “standard npn” −14 type, having IS = 10 A, β = 200, and VA = 125 V. For each of these transistors, find VBE , gm , re , rπ , and ro . Provide your results in table form. (Note that these parameter values are utilized in the text in the analysis of the 741 circuit.)
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 1079 k3 = k4 = 16k1 , find the required value of I1 to yield a bias current in Q3 and Q4 of 1.6 mA.
−14
PROBLEMS
Find I1 for the case in which IS3 = IS4 = 3 × 10 A, IS1 = −14 IS2 = 10 A, and a bias current I3 = 150 μA is required. 000215 V I1 Q3 Q1
I3 Figure P13.35
Q2
Q4
000315 V Figure P13.32
13.33 Transistor Q13 in the circuit of Fig. 13.14 consists, in effect, of two transistors whose emitter–base junctions are −14 connected in parallel and for which ISA = 0.25 × 10 A, −14 ISB = 0.75 × 10 A, β = 50, and VA = 50 V. For operation at a total emitter current of 0.73 mA, find values for the parameters VEB , gm , re , rπ , and ro for the A and B devices.
CHAPTER 13
D 13.32 For the circuit in Fig. P13.32, neglect base currents and use the exponential iC−vBE relationship to show that I I I3 = I1 S3 S4 IS1 IS2
D 13.36 For the 741 circuit, estimate the reference current IREF in the event that ±10-V supplies are used. What value of R5 would be necessary to reestablish the same bias current for ±10-V supplies as exists for ±15 V in the original design? D 13.37 Design a Widlar current source to supply a current of 10 μA given a reference input current of 0.3 mA. Assume −14 that the transistors have IS = 10 A and high β. Find VBE of each of the two transistors as well as the value of R. 13.38 Consider the dc analysis of the 741 input stage shown in Fig. 13.15.
13.34 In the circuit of Fig. 13.14, Q1 and Q2 exhibit emitter–base breakdown at 7 V, while for Q3 and Q4 such a breakdown occurs at about 50 V. What differential input voltage would result in the breakdown of the input-stage transistors?
(a) Derive an expression for I taking βP into account. What is the percentage change in I if βP drops from 50 to 20? (b) Now, consider an alternative design of this circuit in which the feedback loop is eliminated. That is, Q8 and Q9 are eliminated and IC10 is fed to the common-base connection of Q3 and Q4 . What is I now in terms of IC10 ? If βP changes from 50 to 20, what is the resulting percentage change in I?
D 13.35 Figure P13.35 shows the CMOS version of the circuit in Fig. P13.32. Find the relationship between I3 and I1 in terms of k1 , k2 , k3 , and k4 of the four transistors, assuming the threshold voltages of all devices to be equal in magnitude. Note that k denotes μCox W/L. In the event that k1 = k2 and
D 13.39 Consider the dc analysis of the 741 input stage shown in Fig. 13.15 for the situation in which IS 9 = 2IS 8 . For IC 10 = 19 μA and assuming β P to be high, what does I become? Redesign the Widlar source to reestablish IC 1 = IC 2 = 9.5 μA.
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CHAPTER 13
PROBLEMS
1080 Chapter 13 Operational-Amplifier Circuits D 13.40 Consider the circuit shown in Fig. 13.15. If IC10 = 40 μA and I is required to be 10 μA, what must be the ratio of the emitter–junction area of Q9 to that area of Q8 ? Assume that βP is large.
resistance between the two terminals of the VBE – multiplier circuit?
13.41 For the mirror circuit shown in Fig. 13.16 with the bias and component values given in the text for the 741 circuit, what does the current in Q6 become if R2 is shorted?
I 0005 180 μA
D 13.42 It is required to redesign the circuit of Fig. 13.16 by selecting a new value for R3 so that when the base currents are not neglected, the collector currents of Q5 , Q6 , and Q7 all become equal, assuming that the input current IC 3 = 9.5 μA. Find the new value of R3 and the three currents. Recall that β N = 200. 13.43 Consider the input circuit of the 741 op amp of Fig. 13.14 when the emitter current of Q8 is about 19 μA. If β of Q1 is 150 and that of Q2 is 220, find the input bias current IB and the input offset current IOS of the op amp. 13.44 For a particular application, consideration is being given to selecting 741 ICs for input bias and offset currents limited to 60 nA and 5 nA, respectively. Assuming other aspects of the selected units to be normal, what minimum β N and what β N variation are implied? 13.45 For a 741 employing ±5-V supplies, |VBE | = 0.6 V, and |VCEsat | = 0.2 V, find the input common-mode range. Neglect the voltage drops across R1 and R2 . D 13.46 Consider the design of the second stage of the 741. What value of R9 would be needed to reduce IC 16 to 9.5 μA? (Hint: Build on Exercise 13.21) D 13.47 Reconsider the 741 output stage as shown in Fig. 13.17, in which R10 is adjusted to make IC 19 = IC 18 . What is the new value of R10 ? What values of IC 14 and IC 20 result? Recall that IREF = 0.73 mA. D *13.48 An alternative approach to providing the voltage drop needed to bias the output transistors is the VBE – multiplier circuit shown in Fig. P13.48. Design the circuit to provide a terminal voltage of 1.118 V (the same as in the 741 circuit). Base your design on half the current flowing through R1 , and −14 assume that IS = 10 A and β = 200. What is the incremental
180 μA
Figure P13.48
13.49 For the circuit of Fig. 13.14, what is the total current required from the power supplies when the op amp is operated in the linear mode, but with no load? Hence, estimate the quiescent power dissipation in the circuit. (Hint: Use the data given in Table 13.1.) 13.50 Consider the 741 input stage as modeled in Fig. 13.18, with two additional npn diode-connected transistors, Q1a and Q2a , connected between the present npn and pnp devices, one per side. Convince yourself that each of the additional devices will be biased at the same current as Q1 to Q4 —that is, 9.5 μA. What does Rid become? What does Gm 1 become? What is the value of Ro4 now? What is the output resistance of the first stage, Ro1 ? (Note that Ro6 remains unchanged at 18.2 M0003.) What is the new open-circuit voltage gain, Gm 1 Ro1 ? Compare these values with the original ones, namely, Rid = 21 M0003, Gm1 = 0.19 mA/V, Ro4 = 10.5 M0003, Ro1 = 6.7 M0003, and |Avo | = 1273 V/V. 13.51 Consider the current mirror in Fig. 13.19. What value must R2 be increased to in order to increase Ro6 by a factor of 2? Recall that Q6 is operating at IC6 = 9.5 μA and has β = 200 and VA = 125 V. 13.52 Repeat Exercise 13.24 with R1 = R2 replaced by 2-k0003 resistors.
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Problems 1081
(a) Show that an input offset voltage VOS can be compensated for (i.e., reduced to zero) by creating a relative mismatch R/R between R1 and R2 , R 1 + re /R V = OS R 2VT 1 − VOS /2VT where re is the emitter resistance of each of Q1 to Q6 , and R is the nominal value of R1 and R2 . (Hint: Use Eq. 13.94.) (b) Find R/R to trim a 3-mV offset to zero. (c) What is the maximum offset voltage that can be trimmed this way (corresponding to R2 completely shorted)? (Recall that each of Q5 and Q6 is biased at 9.5 μA.)
13.56 If the current transfer ratio of the mirror load of the 741 input stage is 0.995, find the CMRR of the input stage. (Hint: Use Eq. 13.102 together with the output resistance values determined in Exercise 13.28. Recall that the input-stage transistors are biased at 9.5 μA.) 13.57 Consider the circuit of Fig. 13.14 modified to include resistors R in series with the emitters of each of Q8 and Q9 . What does the resistance looking into the collector of Q9 , Ro9 , become? For what value of R does it equal Ro10 (i.e., 31.1 M0003)? For this case, what does Ro looking to the left of node Y become? (Recall that Q9 is biased at 0.73 mA.) *13.58 What is the effect on the differential gain of the 741 op amp of short-circuiting one or the other or both of R1 and R2 in Fig. 13.14? (Refer to Fig. 13.19.) For simplicity, assume β = ∞. 13.59 An alternative approach to that presented in Example 13.5 for determining the CMRR of the 741 input stage is investigated in this problem. Rather than performing the analysis on the closed loop shown in Fig. 13.23, we observe that the negative feedback increases the resistance at node Y by the amount of negative feedback. Thus, we can break the loop at Y and connect a resistance Rf = (1 + Aβ)Ro between the common-base connection of Q3 −Q4 and ground. We can then determine the current i and Gmcm . Using the fact that the loop gain is approximately equal to βP (Exercise 13.17) show that this approach yields an identical result to that found in Example 13.5. 13.60 Consider a variation on the design of the 741 second stage in which R8 = 50 0003. What Ri2 and Gm2 correspond?
Figure P13.54
13.55 Through a processing imperfection, the β of Q4 in Fig. 13.14 is reduced to 10, while the β of Q3 remains at its regular value of 50. Assuming that the collector current of Q3 remains unchanged at 9.5 μA, find the net output dc current of
D 13.61 In the analysis of the 741 second stage, note that Ro2 is affected most strongly by the low value of Ro13B . Consider the effect of placing appropriate resistors in the emitters of Q12 , Q13A , and Q13B on this value. What resistor in the emitter of Q13B would be required to make Ro13B equal to Ro17 and thus Ro2 half as great? What resistors in each of the other emitters would be required?
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PROBLEMS
*13.54 In Example 13.4 we investigated the effect of a mismatch between R1 and R2 on the input offset voltage of the op amp. Conversely, R1 and R2 can be deliberately mismatched (using the circuit shown in Fig. P13.54, for example) to compensate for the op-amp input offset voltage.
the Q5−Q6 mirror, and hence find also the input offset voltage that this mismatch introduces.
CHAPTER 13
13.53 A manufacturing problem in a 741 op amp causes the current-transfer ratio of the mirror circuit that loads the input stage to become 0.8 A/A. For input devices (Q1 –Q4 ) appropriately matched and with high β, and normally biased at 9.5 μA, what input offset voltage results?
CHAPTER 13
PROBLEMS
1082 Chapter 13 Operational-Amplifier Circuits 0002 0002 13.620002 For0002 a 741 employing ±5-V supplies, 0002VBE 0002 = 0.6 V and 0002VCEsat 0002 = 0.2 V, find the output voltage limits that apply. D 13.63 Consider an alternative to the present 741 output stage in which Q23 is not used, that is, in which its base and emitter are joined. Reevaluate the reflection of RL = 2 k0003 to the collector of Q17 . What does A2 become? 13.64 Figure P13.64 shows the circuit for determining the op-amp output resistance when vO is positive and Q14 is conducting most of the current. Using the resistance of the Q18−Q19 network calculated in Exercise 13.35 (163 0003) and neglecting the large output resistance of Q13A , find Rout when Q14 is sourcing an output current of 5 mA.
current in Q22 equal to the maximum current available from the input stage (i.e., the current in Q8 )? What simple change would you make to reduce this current limit to 10 mA? 13.67 Using the data provided in Eq. (13.115) (alone) for the overall gain of the 741 with a 2-k0003 load, and realizing the significance of the factor 0.97 in relation to the load, calculate the open-circuit voltage gain, the output resistance, and the gain with a load of 500 0003. 13.68 A 741 op amp has a phase margin of 80°. If the excess phase shift is due to a second single pole, what is the frequency of this pole? 13.69 A 741 op amp has a phase margin of 80°. If the op amp has nearly coincident second and third poles, what is their frequency? D *13.70 For a modified 741 whose second pole is at 5 MHz, what dominant-pole frequency is required for 85° phase margin with a closed-loop gain of 100? Assuming CC continues to control the dominant pole, what value of CC would be required?
Rout
13.71 An internally compensated op amp having an ft of 5 6 MHz and dc gain of 10 utilizes Miller compensation around an inverting amplifier stage with a gain of –1000. If space exists for at most a 50-pF capacitor, what resistance level must be reached at the input of the Miller amplifier for compensation to be possible? 13.72 Consider the integrator op-amp model shown in Fig. 13.30. For Gm 1 = 2 mA/V, CC = 100 pF, and a resistance 7 of 2 × 10 0003 shunting CC , sketch and label a Bode plot for the magnitude of the open-loop gain. If Gm 1 is related to the first-stage bias current as Gm 1 = I/2VT , find the slew rate of this op amp.
Figure P13.64
13.65 Consider the positive current-limiting circuit involving Q13A , Q15 , and R6 . Find the current in R6 at which the collector current of Q15 equals the current available from Q13A (180 μA) minus the base current of Q14 . (You need to perform a couple of iterations.) D 13.66 Consider the 741 sinking-current limit involving R7 , Q21 , Q24 , R11 , and Q22 . For what current through R7 is the
13.73 For an amplifier with a slew rate of 10 V/μs, what is the full-power bandwidth for outputs of ±10 V? What unity-gain bandwidth, ωt , would you expect if the topology was similar to that of the 741? D 13.74 If a resistance RE is included in each of the emitter leads of Q3 and Q4 of the 741 circuit, show that the slew rate is 4(VT + IRE /2)ωt . Hence find the value of RE that would double the 741 slew rate while keeping ωt and I unchanged. What are the new values of CC , the dc gain, and the 3-dB frequency?
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Problems 1083
CHAPTER 13 PROBLEMS
Figure P13.75
D 13.75 Figure P13.75 shows a circuit suitable for op-amp applications. For all transistors β = 100, VBE = 0.7 V, and ro = ∞. (a) For inputs grounded and output held at 0 V (by negative feedback) find the collector currents of all transistors. Neglect base currents. (b) Calculate the input resistance. (c) Calculate the gain of the amplifier with a load of 5 k0003. (d) With load as in (c) calculate the value of the capacitor C required for a 3-dB frequency of 100 Hz.
Section 13.4: Modern Techniques for the Design of BJT Op Amps Unless otherwise specified, for the problems 0002 0002 in this 0002section 0002 assume0002 βN =0002 40, βP = 10, VAn = 30 V, 0002VAp 0002 = 20 V, 0002VBE 0002 = 0.7 V, 0002VCEsat 0002 = 0.1 V. D 13.76 Design the circuit in Fig. 13.33 to generate a current I = 5 μA. Utilize transistors Q1 and Q2 having areas in a ratio of 1:4. Assume that Q3 and Q4 are matched and design for a
0.15-V drop across each of R3 and R4 . Specify the values of R2 , R3 , and R4 . Ignore base currents. D 13.77 Consider the circuit of Fig. 13.33 for the case designed in Exercise 13.37, namely, I = 10 μA, IS2 /IS1 = 2, R2 = 1.73 k0003, R3 = R4 = 20 k0003. Augment the circuit with npn transistors Q5 and Q6 with emitters connected to ground and bases connected to VBIAS1 , to generate constant currents of 10 μA and 40 μA, respectively. What should the emitter areas of Q5 and Q6 be relative to that of Q1 ? What value of a resistance R6 will, when connected in the emitter of Q6 , reduce the current generated by Q6 to 10 μA? Assuming that the VBIAS1 line has a low incremental resistance to ground, find the output resistance of current source Q5 and of current source Q6 with R6 connected. Ignore base currents. D 13.78 It is required to use the circuit in Fig. 13.33 to bias an npn differential pair. The bias current-source transistor of the pair, Q5 , is identical to Q2 and its base is connected to the BIAS1 line. In its emitter lead is connected a resistance R5 equal to R2 . The differential pair has two equal collector
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CHAPTER 13
PROBLEMS
1084 Chapter 13 Operational-Amplifier Circuits resistances RC connected to VCC , and the output voltage vo is taken between the two collectors. (a) Find an expression for the differential gain Ad in terms of (RC /R5 ) and (IS5 /IS1 ). Comment on the expected temperature dependence of Ad . Neglect the effect of finite βN . (b) Design the circuit for I = 20 μA and Ad = 10 V/V. Let the emitter areas of Q1 and Q5 be in the ratio 1:4. Specify the required values of R5 and RC . D 13.79 (a) Find the input common-mode range of the circuit in Fig. 13.35(a). Let VCC = 3 V and VBIAS = 2.3 V. (b) Give the complementary version of the circuit in Fig. 13.35(a), that is, the one in which the differential pair is npn. For the same conditions as in (a), what is the input common-mode range? 13.80 For the circuit in Fig. 13.35(b), let VCC = 3 V, VBIAS = 2.3 V, I = 20 μA, and RC = 25 k0003. Find the input common-mode range and the differential voltage gain v o /v id . Neglect base currents. D 13.81 For the circuit in Fig. 13.36, let VCC = 3 V, VBIAS = 0.7 V, and IC6 = 40 μA. Find RC that results in a differential gain of 10 V/V. What is the input common-mode range and the input differential resistance? Ignore base currents except when calculating Rid . If Rid is to be increased by a factor of 4 while the gain and VICM remain unchanged, what must I and RC be changed to? 13.82 It is required to find the input resistance and the voltage gain of the input stage shown in Fig. 13.37. Let VICM 0.8 V so that the Q3 −Q4 pair is off. Assume that Q5 supplies 8 μA, that each of Q7 to Q10 is biased at 8 μA, and that all four cascode transistors are operating in the active mode. The input resistance of the second stage of the op amp is 1.5 M0003. The emitter-degeneration resistances are R7 = R8 = 22 k0003, and R9 = R10 = 33 k0003. [Hint: Refer to Fig. 13.38.] D *13.83 Consider the equivalent half-circuit shown in Fig. 13.38. Assume that in the original circuit, Q1 is biased at a current I, Q7 and Q9 are biased at 2I, the dc voltage drop across R7 is 0.2 V, and the dc voltage drop across R9 is 0.3 V. Find the output resistance in terms of I, and hence find the open-circuit voltage gain (i.e., the voltage gain for RL = ∞). Now with RL connected, find the voltage gain in terms of
0007 IRL . For RL = 1 M0003, find I that will result in the voltage gains of 150 V/V and 300 V/V. *13.84 (a) For the circuit in Fig. 13.39, show that the loop gain of the common-mode feedback loop is Aβ 0007
Ro9 0005 Ro7 re7 + R7
Recall that the CMF circuit responds only to the average voltage VCM of its two input voltages and realizes the transfer characteristic VB = VCM + 0.4. Ignore the loading effect of the CMF circuit on the collectors of the cascode transistors. (b) For the values in Example 13.8, calculate the loop gain Aβ. (c) In Example 13.8, we found that with the CMF absent, a current mismatch I = 0.3 μA gives rise to VCM = 2.5 V. Now, with the CMF present, use the value of loop gain found in (b) to calculate the expected VCM and compare to the value found by a different approach in Example 13.8. [Hint: Recall that negative feedback reduces change by a factor equal to (1 + Aβ).] 13.85 The output stage in Fig. 13.41 operates at a quiescent current IQ of 0.6 mA. The maximum current iL that the stage can provide in either direction is 12 mA. Also, the output stage is equipped with a feedback circuit that maintains a minimum current of IQ /2 in the inactive output transistor. Also, VCC = 3 V. (a) What is the allowable range of v O ? (b) For iL = 0, what is the output resistance of the op amp? (c) If the open-loop gain of the op amp is 100,000 V/V, find the closed-loop output resistance obtained when the op amp is connected in the unity-gain voltage follower configuration, with iL = 0. (d) If the op amp is sourcing a load current iL = 12 mA, find iP , iN , and the open-loop output resistance. (e) Repeat (d) for the case of the open-loop op amp sinking a load current of 12 mA. 13.86 It is required to derive the expressions in Eqs. (13.130) and (13.131). Toward that end, first find v B7 in terms of v BEN and hence iN . Then find v B6 in terms of iP . For the latter purpose note that Q4 measures v EBP and develops a current 0007 i4 = v EBP − v EB4 /R4 . This current is supplied to the series connection of Q5 and R5 where R5 = R4 . In the expression you
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Problems 1085
I ISP = SN IS4 IS5 to express v B6 in terms of iP and ISN . Now with v B6 and v B7 determined, find iC6 and iC7 .
D 13.88 For the output stage in Fig. 13.43, find the current IREF that results in a quiescent current IQ = 0.6 mA. Assume that I = 12 μA, QN has eight times the area of Q10 , and Q7 has four times the area of Q11 . What is the minimum current in QN and QP ?
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PROBLEMS
13.87 It is required to derive the expression for v E in Eq. (13.132). Toward that end, note from the circuit in
Fig. 13.43 that v E = v EB7 + v BEN and note that QN conducts a current iN and Q7 conducts a current iC7 given by Eq. (13.131).
CHAPTER 13
obtain for v B6 , use the relationship
PROBLEMS Computer Simulation Problems Problems identified by the Multisim/PSpice icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as gate noise margins and propagation delays. Instructions to assist in setting up PSpice and Multisim simulations for all the indicated problems can be found in the corresponding files on the website. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
D 14.6 Find the PUN that corresponds to the PDN shown in Fig. P14.6, and hence the complete CMOS logic circuit. What is the Boolean function realized?
Y
A
Section 14.1: CMOS Logic-Gate Circuits
B
C
D 14.1 Consider MOS transistors fabricated in a 65-nm 2 2 process for which μn Cox = 470 μA/V , μp Cox = 190 μA/V , Vtn = −Vtp = 0.35 V, and VDD = 1 V.
Figure P14.6
(a) Find Ron of an NMOS transistor with W/L = 1.5. (b) Find Ron of a PMOS transistor with W/L = 1.5. (c) If Ron of the PMOS device is to be equal to that of the NMOS device in (a), what must (W/L)p be?
D 14.7 Find the PDN that corresponds to the PUN shown in Fig. P14.7, and hence the complete CMOS logic circuit. What is the Boolean function realized?
D 14.2 The CMOS inverter of Fig. 14.2(b) is implemented 2 in a 0.13-μm process for which μn Cox = 500 μA/V , μp Cox = 2 125 μA/V , Vtn = −Vtp = 0.4 V, and VDD = 1.2 V. The NMOS transistor has (W/L)n = 1.5.
VDD
A
(a) What must (W/L)p be if QN and QP are to have equal Ron resistances? (b) Find the value of Ron . D 14.3 Give the CMOS circuit that realizes a three-input NOR gate.
B
C
D
D 14.4 Give the CMOS circuit for a three-input NAND gate. D 14.5 Find the PUN that corresponds to the PDN shown in Fig. P14.5, and hence the complete CMOS logic circuit. What is the Boolean function realized?
Y
Figure P14.7
Y
D 14.8 Give the CMOS realization for the Boolean function B A
Y = (A + B)(C + D)
C
Figure P14.5
D 14.9 Find the PDN that is the dual of the PUN in Fig. 14.10(a) and hence give a CMOS realization of the exclusive-OR (XOR) function.
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Problems 1157
How many transistors are required? Explore the possibility of reducing the number of the transistors required.
D 14.12 Sketch a CMOS logic circuit that realizes the function Y = ABC + A B C. D 14.13 It is required to design a CMOS logic circuit that realizes a three-input, even-parity checker. Specifically, the output Y is to be low when an even number (0 or 2) of the inputs A, B, and C are high. (a) Give the Boolean function Y . (b) Sketch a PDN directly from the expression for Y . Note that it requires 12 transistors in addition to those in the inverters. (c) From inspection of the PDN circuit, reduce the number of transistors to 10 (not counting those in the inverters). (d) Find the PUN as a dual of the PDN in (c), and hence the complete realization. D 14.14 Give a CMOS logic circuit that realizes the function of a three-input, odd-parity checker. Specifically, the output is to be high when an odd number (1 or 3) of the inputs are high. Attempt a design with 10 transistors (not counting those in the inverters) in each of the PUN and the PDN. D 14.15 Design a CMOS full-adder circuit with inputs A, B, and C, and two outputs S and C0 such that S is 1 if one or three inputs are 1, and C0 is 1 if two or more inputs are 1.
Section 14.2: Digital Logic Inverters 14.16 A particular logic inverter is specified to have VIL = 0.9 V, VIH = 1.2 V, VOL = 0.2 V, and VOH = 1.8 V. Find the high and low noise margins, NMH and NML . 14.17 The voltage-transfer characteristic of a particular logic inverter is modeled by three straight-line segments in the manner shown in Fig. 14.13. If VIL = 1.2 V, VIH = 1.3 V, VOL = 0.4 V, and VOH = 1.8 V, find: (a) the noise margins
14.18 For a particular inverter design using a power supply VDD , VOL = 0.1VDD , VOH = 0.8VDD , VIL = 0.4VDD , and VIH = 0.6 VDD . What are the noise margins? What is the width of the transition region? For a minimum noise margin of 0.4 V, what value of VDD is required? 14.19 A logic-circuit family that used to be very popular is transistor–transistor logic (TTL). The TTL logic gates and other building blocks are available commercially in small-scale-integrated (SSI) and medium-scale-integrated (MSI) packages. Such packages can be assembled on printed-circuit boards to implement a digital system. The device data sheets provide the following specifications of the basic TTL inverter (of the SN7400 type): Logic-1 input level required to ensure a logic-0 level at the output: MIN (minimum) 2 V Logic-0 input level required to ensure a logic-1 level at the output: MAX (maximum) 0.8 V Logic-1 output voltage: MIN 2.4 V, TYP (typical) 3.3 V Logic-0 output voltage: TYP 0.22 V, MAX 0.4 V Logic-0-level supply current: TYP 3 mA, MAX 5 mA Logic-1-level supply current: TYP 1 mA, MAX 2 mA (a) Find the worst-case values of the noise margins. (b) Assuming that the inverter is in the logic-1 state 50% of the time and in the logic-0 state 50% of the time, find the average power dissipation in a typical circuit. The power supply is 5 V. 14.20 Consider an inverter implemented as in Fig. 14.17(a). Let VDD = 2.5 V, R = 2 k0003, Ron = 100 0003, VIL = 0.8 V, and VIH = 1 V. (a) Find VOL , VOH , NMH , and NML . (b) The inverter is driving N identical inverters. Each of these load inverters, or fan-out inverters as they are usually called, is specified to require an input current of 0.2 mA when the input voltage (of the fan-out inverter) is high and zero current when the input voltage is low. Noting that the input currents of the fan-out inverters will have to be supplied through R of the driving inverter, find the resulting value of VOH and of NMH as a function of the number of fan-out inverters N. Hence find the maximum value N can have while the inverter is still providing an NMH value approximately equal to its NML .
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PROBLEMS
D 14.11 Sketch a CMOS logic circuit that realizes the function Y = AB + A B. This is called the equivalence or coincidence function.
(b) the value of VM (c) the voltage gain in the transition region
CHAPTER 14
D 14.10 Provide a CMOS logic gate circuit that realizes the function Y = ABC + ABC + ABC
CHAPTER 14
PROBLEMS
1158 Chapter 14 CMOS Digital Logic Circuits (c) Find the power dissipation in the inverter in the two cases: (i) the output is low, and (ii) the output is high and driving the maximum fan-out found in (b). 14.21 For an inverter employing a 2-V supply, suggest an ideal set of values for VM , VIL , VIH , VOL , VOH , NML , NMH . Also, sketch the VTC. What value of voltage gain in the transition region does your ideal specification imply? 14.22 For a particular inverter, the basic technology used provides an inherent limit to the small-signal, low-frequency voltage gain of 50 V/V. If, with a 2-V supply, the values of VOL and VOH are ideal, but VM = 0.4VDD , what are the best possible values of VIL and VIH that can be expected? What are the best possible noise margins you could expect? Find the large-signal voltage gain, where the gain is defined by (VOH − VOL )/(VIL − VIH ). (Hint: Use straight-line approximations for the VTC.) *14.23 A logic-circuit type intended for use in a digital-signal-processing application in a newly developed hearing aid can operate down to single-cell supply voltages of 1.2 V. If for its inverter, the output signals swing between 0 and VDD , the “gain-of-one” points are separated by less than 13 VDD , and the noise margins are within 30% of one another, what ranges of values of VIL , VIH , VOL , VOH , NML , and NMH can you expect for the lowest possible battery supply? D 14.24 Design the inverter circuit in Fig. 14.12(a) to provide VOH = 1.2 V, VOL = 50 mV, and so that the current drawn from the supply in the low-output state is 30 μA. The 2 transistor has Vt = 0.4 V, μn Cox = 500 μA/V , and λ = 0. Specify the required values of VDD , RD , and W/L. How much power is drawn from the supply when the output is high? When the output is low?
VOL = 50 mV, and the power dissipation in the low-output state = 60 μW. The transistor available has Vt = 0.4 V, 2 μn Cox = 500 μA/V , and λ = 0. Specify the required values of VDD , RD , and W/L. What are the values obtained for VIL , VM , VIH , NML , and NMH ? D 14.27 Refer to the analysis of the resistive-load MOS inverter in Example 14.2 and utilize the expressions derived there for the various inverter parameters. For a technology for which Vt = 0.3VDD , it is required to design the inverter to obtain VM = VDD /2. In terms of VDD , what is the required value of the design parameter Vx ? What values are obtained for VOH , VOL , VIL , VIH , NMH , and NML , in terms of VDD ? Give numerical values for the case VDD = 1.2 V. Now, express the power dissipated in the inverter in its low-output state 0004 2 in terms of the transistor’s W/L ratio. Let kn = 500 μA/V . If the power dissipation is to be limited to approximately 100 μW, what W/L ratio is needed and what value of RD corresponds? 14.28 An earlier form of logic circuits, now obsolete, utilized NMOS transistors only and was appropriately called NMOS logic. The basic inverter, shown in Fig. P14.28, utilizes an NMOS driver transistor Q1 and another NMOS transistor Q2 , connected as a diode, forms the load of the inverter. Observe that Q2 operates in saturation at all times. Assume Vt1 = Vt2 = Vt , λ1 = λ2 = 0, and denote kn1 /kn2 by kr . Also neglect the body effect in Q2 (note that the body of Q2 , not shown, is connected to ground).
VDD i
0003 Q2
14.25 For the current-steering circuit in Fig. 14.19, VCC = 2 V, IEE = 0.5 mA, find the values of RC1 and RC2 to obtain a voltage swing of 0.5 V at each output. What are the values realized for VOH and VOL ? D 14.26 Refer to the analysis of the resistive-load MOS inverter in Example 14.2 and utilize the expressions derived there for the various inverter parameters. Design the circuit to satisfy the following requirements: VOH = 1.2 V,
0002 0003 0003 vI 0002
Q1 0002
Figure P14.28
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Problems 1159
14.30 Repeat Example 14.3 for a pseudo-NMOS inverter fabricated in a 0.13-μm CMOS technology for which VDD = 2 1.2 V, |Vt |= 0.4 V, kn /kp = 5, and kn = 500 μA/V . Find VOH , VOL , IDD , and the average power dissipation Pav . Also, use the expression given in Exercise 14.5 to evaluate VM .
14.33 For a technology in which Vtn = 0.3VDD , show that the maximum current that the inverter can sink while its low-output level does not exceed 0.1 VDD is 0004 2 0004 2 0.065 kn (W/L)n VDD . For VDD = 1.3 V, kn = 500 μA/V , find (W/L)n that permits this maximum current to be 0.1 mA. 2
14.34 A CMOS inverter for which kn = 5kp = 200 μA/V and Vt = 0.5 V is connected as shown in Fig. P14.34 to a sinusoidal signal source having a Th´evenin equivalent voltage of 0.1-V peak amplitude and resistance of 100 k0003. What signal voltage appears at node A with v I = +1.5 V? With v I = –1.5 V?
QP 100 k vI QN
A
100-mV signal
Section 14.3: The CMOS Inverter 14.31 Consider a CMOS inverter fabricated in a 65-nm CMOS process for which VDD = 1 V, Vtn = −Vtp = 0.35 V, 2 and μn Cox = 2.5μp Cox = 470 μA/V . In addition, QN and QP have L = 65 nm and (W/L)n = 1.5. (a) Find Wp that results in VM = VDD /2. What is the silicon area utilized by the inverter in this case? (b) For the matched case in (a), find the values of VOH , VOL , VIH , VIL , NML , and NMH . (c) For the matched case in (a), find the output resistance of the inverter in each of its two states. 14.32 Consider a CMOS inverter fabricated in a 0.25-μm CMOS process for which VDD = 2.5 V, Vtn = −Vtp = 2 0.5 V, and μn Cox = 3.5 μp Cox = 115 μA/V . In addition, QN
Figure P14.34
D 14.35 There are situations in which QN and QP of the CMOS inverter are deliberately mismatched to realize a certain desired value for VM . Show that the value required of the parameter r of Eq. (14.40) is given by r=
VM − Vtn VDD − Vtp − VM
For a 0.13-μm process characterized by Vtn = −Vtp = 0.4 V, VDD = 1.3 V, and μn = 4μp , find the ratio Wp /Wn required to obtain VM = 0.6VDD .
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
14.29 For the pseudo-NMOS inverter analyzed in Example 14.3 and in Exercise 14.5, what is the value of r that results in VM = VDD /2 = 0.9 V?
and QP have L = 0.25 μm and (W/L)n = 1.5. Investigate the variation of VM with the ratio Wp /Wn . Specifically, calculate VM for (a) Wp = 3.5W n (the matched case), (b) Wp = Wn (the minimum-size case); and (c) Wp = 2W n (a compromise case). For cases (b) and (c), estimate the approximate reduction in NML and silicon area relative to the matched case (a).
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(a) Sketch i–v for Q2 and hence show that for vI low (i.e., vI < Vtn ), the output voltage will be VOH = VDD −Vt . (Hint: Although Q2 will be conducting zero current, it will have a voltage drop of Vt .) (b) Taking VIL as the value of vI at which Q1 begins to conduct and vO begins to fall, find VIL . (c) Find the relationship between vO and vI in the transition region. This is the region for which vI > Vt and both Q1 and Q2 are operating in saturation. Show that the relationship is linear and find its slope. (d) If VOL 0002 0 V, find the current IDD drawn from VDD and hence the average power dissipation in the inverter, assuming that it spends half the time in each of its two states. (e) Find numerical values for all the parameters asked for above for the case VDD = 1.8 V, Vt = 0.5 V, (W/L)1 = 5, 2 (W/L)2 = 15 , and μn Cox = 300 μA/V .
CHAPTER 14
PROBLEMS
1160 Chapter 14 CMOS Digital Logic Circuits 14.36 Consider the CMOS inverter of Fig. 14.22 with QN and QP matched and with the input v I rising slowly from 0 to VDD . At what value of v I does the current flowing through QN and QP reach its peak? Give an expression for the peak current, 0004 2 neglecting λn and λp . For kn = 500 μA/V , (W/L)n = 1.5, VDD = 1.3 V, and Vtn = 0.4 V, find the value of the peak current. 14.37 Repeat Example 14.4 for a CMOS inverter fabricated in a 0.13-μm process for which VDD = 1.3 V, Vtn =| Vtp | = 2 0.4 V, μn = 4μp , and μn Cox = 500 μA/V . In addition, QN and QP have L = 0.13 μm and (W/L)n = 1.5. For part (a) use VM = VDD /2 = 0.65 V.
S
C
R
Figure P14.39
14.40 For the inverter circuit in Fig. P14.40, let vI go from VDD to 0 V at t = 0. At t = 0+, vO = VOL . Find expressions for VOH , vO (t), and tPLH . If R = 10 k0003, what is the largest value of C that ensures that tPLH is at most 100 ps?
VDD
Section 14.4: Dynamic Operation of the CMOS Inverter 14.38 For the circuit shown in Fig. P14.38, let switch S open at t = 0. (a) Give the expression for vO (t). (b) For I = 1 mA and C = 10 pF, find the time at which vO reaches 1 V.
vI C
Figure P14.40
I
C
R
S
Figure P14.38
14.39 For the circuit in Fig. P14.39, let C be charged to 10 V and switch S closes at t = 0. (a) Give the expression for vO (t). (b) For C = 100 pF and R = 1 k0003, find tPHL and tf .
14.41 For the inverter of Fig. 14.18(a) with a capacitance C connected between the output and ground, let the on-resistance of PU be 2 k0003 and that of PD be 1 k0003. If the capacitance C = 50 fF, find tPLH , tPHL , and tP . 14.42 A logic inverter is implemented using the arrangement of Fig. 14.18 with switches having Ron = 2 k0003, VDD = 1.8 V, and VIL = VIH = VDD /2. (a) Find VOL , VOH , NML , and NMH . (b) If v I rises instantaneously from 0 V to +1.8 V and assuming the switches operate instantaneously—that is, at t = 0, PU opens and PD closes—find an expression for v O (t), assuming that a capacitance C is connected between the output node and ground. Hence find the high-to-low
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 1161
(a) If the current available to charge a load capacitance is half as large as that available to discharge the capacitance, what do you expect tPLH and tPHL to be? (b) If when an external capacitive load of 0.5 pF is added at the inverter output, its propagation delays increase by 50%, what do you estimate the normal combined capacitance of inverter output and input to be? (c) If without the additional 0.5-pF load connected, the load inverter is removed and the propagation delays were observed to decrease by 40%, estimate the two components of the capacitance found in (b): that is, the component due to the inverter output and other associated parasitics, and the component due to the input of the load inverter. *14.44 Consider an inverter for which tPLH , tPHL , tTLH , and tTHL are 20 ns, 10 ns, 30 ns, and 15 ns, respectively. The rising and falling edges of the inverter output can be approximated by linear ramps. Also, for simplicity, we define tTLH to be 0% to 100% (rather than 10% to 90%) rise time, and similarly for tTHL . Two such inverters are connected in tandem and driven by an ideal input having zero rise and fall times. Calculate the time taken for the output voltage to complete its excursion for (a) a rising input and (b) a falling input. What is the propagation delay for the inverter? 14.45 For a CMOS inverter fabricated in a 0.13-μm 0004 0004 process with VDD = 1.2 V, Vtn = −Vtp = 0.4 V, kn = 4kp = 2 430 μA/V , and having (W/L)n = 1.5 and (W/L)p = 3, find tPHL , tPLH , and tP when the equivalent load capacitance C = 10 fF. Use the method of average currents. D 14.46 Consider a matched CMOS inverter fabricated in the 0.13-μm process specified in Problem 14.45. If C = 30 fF,
14.47 For the CMOS inverter in Exercise 14.11 use the method of equivalent resistance to determine tPHL , tPLH , and tP . 14.48 Use the method of equivalent resistance to determine the propagation delay of a minimum-size inverter, that is, one for which (W/L)n = (W/L)p = 1, designed in a 0.13-μm technology. The equivalent load capacitance C = 20 fF. D 14.49 Use the method of equivalent resistance to design an inverter to be fabricated in a 0.13-μm technology. It is required that for C = 10 fF, tPLH = tPHL , and tP ≤ 50 ps. 14.50 The method of average currents yields smaller values for tPHL and tPLH than those obtained by the method of equivalent resistances. Most of this discrepancy is due to the fact that the formula we derived for Iav does not take into account velocity saturation. As will be seen in Section 15.1.2, velocity saturation reduces the current significantly. Using the results in Example 14.6, by what factor do you estimate the current reduction to be in the NMOS transistor? Since tPLH does not change, what do you conclude about the effect of velocity saturation on the PMOS transistor in this technology? 14.51 Use the method of average currents to estimate tPHL , tPLH , and tP of a CMOS inverter fabricated in a 65-nm process for which Vtn = |Vtp | = 0.35 V, VDD = 1 2 2 V, μn Cox = 470 μA/V , and μp Cox = 190 μA/V . The inverter has (W/L)n = 1.5 and (W/L)p = 3, and the total capacitance at the inverter output node is 10 fF. Also, find the theoretical maximum frequency at which this inverter can be operated. 14.52 Find the propagation delay for a minimum-size 0004 0004 2 inverter for which kn = 4kp = 380 μA/V and (W/L)n = (W/L)p = 0.27 μm/0.18 μm, VDD = 1.8 V, Vtn = –Vtp = 0.5 V, and the capacitance is roughly 4 fF/μm of device width plus 2 f F/device. There is an additional load capacitance of 5 fF. What does tP become if the design is changed to a matched one? Use the method of average current.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
14.43 In a particular logic family, the standard inverter, when loaded by a similar circuit, has a propagation delay specified to be 0.9 ns:
use the method of average currents to determine the required (W/L) ratios so that tP ≤ 80 ps.
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propagation delay (tPHL ) for C = 0.1 pF. Also find tTHL (see Fig. 14.29). (c) Repeat (b) for v I falling instantaneously from +1.8 V to 0 V. Again assume that PD opens and PU closes instantaneously. Find an expression for v O (t), and hence find tPLH and tTLH .
CHAPTER 14
PROBLEMS
1162 Chapter 14 CMOS Digital Logic Circuits 14.53 A matched CMOS inverter fabricated in a process for (e) Compare the tP values in (c) and (d) for the two extreme 2 2 2 cases: which Cox = 3.7 f F/μm, μn Cox = 180 μA/V, μp Cox = 45 μA/V, Vtn = – Vtp = 0.7 V, and VDD = 3.3 V, uses Wn = 0.75 μm and (i) Cw = 0 Ln = Lp = 0.5 μm. The overlap capacitance and the effective drain–body capacitance per micrometer of gate width are 0.4 (ii) Cw Cn f F and 1.0 f F, respectively. The wiring capacitance is Cw = 2 f F. If the inverter is driving another identical inverter, find What do you conclude about the selection of Wp /Wn ? tPLH , tPHL , and tP . For how much additional capacitance load does the propagation delay increase by 50%?
Section 14.5: Transistor Sizing 14.54 An inverter whose equivalent load capacitance C is composed of 15 fF contributed by the inverter transistors, and 45 fF contributed by the wiring and other external circuitry, has been found to have a propagation delay of 80 ps. By what factor must (W/L)n and (W/L)p be increased so as to reduce tP to 40 ps? By what factor is the inverter area increased? D *14.55 In this problem we investigate the effect of the selection of the ratio Wp /Wn on the propagation delay of an inverter driving an identical inverter, as in Fig. 14.32. Assume all transistors have the same L. (a) Noting that except for Cw each of the capacitances in Eqs. (14.58) and (14.59) is proportional to the width of the relevant transistor, show that C can be expressed as 0006 0007 Wp C = Cn 1 + + Cw Wn where Cn is determined by the NMOS transistors. (b) Using the equivalent resistances RN and RP , show that for (W/L)n = 1, 3
tPHL = 8.625 × 10 C 3
tPLH =
20.7 × 10 C Wp /Wn
(c) Use the results of (a) and (b) to determine tP in the case Wp = Wn , in terms of Cn and Cw . (d) Use the results of (a) and (b) to determine tP in the matched case: that is, when Wp /Wn is selected to yield tPHL = t PLH .
D 14.56 Consider the CMOS gate shown in Fig. 14.9. Specify W/L ratios for all transistors in terms of the ratios n and p of the basic inverter, such that the worst-case tPHL and tPLH of the gate are equal to those of the basic inverter. D 14.57 Find appropriate sizes for the transistors used in the exclusive-OR circuit of Fig. 14.10(b). Assume that the basic inverter has (W/L)n = 0.20 μm/0.13 μm and (W/L)p = 0.40 μm/0.13 μm. What is the total area, including that of the required inverters? 14.58 Consider a four-input CMOS NAND gate for which the transient response is dominated by a fixed-size capacitance between the output node and ground. Compare the values of tPLH and tPHL , obtained when the devices are sized as in Fig. 14.35, to the values obtained when all n-channel devices have W/L = n and all p-channel devices have W/L = p. 14.59 Figure P14.59 shows two approaches to realizing the OR function of six input variables. The circuit in Fig. P14.59(b), though it uses additional transistors, has in fact less total area and lower propagation delay because it uses NOR gates with lower fan-in. Assuming that the transistors in both circuits are properly sized to provide each gate with a current-driving capability equal to that of the basic matched inverter, find the number of transistors and the total area of each circuit. Assume the basic inverter to have a (W/L)n ratio of 0.20 μm/0.13 μm and a (W/L)p ratio of 0.40 μm/0.13 μm. *14.60 Consider the two-input CMOS NOR gate of Fig. 14.7 whose transistors are properly sized so that the current-driving
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 1163
…
Y
A1
A2
…
A6
Y
A1
A2
…
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A1 A6 (a) A1
PROBLEMS
A2 A3 A4
A6
A5 A6 (b) Figure P14.59
capability in each direction is equal to that of a matched inverter. For Vt = 1 V and VDD = 5 V, find the gate threshold in the cases for which (a) input terminal A is connected to ground and (b) the two input terminals are tied together. Neglect the body effect in QPB . 14.61 A chain of four inverters whose sizes are scaled by a factor x is used to drive a load capacitance CL = 1200 C, where C is the input capacitance of the standard inverter (which is the first in the chain). (a) Without increasing the number of inverters in the chain, find the optimum value of x that results in minimizing the overall delay tP and find the resulting value of tP in terms of the time constant CR, where R is the output resistance of the standard inverter. (b) If you are allowed to increase the number of inverters in the chain, what is the number of inverters and the value of x that result in minimizing the total path delay tP ? What is the value of tP achieved? 14.62 The purpose of this problem is to find the values of n and x that result in minimum path delay tP for the inverter chain in Fig. 14.37(c). (a) Show that tP = τtotal = (n − 1)xRC +
1 x
n−1
RCL
(b) Differentiate the expression for tP in (a) relative to x and set the derivative to zero. Thus show that the first condition for optimality is n
x =
CL C
(c) Differentiate the expression for tP in (a) relative to n and set the derivative to zero. Thus show that the second condition for optimality is 0006 x
n
C CL
0007 = ln x
(d) Combine the expressions in (b) and (c) to show that the value of x for minimum overall delay is x=e
Section 14.6: Power Dissipation 14.63 An IC inverter fabricated in a 0.18-μm CMOS process is found to have a load capacitance of 10 fF. If the inverter is operated from a 1.8-V power supply, find the energy needed to charge and discharge the load capacitance. If the IC chip has 2 million of these inverters operating at an average switching frequency of 1 GHz, what is the power dissipated in the chip? What is the average current drawn from the power supply?
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 14
PROBLEMS
1164 Chapter 14 CMOS Digital Logic Circuits 14.64 Consider a logic inverter of the type shown in Fig. 14.18. Let VDD = 1 V, and let a 5-fF capacitance be connected between the output node and ground. If the inverter is switched at the rate of 2 GHz, determine the dynamic power dissipation. What is the average current drawn from the dc power supply? 14.65 In a particular logic-circuit technology, operating with a 3.3-V supply, the basic inverter draws (from the supply) a current of 60 μA in one state and 0 μA in the other. When the inverter is switched at the rate of 100 MHz, the average supply current becomes 150 μA. Estimate the equivalent capacitance at the output node of the inverter. 14.66 A collection of logic gates for which the static power dissipation is zero, and the dynamic power dissipation is 10 mW is operating at 50 MHz with a 5-V supply. By what fraction could the power dissipation be reduced if operation at 3.3 V were possible? If the frequency of operation is reduced by the same factor as the supply voltage (i.e., 3.3/5), what additional power can be saved? 14.67 A particular logic gate has tPLH and tPHL of 30 ns and 50 ns, respectively, and dissipates 1 mW with output low and 0.6 mW with output high. Calculate the corresponding delay–power product (under the assumption of a 50% duty-cycle signal and neglecting dynamic power dissipation). D *14.68 We wish to investigate the design of the inverter shown in Fig. 14.17(a). In particular, we wish to determine the value for R. Selection of a suitable value for R is determined by two considerations: propagation delay and power dissipation. (a) Show that if v I changes instantaneously from high to low and assuming that the switch opens instantaneously, the output voltage obtained across a load capacitance C will be 0002
0003
v O (t) = VOH − VOH − VOL e−t/τ1 where τ1 = CR. Hence show that the time required for 0002 0003 v O (t) to reach the 50% point, 21 VOH + VOL , is tPLH = 0.69CR
(b) Following a steady state, if v I goes high and assuming that the switch closes immediately and has the equivalent circuit in Fig. 14.17(c), show that the output falls exponentially according to 0003
0002
v O (t) = VOL + VOH − VOL e−t/τ2 0002 0003 where τ2 = C R Ron 0002 CRon for Ron R. Hence show that the time for v O (t) to reach the 50% point is tPHL = 0.69CRon (c) Use the results of (a) and (b) to obtain the inverter propagation delay, defined as the average of tPLH and tPHL as tP 0002 0.35CR
for Ron R
(d) Show that for an inverter that spends half the time in the logic-0 state and half the time in the logic-1 state, the average static power dissipation is 2
P=
1 VDD 2 R
(e) Now that the trade-offs in selecting R should be clear, show that, for VDD = 5 V and C = 10 pF, to obtain a propagation delay no greater than 5 ns and a power dissipation no greater than 15 mW, R should be in a specific range. Find that range and select an appropriate value for R. Then determine the resulting values of tP and P. D 14.69 A logic-circuit family with zero static power dissipation normally operates at VDD = 2.5 V. To reduce its dynamic power dissipation, operation at 1.8 V is considered. It is found, however, that the currents available to charge and discharge load capacitances also decrease. If current is (a) 2 proportional to VDD or (b) proportional to VDD , what reductions in maximum operating frequency do you expect in each case? What fractional change in delay–power product do you expect in each case?
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 1165
1 ns each. Find Ipeak . To determine the energy drawn from the supply per transition, assume that the current pulse can be approximated by a triangle with a base corresponding to the time for the rising or falling edge to go from Vt to VDD −Vt , and the height equal to Ipeak . Also, determine the power dissipation that results when the inverter is switched at 100 MHz.
CHAPTER 14
14.70 In this problem we estimate the CMOS inverter power dissipation resulting from the current pulse that flows in QN and QP when the input pulse has finite rise and fall times. Refer to Fig. 14.39 and let Vtn = −Vtp = 0.5 V, VDD = 1.8 V, and 2 kn = kp = 450 μA/V . Let the input rising and falling edges be linear ramps with the 0-to-VDD and VDD -to-0 transitions taking
PROBLEMS
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 1227
0002
To reduce the device count, two other forms of static CMOS, namely, pseudo-NMOS and pass-transistor logic (PTL), are employed in special applications as supplements to standard CMOS.
0002
Pseudo-NMOS utilizes the same PDN as in standard CMOS logic but replaces the PUN with a single PMOS transistor whose gate is grounded and thus is permanently on. Unlike standard CMOS, pseudo-NMOS is a ratioed form of logic in which VOL is determined by the ratio r of kn to kp . Normally, r is selected in the range of 4 to 10 and its value determines the noise margins.
0002
0002
Pseudo-NMOS has the disadvantage of dissipating static power when the output of the logic gate is low. Static power can be eliminated by turning the PMOS load on for only a brief interval, known as the precharge interval, to charge the capacitance at the output node to VDD . Then the inputs are applied, and depending on the input combination, the output node either remains high or is discharged through the PDN. This is the essence of dynamic logic. Pass-transistor logic utilizes either single NMOS transistors or CMOS transmission gates to implement a network of switches that are controlled by the input logic variables. Switches implemented by single NMOS transistors, though simple, result in the reduction of VOH from VDD to VDD – Vt .
0002
The CMOS transmission gate, composed of the parallel connection of an NMOS and a PMOS transistor, is a very effective switch in both analog and digital applications. It passes the entire input signal swing, 0 to VDD . As well, it has an almost constant on-resistance over the full output range.
0002
A particular form of dynamic logic circuits, known as Domino logic, allows the cascading of dynamic logic gates.
0002
Emitter-coupled logic (ECL) is the fastest commercially available logic-circuit family. It achieves its high speed of operation by avoiding transistor saturation and by utilizing small logic-signal swings. Its high speed of operation is achieved at the expense of large power dissipation, which limits its application to highly specialized applications.
0002
The ECL gate provides two complementary outputs, realizing the OR and NOR functions. The outputs of ECL gates can be wired together to realize the OR function of the individual output variables.
0002
BiCMOS combines the low power and wide noise margins of CMOS with the high current-driving capability (and thus the short gate delays) of BJTs. However, the added processing complexity (over that required for CMOS) has limited its use to specialized applications.
PROBLEMS Section 15.1: Implications of Technology Scaling: Issues in Deep-Submicron Design 15.1 A chip with a certain area designed using the 5-μm process of the late 1970s contains 20,000 transistors. What does Moore’s law predict the number of transistors to be on a chip of equal area fabricated using the 32-nm process of 2013? 15.2 Consider the scaling from a 0.13-μm process to a 65-nm process. (a) Assuming VDD and Vt are scaled by the same factor as the device dimensions (S = 2), find the factor by which tP ,
the maximum operating speed, Pdyn , power density, and PDP decrease (or increase)? (b) Repeat (a) for the situation in which VDD and Vt remain unchanged. 15.3 For a 65-nm technology, VDSsat for minimum-length NMOS devices is measured to be 0.25 V and that for minimum-length PMOS devices 0.45 V. What do you estimate the effective values of μn and μp to be? Also find the values of Ecr for both device polarities. 15.4 Consider NMOS and PMOS transistors with minimum channel length fabricated in a 0.13-μm CMOS process. 2 If the effective values of μn and μp are 350 cm /V · s and
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 15
PROBLEMS
1228 Chapter 15 Advanced Topics in Digital Integrated-Circuit Design 2
150 cm /V · s, respectively, find the expected values of VDSsat for both device polarities. 15.5 (a) Show that for a short-channel NMOS transistor, the ratio of the current IDsat obtained at v GS = VDD to the current obtained if velocity saturation were absent is given by 0002 0003 1 2VDSsat VDD − Vt − VDSsat IDsat 2 = 0007 2 ID VDD − Vt (b) Find the ratio in (a) for a transistor fabricated in a 65-nm process with L = 65-nm, Vt = 0.35 V, VDSsat = 0.25 V, and VDD = 1.0 V. 15.6 (a) Consider a CMOS inverter fabricated in a deep-submicron technology utilizing transistors with the minimum allowed channel length and having an equivalent load capacitance C. Let v I rise instantaneously to VDD and assume that QP turns off and QN turns on immediately. Ignoring channel-length modulation, that is, λ = 0, and assuming QN operates in the velocity-saturation region, show that CVDD tPHL = 2IDsat (b) Using the equivalent resistance of QN show that tPHL = 0.69C
12.5 × 10 (W/L)n
the static power dissipation increase? Assume n = 2. Repeat for a reduction in Vt by 0.2 V. What do you conclude about the selection of a value of Vt in process design? 15.9 Measurements on a MOSFET operating in the subthreshold conduction region indicate that the current changes by a factor of 10 for every 80-mV change in vGS and that iD = 20 nA at vGS = 0.16 V. (a) Find the value of iD at vGS = 0. (b) For a chip having 1 billion transistors, find the current drawn from the 1-V supply VDD as a result of subthreshold conduction. Hence, estimate the resulting static power dissipation. 2
15.10 An NMOS transistor with kn = 0.4 mA/V and a nominal Vtn of 0.4 V is to operate in saturation at ID = 0.2 mA. (a) If Vtn can vary by as much as ±10%, what is the expected range of ID obtained? (b) If the transistor is used to discharge a 100-fF load capacitance, what is the expected variation in delay time, assuming that the output voltage is to change by 0.1 V? 15.11 An interconnect wire with a length L, a width W, and a thickness T has a resistance R given by
3
(c) If the formulas in (a) and (b) are to yield the same result, find VDSsat for the NMOS transistor for a 0.13-μm technology characterized by VDD = 1.2 V, Vt = 0.4 V, and 2 μn Cox = 325 μA/V . D 15.7 (a) For a CMOS inverter fabricated in a deep-submicron technology with Ln = Lp = the minimum allowed channel length, it is required to select Wp /Wn so that tPHL = tPLH . This0006 can0006be achieved by making IDsat of QN equal to IDsat of QP at 0006v GS 0006 = VDD . Show that Wp /Wn is given by 1 Wp μn VDSsatn VDD − Vtn − 2 VDSsatn 0006 0006 = 0006 0006 10006 0006 Wn μp 0006VDSsatp 0006 VDD − 0006Vtp 0006 − 0006VDSsatp 0006 2 (b) Find the required Wp /Wn for a 65-nm technology for which μn /μ0006p = 4, 0006VDD = 1.0 V, Vtn = −Vtp = 0.35 V, VDSsatn = 0.25 V, and 0006VDSsatp 0006 = 0.45 V. D 15.8 The current IS in the subthreshold conduction −V /nV Eq. (15.13) is proportional to e t T . If the threshold voltage of an NMOS transistor is reduced by 0.1 V, by what factor will
R=ρ
L ρL = A TW
where ρ is the resistivity of the material of which the wire is made. The quantity ρ/T is called the sheet resistance and has the dimension of ohms, although it is usually expressed as ohms/square or /0002 (refer to Fig. P15.11a).
W
Square
W T L (a) R C
(b) Figure P15.11
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 1229
15.15 Find tPLH , tPHL , and tP for the pseudo-NMOS inverter specified in Problem 15.13 when loaded with C = 10 fF. D *15.16 Design a pseudo-NMOS inverter that has equal capacitive charging and discharging currents /4 0006 0006 at v O = VDD 0002 for use in a system with VDD = 2.5 V, 0006Vt 0006 = 0.5 V, kn = 2 0002 2 115 μA/V , kp = 30 μA/V , and (W/L)n = 1.5. What are the values of (W/L)p , VIL , VIH , VM , VOH , VOL , NMH , and NML ? *15.17 Use Eq. (15.26) to find the value of r for which NML is maximized. What is the corresponding value of NML for the case VDD = 1.3 V and Vt = 0.4 V ? Show that NML does not change very much with r by evaluating NML for r = 2, 5, and 10.
15.12 The purpose of this problem is to compare the value of tPLH obtained with a resistive load [see Fig. P15.12(a)] to that obtained with a current-source load [see Fig. P15.12(b)]. For a fair comparison, let the current source I = VDD /RD , which is the initial current available to charge the capacitor in the case of a resistive load. Find tPLH for each case, and hence the percentage reduction obtained when a current-source load is used.
15.18 For what value of r does NMH of a pseudo-NMOS inverter become zero? Prepare a table of NMH and NML versus r, for r = 2 to 10. Let VDD = 1.3 V and Vt = 0.4 V. Use your table and iteration to determine the value of r that results in NML = NMH . What is the resulting margin?
15.13 For a pseudo-NMOS inverter fabricated in a 0.13-μm 2 process and having kn = 5kp = 500 μA/V , Vtn = −Vtp = 0.4 V, and VDD = 1.3 V, find VOH , VOL , and Isat . Hence, find the static power dissipation in the low-output state.
D 15.19 Design a pseudo-NMOS inverter that has VOL = 0006 0006 0002 0002 2 0.1 V. Let VDD = 1.8 V, 0006Vt 0006 = 0.5 V, kn = 4kp = 400 μA/V , and (W/L)p = 1. What is the value of (W/L)n ? Calculate the values of NML and the static power dissipation.
VDD
VDD
RD
I
vO vI
vI
QN
VDD 0
C
vO vI
vI
QN
C
VDD 0
0
t (a)
0
t (b)
Figure P15.12
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
Section 15.3: Pseudo-NMOS Logic Circuits
15.14 For the pseudo-NMOS inverter specified in Problem 15.13, find VOL , VIL , VM , VIH , VOH , NML , and NMH .
CHAPTER 15
(a) Find the resistance of an aluminum wire that is 5 mm long and 0.5 μm wide, if the sheet resistance is specified to be 27 m /0002. (b) If the wire capacitance to ground is 0.1 fF/μm length, what is the total wire capacitance? (c) If we can model the wire very approximately as an RC circuit as shown in Fig. P15.11(b), find the delay time introduced by the wire. (Hint: tdelay = 0.69RC.) (P.S. Only a small fraction of the interconnect on an IC would be this long!)
CHAPTER 15
PROBLEMS
1230 Chapter 15 Advanced Topics in Digital Integrated-Circuit Design D *15.20 It is required to design a minimum-area pseudo-NMOS inverter with equal high and low 0006 noise 0006 margins using a 1.3-V supply and devices for which 0006Vt 0006 = 0002 0002 2 0.4 V, kn = 4kp = 500 μA/V , and the minimum-size device has (W/L) = 1. Use r = 5.7 and show that NML 0003 NMH . Specify the values of (W/L)n and (W/L)p . What is the static power dissipated in this gate? What is the ratio of propagation delays for low-to-high and high-to-low transitions? For an equivalent load capacitance of 100 fF, find tPLH , tPHL , and tP . At what frequency of operation would the static and dynamic power levels be equal? Is this speed of operation possible in view of the tP value you found? D 15.21 Sketch a pseudo-NMOS realization of the function Y = A + B(C + D). D 15.22 Sketch a pseudo-NMOS realization of the exclusive-OR function Y = AB + A B. D 15.23 Consider a four-input pseudo-NMOS NOR gate in which the NMOS devices have (W/L)n = 1.5. It is required to find (W/L)p so value of VOL is 0.1 V. Let 0006 that 0006 the worst-case 0002 0002 2 VDD = 1.3 V, 0006Vt 0006 = 0.4 V, and kn = 4kp = 500 μA/V .
15.24 This problem investigates the effect of velocity saturation (Section 15.1.3) on the operation of a pseudo-NMOS inverter fabricated in a 0.13-μm CMOS process for which 2 VDD =0006 1.3 V, Vt = 0.4 V, kn = 5kp = 500 μA/V , and |VDSsatp 0006 = 0.6 V. Consider the case with v I = VDD and v O = VOL . Note that QP will be operating in the velocity-saturation region. Find its current IDsat and use it to determine VOL .
Section 15.4: Pass-Transistor-Logic Circuits 15.25 Recall that MOS transistors are symmetrical and that what distinguishes the source from the drain is their relative voltage levels: For NMOS, the terminal with the higher voltage is the drain; for PMOS, the terminal with the higher voltage is the source. For each of the circuits in Fig. P15.25, label the source and drain terminals and give the output voltage VO in terms of VDD , Vtn , and |Vtp |. Note that Vtn and |Vtp | are determined by the body effect, and give expressions for their values. Note that VO is the value reached after the capacitor charging/discharging interval has come to an end.
VDD
VO
0V
VO
VDD
C
C
(a)
(b)
VDD
VO
VDD
VO
0V
C
(c)
C
(d)
Figure P15.25
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 1231
15.28 Consider the circuit in Fig. 15.18 with the NMOS transistor having W/L = 1.5 and fabricated in a 0.13-μm CMOS process for which Vt0 = 0.4 V, VDD = 1.2 V, and 2 μn Cox = 500 μA/V . Determine tPHL for the case C = 10 fF. 15.29 Consider the case specified in Exercise 15.8. If the output of the switch is connected to the input of a CMOS inverter having (W/L)p = 2(W/L)n = 0.54 μm/0.18 μm, find the static current of the inverter and its static power dissipation when the inverter input is at the value found in Exercise 15.8. Also find the inverter output voltage. Let μn Cox = 4 μp Cox = 2 300 μA/V . 15.30 An NMOS pass-transistor switch with W/L = 1.2 μm/0.8 μm, used in a 3.3-V system for which Vt0 = 0.8 V, 1/2 2 γ = 0.5 V , 2φf = 0.6V, μn Cox = 3μp Cox = 75 μA/V , drives a 100-f F load capacitance at the input of a matched standard CMOS inverter using (W/L)n = 1.2 μm/0.8 μm. For the switch gate terminal at VDD , evaluate the switch VOH and VOL for inputs at VDD and 0 V, respectively. For this value of VOH , what inverter static current results? Estimate tPLH and tPHL for this arrangement as measured from the input to the output of the switch itself.
*15.32 A designer, beginning to experiment with the idea of pass-transistor logic, seizes upon what he sees as two good ideas: (a) that a string of minimum-size single MOS transistors can do complex logic functions, (b) but that there must always be a path between output and a supply terminal. Correspondingly, he first considers two circuits (shown in Fig. P15.32). For each, express Y as a function of A and B. In each case, what can be said about general operation? About the logic levels at Y ? About node X ? Do either of these circuits look familiar? If in each case the terminal connected to VDD is instead connected to the output of a CMOS inverter whose input is connected to a signal C, what does the function Y become?
A
B
VDD X
Y B
A
15.31 Figure P15.31 shows a PMOS transistor operating as a switch in the on position.
(a)
(a) If initially v O = 0 and at t = 0, v I is raised to VDD , what is the final value VOH reached at the output?
A
B
VDD Y X
vI
vO
Q
B
A
C (b) Figure P15.31
Figure P15.32
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
15.27 Consider the circuit in Fig. 15.17 with the NMOS transistor having W/L = 1.5 and fabricated in a CMOS process 1/2 for which Vt0 = 0.4 V, γ = 0.2 V , 2φf = 0.88 V, VDD = 1.2 V, 2 and μn Cox = 500 μA/V . Find tPLH for the case C = 10 fF.
(b) If initially v O = VDD and at t = 0, v I is lowered to 0 V, what is the final value VOL reached at the output? (c) For the situation in (a), find tPLH for v O to rise from 2 0 to0006 VDD /2. Let kp = 125 μA/V , VDD = 1.2 V, and |Vtp 0006 = 0.4 V.
CHAPTER 15
15.26 Let the NMOS transistor switch in Fig. 15.17 be fabricated in a 0.13-μm CMOS process for which Vt0 = 0.4 V, 1/2 γ = 0.2 V , 2φf = 0.88 V, and VDD = 1.2 V. Determine VOH .
CHAPTER 15
PROBLEMS
1232 Chapter 15 Advanced Topics in Digital Integrated-Circuit Design 15.33 Consider the circuits in Fig. P15.32 with all PMOS transistors replaced with NMOS, and all NMOS by PMOS, and with ground and VDD connections interchanged. What do the output functions Y become? 0002 n
15.34 For the level-restoring circuit of Fig. 15.19, let k = 0002 2 1/2 3kp = 75 μA/V , VDD = 3.3 V, |Vt0 |= 0.8 V, γ = 0.5 V , 2φf = 0.6 V, (W/L)1 = (W/L)n = 1.2 μm/0.8 μm, (W/L)p = 3.6 μm/0.8 μm, and C = 20 fF. Also let vB = VDD . Now for vA rising to VDD , and Q1 charging C and causing vO1 to rise, show that the value of vO1 that causes vO2 to drop by a threshold voltage below VDD (i.e., to 2.5 V) so that QR turns on, is approximately VDD /2 and thus occurs at t 0003 tLH . What is the capacitor-charging current available at this time (i.e., just prior to QR turning on)? What is it at vO1 = 0? What is the average current available for charging C? Estimate the time tPLH . (Note that after QR turns on, vO1 rises to VDD .) D *15.35 The purpose of this problem is to illustrate how W/L of the level-restoring transistor QR in the circuit of Fig. 15.19 is determined. For this purpose consider the circuit as specified in Problem 15.34 and let vB = VDD . Now, consider the situation when vA is brought down to 0 V and Q1 conducts and begins to discharge C. The voltage vO1 will begin to drop from VDD . Meanwhile, vO2 is still low and QR is conducting (though at t = 0, the current in QR is zero). Calculate the discharge current at t = 0. As QR conducts, its current subtracts from the current of Q1 , reducing the current available to discharge C. Find the value of vO1 at which the inverter begins to switch. This is VIH = 18 (5VDD − 2Vt ). Then, find the current that Q1 conducts at this value of vO1 . Choose W/L for QR so that the maximum current it conducts is limited to one-half the value of the current in Q1 . What is the W/L you have chosen? Estimate tPHL as the time for vO1 to drop from VDD to VIH .
0006 0002 2 0006 1/2 4kp = 500 μA/V , 0006Vt0 0006 = 0.4 V, γ = 0.2 V , 2φf = 0.88 V, and VDD = 1.2 V. Let QN and QP have (W/L)n = (W/L)p = 1.5. The total capacitance at the output node is 15 fF. (a) What are the values of VOH and VOL ? (b) For the situation in Fig. 15.21(a), find iDN (0), iDP (0), 0007 0007 iDN tPLH , iDP tPLH , and tPLH . (c) For the situation depicted in Fig. 15.21(b), find iDN (0), 0007 0007 iDP (0), iDN tPHL , iDP tPHL , and tPHL . At what value of v O will QP turn off? (d) Find tP . 15.37 For the transmission gate specified in Problem 15.36, find RTG at v O = 0 and 0.6 V. Use the average of those values to determine tPLH for the situation in which C = 15 fF. *15.38 Refer to the situation in Fig. 15.21(b). Derive expressions for RNeq , RPeq , and RTG following the approach used in Section 15.4.4 for the capacitor-charging case. Evaluate the value of RTG for v O = VDD and v O = VDD /2 for the process technology specified in Problem 15.36. Find the average value of RTG and use it to determine tPHL for the case C = 15 fF. 15.39 A transmission gate for which (W/L)n = (W/L)p = 1.5 is fabricated in a 0.13-μm CMOS technology and used in a circuit for which C = 10 fF. Use Eq. (15.49) to obtain an estimate of RTG and hence of the propagation delay tP . 15.40 Figure P15.40 shows a chain of transmission gates. This situation often occurs in circuits such as adders and multiplexers. Consider the case when all the transmission gates are turned on and a step voltage VDD is applied to the input. The propagation delay tP can be determined from the Elmore delay formula as follows:
15.36 The transmission gate in Fig. 15.21(a) and 15.21(b) 0002 is fabricated in a CMOS process technology for which kn =
1
2
tP = 0.69
n 0012
kCRTG
k=0
3
n vO
vI C
VDD
C
C
C
t
0 Figure P15.40
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 1233
n(n + 1) 2
Now evaluate tP for the case of 16 transmission gates with RTG = 10 k and C = 10 fF. What does the value of tP become if the input is a ramp rather than a step function? D 15.41 (a) Use the idea embodied in the exclusive-OR realization in Fig. 15.26 to realize Y = AB + A B. That is, find a realization for Y using two transmission gates. (b) Now combine the circuit obtained in (a) with the circuit in Fig. 15.26 to obtain a realization of the function Z = Y C + Y C where C is a third input. Sketch the complete 12-transistor circuit realization of Z. Note that Z is a three-input exclusive-OR. D *15.42 Using the idea presented in Fig. 15.27, sketch a CPL circuit whose outputs are Y = AB+AB and Y = AB+A B. D 15.43 Extend the CPL idea in Fig. 15.27 to three variables to form Z = ABC and Z = ABC = A + B + C.
Section 15.5: Dynamic MOS Logic Circuits D 15.44 Based on the basic dynamic logic circuit of Fig. 15.28, sketch complete circuits for NOT, NAND, and NOR gates, the latter two with two inputs, and a circuit for which Y = AB + CD. 15.45 In this and the following problem, we investigate the dynamic operation of a two-input NAND gate realized in the dynamic logic form and fabricated in a CMOS process 0002 0002 2 technology for which kn = 4kp = 500 μA/V , Vtn = −Vtp = 0.4 V, and VDD = 1.2 V. To keep CL small, minimum-size NMOS devices are used for which W/L = 1.5 (this includes Qe ). The PMOS precharge transistor Qp has W/L = 3. The capacitance CL is found to be 15 f F. Consider the precharge operation with the gate of Qp at 0 V, and assume that at t = 0, CL is fully discharged. Calculate the rise time of the output voltage, defined as the time for v Y to rise from 10% to 90% of the final value of 1.2 V. 15.46 For the gate specified in Problem 15.45, evaluate the high-to-low propagation delay, tPHL . 15.47 Consider a two-input NOR gate realized in the dynamic logic form illustrated in Fig. 15.28. Assume that the
15.48 The leakage current in a dynamic logic gate causes the capacitor CL to discharge during the evaluation phase, even if the PDN is not conducting. For CL = 10 f F, and −12 Ileakage = 2 × 10 A, find the longest allowable evaluation time if the decay in output voltage is to be limited to 0.2 V. If the precharge interval is much shorter than the maximum allowable evaluation time, find the minimum clocking frequency required.
PROBLEMS
tP = 0.69 CRTG
gate is fabricated in a 0.13-μm CMOS technology for which 2 VDD = 1.2 V, Vt = 0.4 V, and μn Cox = 4 μp Cox = 500 μA/V . The NMOS devices have W/L = 1.5, and the PMOS transistor has W/L = 3. The total capacitance at the output is found to be 15 fF. Calculate the rise time of vO , from 0.1 VDD to 0.9 VDD , in the precharge interval. Also, calculate the worst-case value of tPHL .
CHAPTER 15
where RTG is the resistance of each transmission gate, C is the capacitance between each node and ground, and n is the number of transmission gates in the chain. Note that the sum of the series in this formula is given by
*15.49 In this problem, we wish to calculate the reduction in the output voltage of a dynamic logic gate as a result of charge redistribution. Refer to the circuit in Fig. 15.30(a), and assume that at t = 0−, v Y = VDD , and v C1 = 0. At t = 0, φ goes high and QP turns off, and simultaneously the voltage at the gate of Q1 goes high (to VDD ), turning Q1 on. Transistor Q1 will remain conducting until either the voltage at its source (v C 1 ) reaches VDD – Vtn or until v Y = v C1 , whichever comes first. In both cases, the final value of v Y can be found using charge conservation: that is, by equating the charge gained by C1 to the charge lost by CL . (a) Convince yourself that the first situation obtains when 0006 0006 0006 v Y 0006 ≤ Vtn . (b) For each of the two situations, derive an expression for
v Y . (c) Find an0006 expression for the maximum ratio (C1 /CL ) for 0006 which 0006 v Y 0006 ≤ Vtn . (d) For Vtn = 0.5 V, VDD = 1.8 V, CL = 15 f F, and neglecting the body effect in Q1 , find the drop in voltage at the output in the two cases: (a) C1 = 4 f F and (b) C1 = 7.5 f F. 15.50 Solve the problem in Exercise 15.15 symbolically (rather than numerically). Refer to Fig. E15.15 and assume Qeq1 and Qeq2 to be identical with threshold voltages Vtn = 0.2VDD and transconductance parameters kn . Also, let CL1 = CL2 . Derive an expression for the drop in the output voltage,
v Y2 . 15.51 For the four-input dynamic logic NAND gate analyzed in Example 15.4, estimate the maximum clocking frequency allowed.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 15
PROBLEMS
1234 Chapter 15 Advanced Topics in Digital Integrated-Circuit Design Section 15.6: Bipolar and BiCMOS Logic Circuits 15.52 For the circuit in Fig. 15.34, let VCC = 0 V, I = 1 mA, and VR = −1 V. Find RC to obtain an output voltage swing of 0.4 V. By how much should the output levels be shifted so that the values of VOH and VOL become centered on VR ? What will the shifted values of VOH and VOL be? 15.53 In Fig. P15.53(a), the ECL gate discussed in the text, only the input A is shown (the other input B is assumed to be left open and thus deactivated). Figure P15.53(b) shows that OR transfer characteristic: that is, vOR versus vI . Determine the parameters of the transfer characteristic: that is, VIL , VIH , VOL , and VOH . Define VIL as the value of vI for which QR conducts 99% of IE and QA conducts 1% of IE . Conversely, define VIH as the value of vI for which QA conducts 99% of IE and QR conducts 1% of IE . Also, determine the width of the transition region (i.e., VIH − VIL ) and the noise margins NMH and NML . Assume that at an emitter current of 1 mA the transistor VBE = 0.75 V and β2 = 100. D 15.54 For the ECL circuit in Fig. P15.54, the transistors exhibit VBE of 0.75 V at an emitter current I and have very high β. (a) Find VOH and VOL .
(a)
(b) For the input at B that is sufficiently negative for QB to be cut off, what voltage at A causes a current of I/2 to flow in QR ? (c) Repeat (b) for a current in QR of 0.99I. Define this value of v A as VIL . (d) Repeat (c) for a current in QR of 0.01I. Define this value of v A as VIH . (e) Use the results of (c) and (d) to specify VIL and VIH . (f) Find NMH and NML . (g) Find the value of IR that makes the noise margins equal to the width of the transition region, VIH − VIL . (h) Using the IR value obtained in (g), give numerical values for VOH , VOL , VIH , VIL , and VR for this ECL gate. 15.55 For the ECL gate in Fig. 15.35, calculate an approximate value for the power dissipated in the circuit under the conditions that all inputs are low and that the emitters of the output followers are left open. Assume that the reference circuit supplies four identical gates, and hence only a quarter of the power dissipated in the reference circuit should be attributed to a single gate. D *15.56 Using the logic and circuit flexibility of ECL indicated by Figs. 15.35 and 15.37, sketch an ECL logic circuit that realizes the exclusive-OR function, Y = AB + AB. Give a logic diagram (as opposed to a circuit diagram).
(b)
Figure P15.53
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 1235
CHAPTER 15
R
R Q2
Q3
R 2
D
C
PROBLEMS
Q1 A
B
QA
I
QB
QR
I
I
I
I
Figure P15.54
*15.57 For the circuit in Fig. P15.57, let the levels of the inputs A, B, C, and D be 0 and +5 V. For all inputs low at 0 V, what is the voltage at E? If A and C are raised to +5 V,
00055 V 2.5 k A
Q1
B
Q2
E Q5
18 k
C
Q3
D
Q4 Q6
18 k
Figure P15.57
0006 0006 what is the voltage at E? Assume 0006VBE 0006 = 0.7 V and β = 50. Express E as a logic function of A, B, C, and D. 15.58 Consider the conceptual BiCMOS 0006circuit of 0006 Fig. 15.38(a), for the conditions that VDD = 5 V, 0006Vt 0006 = 1 V, 0002 0002 2 VBE = 0.7 V, β = 100, kn = 2.5kp = 100 μA/V , and (W/L)n = 2 μm/1μm. For v I = v O = VDD /2, find (W/L)p so that IEQ1 = IEQ2 . What is this totem-pole transient current? 15.59 Consider the conceptual BiCMOS circuit of Fig. 15.38(a) for the conditions stated in Problem 15.58. What is the threshold voltage of the inverter if both QN and QP have W/L = 2 μm/1 μm? What totem-pole current flows at v I equal to the threshold voltage? D *15.60 Consider the choice of values for R1 and R2 in the circuit of Fig. 15.38(c). Let the inverter be specified as in Problem 15.58 with the MOSFETs matched and (W/L)P = 2.5(W/L)n . An important consideration in making this choice is that the loss of base drive current will be limited. This loss becomes particularly acute when the current through QN and QP becomes small. This in turn happens near the end of the output signal swing when the 0006associated 0006 0006 0006MOS device is deeply in triode operation (say at 0006v DS 0006 = 0006Vt 0006/3). Determine values for R1 and R2 so that the loss in base current is limited to 50%. What is the ratio R1 /R2 ? Repeat for a 20% loss in base drive. D 15.61 Sketch the circuit of a BiCMOS two-input NOR gate based on the R-circuit of Fig. 15.38(e).
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 1283
activating its row, via the row-address decoder, and its column, via the column-address decoder. The sense amplifier detects the content of the selected cell and provides a full-swing version of it to the data-output terminal of the chip. 0002
0002
There are two kinds of MOS RAM: static and dynamic. Static RAMs (SRAMs) employ flip-flops as the storage cells. In a dynamic RAM (DRAM), data is stored on a capacitor and thus must be periodically refreshed. DRAM chips provide the highest possible storage capacity for a given chip area.
0002
0002
Two circuits have emerged as the near-universal choice in implementing the storage cell: the six-transistor SRAM cell and the one-transistor DRAM cell. 0002
0002
Although sense amplifiers are utilized in SRAMs to speed up operation, they are essential in DRAMs. A particular type of sense amplifier is a differential circuit that employs positive feedback to obtain an output signal that grows exponentially toward either VDD or 0.
Read-only memory (ROM) contains fixed data patterns that are stored at the time of fabrication and cannot be changed by the user. On the other hand, the contents of an erasable programmable ROM (EPROM) can be changed by the user. The erasure and reprogramming is a time-consuming process and is performed only infrequently. Some EPROMS utilize floating-gate MOSFETs as the storage cells. The cell is programmed by applying (to the selected gate) a high voltage, which in effect changes the threshold voltage of the MOSFET. Erasure is achieved by illuminating the chip by ultraviolet light. Even more versatile, EEPROMs can be erased and reprogrammed electrically. These are called flash memories and are currently in widespread use. CMOS image sensors are organized in arrays very similar to those used in memories. Each pixel circuit measures the light intensity at its pixel and provides this information on its column line in analog form, which is converted into a digital signal by means of an analog-to-digital converter (ADC).
PROBLEMS Section 16.1: Latches and Flip-Flops 16.1 Consider the latch of Fig. 16.1 with the two inverters identical and each characterized by VOL = 0 V, VOH = 5 V, VIL = 2 V, and VIH = 3 V. Let the transfer characteristic of each inverter be approximated by three straight-line segments. Sketch the transfer characteristic of the feedback loop of the latch and give the coordinates of points A, B, and C [refer to Fig. 16.1(b)]. What is the gain at C? What is the width of the transition region? D 16.2 Sketch the standard CMOS circuit implementation of the SR flip-flop shown in Fig. 16.3. D 16.3 Sketch the logic-gate implementation of an SR flip-flop utilizing two cross-coupled NAND gates. Clearly label the output terminals and the input trigger terminals. Provide the truth table and describe the operation.
D 16.4 For the SR flip-flop of Fig. 16.4, show that if each of the two inverters utilizes matched transistors, that is, (W/L)p = 0007 μn /μp (W/L)n , then the minimum W/L that each of Q5 −Q8 must have so that switching occurs is 2(W/L)n . Give the sizes of all eight transistors if the flip-flop is fabricated in a 0.13-μm process for which μn = 4 μp . Use the minimum channel length for all transistors and the minimum size (W/L = 1) for Q1 and Q3 . D 16.5 Repeat part (a) of the problem in Example 16.1 for the case of inverters that do not use matched QN and QP . Rather, assume that each of the inverters uses (W/L)p = (W/L)n = 0.27 μm/0.18 μm. Find the threshold voltage of each inverter. Then determine the value required for the W/L of each of Q5 to Q8 so that the flip-flop switches. (Hint: Refer to Table 14.2.) D 16.6 In this problem we investigate the effect of velocity saturation (Section 15.1.3) on the design of the SR flip-flop in Example 16.1. Specifically, answer part (a) of the question
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 16
PROBLEMS
1284 Chapter 16 Memory Circuits in Example 16.1, taking into account the fact that for 0002 this0002 0002VDSsat 0002 V and technology, VDSsat for n-channel devices is 0.6 0002 0002 −1 for p-channel devices is 1 V. Assume λn = 0002λp 0002 = 0.1 V . What is the minimum required value for (W/L)5 and for (W/L)6 ? Comment on this value relative to that found in Example 16.1. (Hint: Refer to Eq. 15.11.) D 16.7 The CMOS SR flip-flop in Fig. 16.4 is fabricated in 2 a 0.13-μm 0002 0002 process for which μn Cox = 4μp Cox = 500 μA/V , Vtn = 0002Vtp 0002 = 0.4 V, and VDD = 1.2 V. The inverters have (W/L)n = 0.2 μm/0.13 μm and (W/L)p = 0.8 μm/0.13 μm. The four NMOS transistors in the set–reset circuit have equal W/L ratios. (a) Determine the minimum value required for this ratio to ensure that the flip-flop will switch. (b) If a ratio twice the minimum is selected, determine the minimum required width of the set and reset pulses to ensure switching. Assume that the total capacitance between each of the Q and Q nodes and ground is 15 fF.
Figure P16.10
Section 16.2: Semiconductor Memories: Types and Architectures 16.11 How many cells does a 4-Gbit RAM have?
D 16.8 The clocked SR flip-flop in Fig. 16.4 is not a fully complementary CMOS circuit. Sketch the fully complementary version by augmenting the circuit with the PUN corresponding to the PDN comprising Q5 , Q6 , Q7 , and Q8 . Note that the fully complementary circuit utilizes 12 transistors. Although the circuit is more complex, it switches faster. D 16.9 Consider another possibility for the circuit in Fig. 16.7: Relabel the R input as S and the S input as R. Let S and R normally rest at VDD . Let the flip-flop be storing a 0; thus VQ = 0 V and VQ = VDD . To set the flip-flop, the S terminal is lowered to 0 V and the clock φ is raised to VDD . The relevant part of the circuit is then transistors Q5 and Q2 . For the flip-flop to switch, the voltage at Q must be lowered to VDD /2. What is the minimum required W/L for Q5 in terms 0007 of (W/L)2 and μn /μp ? Assume Vtn = |Vtp |. *16.10 Figure P16.10 shows a commonly used circuit of a D flip-flop that is triggered by the negative-going edge of the clock φ. (a) For φ high, what are the values of Q and Q in terms of D? Which transistors are conducting? (b) If D is high and φ goes low, which transistors conduct and what signals appear at Q and at Q? Describe the circuit operation. (c) Repeat (b) for D low with the clock φ going low. (d) Does the operation of this circuit rely on charge storage?
16.12 A 4-Gbit memory chip is organized as 256M words × 16 bits. How many bits does the word address need? 16.13 A particular 1-M-bit-square memory array has its peripheral circuits reorganized to allow for the readout of a 16-bit word. How many address bits will the new design need? 16.14 For the memory chip described in Problem 16.13, how many word lines must be supplied by the row decoder? How many sense amplifiers/drivers would a straightforward implementation require? If the chip power dissipation is 500 mW with a 5-V supply for continuous operation with a 20-ns cycle time, and all the power loss is dynamic, estimate the total capacitance of all logic activated in any one cycle. If we assume that 90% of this power loss occurs in array access, and that the major capacitance contributor will be the bit line itself, calculate the capacitance per bit line and per bit for this design. (Recall from Problem 16.13 that 16 bit lines are selected simultaneously.) If closer manufacturing control allows the memory array to operate at 3 V, how much larger a memory array can be designed in the same technology at about the same power level? 16.15 A 1.5-V, 1-Gbit dynamic RAM (called DRAM) by Hitachi uses a 0.16-μm process with a cell size of 0.38 × 2 2 0.76 μm in a 19 × 38 mm chip. What fraction of the chip is occupied by the I/O connections, peripheral circuits, and interconnect?
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 1285
16.16 Repeat Exercise 16.4 for an SRAM fabricated in a 0.25-μm CMOS process for which VDD = 2.5 V and Vt = 0.5 V.
*16.22 Refer to the circuit in Fig. 16.13 and find the maximum ratio (W/L)5 /(W/L)1 for VQ ≤ Vt , this time taking into account the velocity-saturation effect (Section 15.1.3, Eq. 15.11). The SRAM is fabricated in a 0.18-μm CMOS process for which VDD = 1.8 V, Vt = 0.5 V, and for the n-channel devices VDSsat = 0.6 V. Compare to the value obtained without accounting for velocity saturation. (Hint: Convince yourself that for this situation only Q5 will be operating in velocity saturation.)
16.17 Repeat Exercise 16.4 for an SRAM fabricated in a 0.13-μm CMOS process for which VDD = 1.2 V and Vt = 0.4 V. 16.18 Locate on the graph of Fig. 16.14 the points A, B, and C that correspond to the following three process technologies: (a) 0.25-μm: VDD = 2.5 V and Vt = 0.5 V (b) 0.18-μm: VDD = 1.8 V and Vt = 0.5 V (c) 0.13-μm: VDD = 1.2 V and Vt = 0.4 V In each case, impose the condition that in a read-1 operation VQ = Vt . D 16.19 Find the maximum allowable W/L for the access transistors of the SRAM cell in Fig. 16.12 so that in the read operation, the voltages at Q and Q do not change by more than |Vt |. Assume that the SRAM is fabricated in a 0.13-μm technology for which VDD = 1.2 V and Vtn = |Vtp | = 0.4 V, and (W/L)n = 1.5. Find VQ and I5 that result in each of the following cases: (i) (W/L)a = 13 the maximum allowed (ii) (W/L)a = 23 the maximum allowed (iii) (W/L)a = the maximum allowed 2
Assume μn Cox = 500 μA/V . Which one of the three designs results in the shortest read delay? D 16.20 Consider a 6T SRAM cell 0002fabricated in a 0002 0.18-μm CMOS process for which Vtn = 0002Vtp 0002 = 0.5 V and VDD = 1.8 V. If during a read-1 operation it is required that VQ not exceed 0.2 V, use the graph in Fig. 16.14 to determine the maximum allowable value of the ratio (W/L)5 /(W/L)1 . For L1 = L5 = 0.18 μm, select values for W1 and W5 that minimize the combined areas of Q1 and Q5 . Assume that the minimum width allowed is 0.18 μm. 16.21 Consider the read operation of the 6T SRAM cell of Fig. 16.12 when it is storing a 0, that is, VQ = 0 V, and VQ = VDD . Assume that the bit lines are precharged to VDD before the word-line voltage is raised to VDD . Sketch the relevant part of the circuit and describe the operation. Show
D *16.23 For the 6T SRAM of Fig. 16.12, fabricated in a 0.13-μm CMOS process for which VDD = 1.2 V, Vt0 = 0.4 V, 1/2 2φf = 0.88 V, and γ = 0.2 V , find the maximum ratio (W/L)5 /(W/L)1 for which VQ ≤ Vt0 during a read-1 operation (Fig. 16.13). Then, take into account the body effect in Q5 and compare this result to the value obtained without accounting for the body effect. D 16.24 A 6T SRAM cell is fabricated in a 0.13-μm CMOS process for which VDD = 1.2 V, Vt = 0.4 V, and μn Cox = 2 500 μA/V . The inverters utilize (W/L)n = 1. Each of the bit lines has a 2-pF capacitance to ground. The sense amplifier requires a minimum of 0.2-V input for reliable and fast operation. (a) Find the upper bound on W/L for each of the access transistors so that VQ and VQ do not change by more than Vt volts during the read operation. (b) Find the delay time 0005t encountered in the read operation if the cell design utilizes minimum-size access transistors. (c) Find the delay time 0005t if the design utilizes the maximum allowable size for the access transistors. 16.25 Consider the operation of writing a 1 into a 6T SRAM cell that is originally storing a 0. Sketch the relevant part of the circuit and explain the operation. Without doing detailed analysis, show that the analysis would lead to results identical to those obtained in the text for the write-0 operation. D 16.26 For a 6T SRAM cell fabricated in a 0.13-μm CMOS process, find the maximum permitted value of (W/L)p in terms of (W/L) 0002 0002a of the access transistors. Assume VDD = 1.2 V, Vtn = 0002Vtp 0002 = 0.4 V, and μn = 4μp . D 16.27 For a 6T SRAM cell fabricated in a 0.25-μm CMOS process, find the maximum permitted value of (W/L)p in terms
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
that the analysis parallels that presented in the text for the read-1 operation.
CHAPTER 16
Section 16.3: Random-Access Memory (RAM) Cells
CHAPTER 16
PROBLEMS
1286 Chapter 16 Memory Circuits of (W/L) 0002 0002a of the access transistors. Assume VDD = 2.5 V, Vtn = 0002Vtp 0002 = 0.5 V, and μn 0004 4μp . 16.28 Locate on the graph in Fig. 16.17 the points A, B, and C corresponding to the following three CMOS fabrication processes: 0002 0002 (a) 0.25-μm: VDD = 2.5 V, Vtn = 0002Vtp 0002 = 0.5 V 0002 0002 (b) 0.18-μm: VDD = 1.8 V, Vtn = 0002Vtp 0002 = 0.5 V 0002 0002 (c) 0.13-μm: VDD = 1.2 V, Vtn = 0002Vtp 0002 = 0.4 V For all three, μn 0004 4μp . In each case, VQ is to be limited to a maximum value of Vtn . D 16.29 Design a minimum-size 6T SRAM cell0002 in0002 a 0.13-μm process for which VDD = 1.2 V and Vtn = 0002Vtp 0002 = 0.4 V. All transistors are to have equal L = 0.13 μm. Assume that the minimum width allowed is 0.13 μm. Verify that your minimum-size cell meets the constraints in Eqs. (16.5) and (16.11). 16.30 For a particular DRAM design, the cell capacitance CS = 35 fF and VDD = 1.2 V. Each cell represents a capacitive load on the bit line of 0.8 fF. Assume a 20-fF capacitance for the sense amplifier and other circuitry attached to the bit line. What is the maximum number of cells that can be attached to a bit line while ensuring a minimum bit-line signal of 25 mV? How many bits of row addressing can be used? If the sense-amplifier gain is increased by a factor of 4, how many word-line address bits can be accommodated? 16.31 For a DRAM available for regular use 98% of the time, having a row-to-column ratio of 2 to 1, a cycle time of 10 ns, and a refresh cycle of 10 ms, estimate the total memory capacity. 16.32 In a particular dynamic memory chip, CS = 30 fF, the bit-line capacitance per cell is 0.5 f F, and bit-line control circuitry involves 12 fF. For a 1-Mbit-square array, what bit-line signals result when a stored 1 is read? When a stored 0 is read? Assume that VDD = 1.2 V. 16.33 For a DRAM cell utilizing a capacitance of 30 fF, refresh is required within 12 ms. If a signal loss on the capacitor of 0.2 V can be tolerated, what is the largest acceptable leakage current present at the cell?
Section 16.4: Sense Amplifiers and Address Decoders D 16.34 Consider the operation of the differential sense amplifier of Fig. 16.20 following the rise of the sense control
signal φ s . Assume that a balanced differential signal of 0.1 V is established between the bit lines, each of which has a 1 pF capacitance. For VDD = 1.2 V, what value of Gm of each of the inverters in the amplifier is required to cause the outputs to reach 0.1VDD and 0.9VDD [from initial values of 0.5VDD − (0.1/2) and 0.5VDD + (0.1/2) 0002 0002 volts, respectively] in 2 ns? If for the matched inverters, 0002Vt 0002 = 0.4 V 0002 0002 2 and kn = 4kp = 500 μA/V , what are the device widths required? If the input signal is 0.2 V, what does the amplifier response time become? 16.35 A particular version of the regenerative sense amplifier of Fig. technology uses transistors for 0002 0002 16.20 in a00020.13-μm 0002 2 which 0002Vt 0002 = 0.4 V, kn = 4kp = 500 μA/V , VDD = 1.2 V, with (W/L)n = 0.26 μm/0.13 μm and (W/L)p = 1.04 μm/0.13 μm. For each inverter, find the value of Gm . For a bit-line capacitance of 0.4 pF, and a delay until an output of 0.9VDD is reached of 1 ns, find the initial difference voltage required between the two bit lines. If the time can be relaxed by 1 ns, what input signal can be handled? With the increased delay time and with the input signal at the original level, by what percentage can the bit-line capacitance, and correspondingly the bit-line length, be increased? If the delay time required for the bit-line capacitances to charge by the constant current available from the storage cell, and thus develop the difference-voltage signal needed by the sense amplifier, was 2 ns, what does it increase to when longer lines are used? D 16.36 (a) For the sense amplifier of Fig. 16.20, show that the time required for the bit lines to reach 0.9VDD 0007 0007 and 0.1VDD is given by td = CB /Gm ln 0.8VDD /0005V , where 0005V is the initial difference voltage between the two bit lines. (b) If the response time of the sense amplifier is to be reduced to one-half the value of an original design, by what factor must the width of all transistors be increased? (c) If for a particular design, VDD = 1.2 V and 0005V = 0.2 V, find the factor by which the widths of all transistors must be increased so that 0005V is reduced by a factor of 2, while keeping td unchanged? D 16.37 It is required to design a sense amplifier of the type shown in Fig. 16.20 to operate with a DRAM using the dummy-cell technique illustrated in Fig. 16.22. The DRAM cell provides readout voltages of –100 mV when a 0 is stored and +40 mV when a 1 is stored. The sense amplifier is required to provide a differential output voltage of 1 V in at most 2 ns. Find the W/L ratios of the transistors in the amplifier matched inverters, assuming that the processing 0002 0002 technology 0002 0002 2 is characterized by kn = 4kp = 300 μA/V , 0002Vt 0002 = 0.5 V, and VDD = 1.8 V. The capacitance of each half-bit line is 0.5 pF.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 1287
D 16.38 It is required to design the sense amplifier of Fig. 16.24 to detect an input signal of 140 mV and provide a full output in 0.5 ns. If C = 50 fF and VDD = 1.2 V, find the required current I and the power dissipation.
(a) If Q1 and Q2 are to operate at the edge of saturation, what is the dc voltage at the drain of Q1 ? (b) If the switching voltage 0005V is to be about 140 mV, at what overdrive voltage VOV should Q1 and Q2 be operated in equilibrium? What dc voltage should appear at the common-source terminals of Q1 and Q2 ? (c) If the delay component 0005t given by Eq. (16.18) is to be 0.5 ns, what current I is needed if C = 55 fF? (d) Find the W/L required for each of Q1 to Q4 for μn Cox = 2 4μp Cox = 500 μA/V . (e) If Q5 is to operate at the same overdrive voltage as Q1 and Q2 , find its required W/L and the value of the reference voltage VR , 16.40 Consider a 1024-row NOR decoder. To how many address bits does this correspond? How many output lines does the decoder have? How many input lines does the NOR array require? How many NMOS and PMOS transistors does such a design need? 16.41 For the column decoder shown in Fig. 16.26, how many column-address bits are needed in a 1-Mbit-square array? How many NMOS pass transistors are needed in the multiplexer? How many NMOS transistors are needed in the NOR decoder? How many PMOS transistors? What is the total number of NMOS and PMOS transistors needed? 16.42 Consider the use of the tree column decoder shown in Fig. 16.27 for application with a square 1-Mbit array. How many address bits are involved? How many levels of pass gates are used? How many pass transistors are there in total? 16.43 Consider a ring oscillator consisting of five inverters, each having tPLH = 3 ns and tPHL = 2 ns. Sketch one of the output waveforms, and specify its frequency and the percentage of the cycle during which the output is high. 16.44 A ring-of-nine oscillator is found to operate at 20 MHz. Find the propagation delay of the inverter.
Section 16.5: Read-Only Memory (ROM) 16.46 Give the eight words stored in the ROM of Fig. 16.30. D 16.47 Design the bit pattern to be stored in a (16 × 4) ROM that provides the 4-bit product of two 2-bit variables. Give a circuit implementation of the ROM array using a form similar to that of Fig. 16.30. 16.48 Consider a dynamic version of the ROM in Fig. 16.30 in which the gates of the PMOS devices are connected to a precharge control signal φ. Let all the NMOS devices have W/L = 3 μm/1.2 μm and all the PMOS devices have W/L = 12 0002 0002 2 μm/1.2 μm. Assume kn = 3kp = 90 μA/V , Vtn = − Vtp = 1 V, and VDD = 5 V. (a) During the precharge interval, φ is lowered to 0 V. Estimate the time required to charge a bit line from 0 to 5 V. Use as an average charging current the current supplied by a PMOS transistor at a bit-line voltage halfway through the excursion of 0 to 5 V (i.e., 2.5 V). The bit-line capacitance is 1 pF. Note that all NMOS transistors are cut off at this time. (b) After the precharge interval is completed and φ returns to VDD , the row decoder raises the voltage of the selected word line. Because of the finite resistance and capacitance of the word line, the voltage rises exponentially toward VDD . If the resistance of each of the polysilicon word lines is 5 k0004 and the capacitance between the word line and ground is 2 pF, what is the (10% to 90%) rise time of the word-line voltage? What is the voltage reached at the end of one time constant? (c) If we approximate the exponential rise of the word-line voltage by a step equal to the voltage reached in one time constant, find the interval 0005t required for an NMOS transistor to discharge the bit line and lower its voltage by 1 V.
Section 16.6: CMOS Image Sensors 16.49 Consider the pixel circuit in Fig. 16.34. If the capacitance C at the storage node X is 25 fF and if QP resets the node voltage to VDD , how much electron charge is accumulated onto the capacitance when the voltage drops by 1 V? Also give the number of electrons this represents. (Recall that the magnitude −19 of the electron charge is 1.6 × 10 C).
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
D 16.39 Consider the sense amplifier in Fig. 16.24 in the equilibrium condition shown in part (b) of the figure. Let VDD = 1.2 V and Vt = 0.4 V.
D 16.45 Design the one-shot circuit of Fig. 16.29 to provide an output pulse of 10-ns width. If the inverters available have tP = 2.5 ns delay, how many inverters do you need for the delay circuit?
CHAPTER 16
What will be the amplifier response time when a 0 is read? When a 1 is read?
Problems 1369
op amps but are sensitive to the op-amp nonidealities and are thus limited to low-Q applications (Q ≤ 10).
various special second-order filtering functions, as shown in Fig. 17.18. 0002
0002
0002
The classical sensitivity function
By replacing the inductor of an LCR resonator with a simulated inductance obtained using the Antoniou circuit of Fig. 17.20(a), the op amp–RC resonator of Fig. 17.21(b) is obtained. This resonator can be used to realize the various second-order filter functions as shown in Fig. 17.22. The design equations for these circuits are given in Table 17.1.
0002
Biquads based on the two-integrator-loop topology are the most versatile and popular second-order filter realizations. There are two varieties: the KHN circuit of Fig. 17.24(a), which realizes the LP, BP, and HP functions simultaneously and can be combined with the output summing amplifier of Fig. 17.24(b) to realize the notch and all-pass functions; and the Tow–Thomas circuit of Fig. 17.25(b), which realizes the BP and LP functions simultaneously. Feedforward can be applied to the Tow–Thomas circuit to obtain the circuit of Fig. 17.26, which can be designed to realize any of the second-order functions (see Table 17.2).
0002
Transconductance-C circuits utilize transconductors and capacitors to realize medium- and high-frequency filters (as high as hundreds of megahertz) that can be implemented in CMOS. The basic building block is the integrator, and the basic filter building block is based on the two-integrator-loop topology.
0002
Switched-capacitor (SC) filters are based on the principle that a capacitor C, periodically switched between two circuit nodes at a high rate, fc , is equivalent to a resistance R = 1/Cf c connecting the two circuit nodes. SC filters can be fabricated in monolithic form using CMOS IC technology.
Single-amplifier biquads (SABs) are obtained by placing a bridged-T network in the negative-feedback path of an op amp. If the op amp is ideal, the poles realized are at the same locations as the zeros of the RC network. The complementary transformation can be applied to the feedback loop to obtain another feedback loop having identical poles. Different transmission zeros are realized by feeding the input signal to circuit nodes that are connected to ground. SABs are economic in their use of
0002
Tuned amplifiers utilize LC-tuned circuits as loads, or at the input, of transistor amplifiers. They are used in the design of the RF tuner and the IF amplifier of communication receivers. The cascode and the CC–CB cascade configurations are frequently used in the design of tuned amplifiers. Stagger-tuning the individual tuned circuits results in a flatter passband response (in comparison to that obtained with all the resonant circuits synchronously tuned).
y
Sx =
∂y/y ∂x/x
is a very useful tool in investigating how tolerant a filter circuit is to the unavoidable inaccuracies in component values and to the nonidealities of the op amps.
PROBLEMS Section 17.1: Filter Transmission, Types, and Specification
17.2 A sinusoid with 1-V peak amplitude is applied at the input of a filter having the transfer function 4
17.1 The transfer function of a first-order low-pass filter (such as that realized by an RC circuit) can be 0003 0002 expressed as T (s) = ω0 / s + ω0 , where ω0 is the 3-dB frequency of the filter. Give in table form the values of |T |, φ, G, and A at ω = 0, 0.5ω0 , ω0 , 2ω0 , 5ω0 , 10ω0 , and 100ω0 .
T (s) =
2π × 10 s + 2π × 104
Find the peak amplitude and the phase (relative to that of the input sinusoid) of the output sinusoid if the frequency of the input sinusoid is (a) 1 kHz, (b) 10 kHz, (c) 100 kHz, and (d) 1 MHz.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 17
PROBLEMS
1370 Chapter 17 Filters and Tuned Amplifiers 2
*17.3 A filter has the transfer function T (s) = 1/[(s + 1)(s + √ s + 1)]. Show that |T | = 1 + ω6 and find an expression for its phase response φ(ω). Calculate the values of |T | and φ for ω = 0.1, 1, and 10 rad/s and then find the output corresponding to each of the following input signals: (a) 10 sin 0.1t (volts) (b) 10 sin t (volts) (c) 10 sin 10t (volts)
complex-conjugate poles is at 18° angles from the jω axis, and the other pair is at 54° angles. Give the transfer function in each of the following cases. (a) The transmission zeros are all at s = ∞ and the dc gain is unity. (b) The transmission zeros are all at s = 0 and the high-frequency gain is unity. What type of filter results in each case?
17.4 For the filter whose magnitude response is sketched (as the blue curve) in Fig. 17.3, find |T | at ω = 0, ω = ωp , and ω = ωs . Amax = 0.2 dB, and Amin = 60 dB. D 17.5 A low-pass filter is required to pass all signals within its passband, extending from 0 to 4 kHz, with a transmission variation of at most 5% (i.e., the ratio of the maximum to minimum transmission in the passband should not exceed 1.05). The transmission in the stopband, which extends from 5 kHz to ∞, should not exceed 0.05% of the maximum passband transmission. What are the values of Amax , Amin , and the selectivity factor for this filter? 17.6 A low-pass filter is specified to have fp = 5 kHz and a selectivity factor of 10. The specifications are just met by a first-order transfer function
17.11 A third-order low-pass filter has transmission zeros at ω = 2 rad/s and ω = ∞. Its natural modes are at s = −1 and s = −0.5 ± j0.8. The dc gain is unity. Find T(s). 17.12 A second-order low-pass filter has poles at −0.25 ± j and a transmission zero at ω = 2 rad/s. If the dc gain is unity, give the transfer function T (s). What is the gain at ω approaching infinity? 17.13 Find the order N and the form of T(s) of a bandpass filter having transmission zeros as follows: one at ω = 0, one 3 3 3 at ω = 10 rad/s, one at 3 × 10 rad/s, one at 6 × 10 rad/s, and one at ω = ∞. If this filter has a monotonically decreasing passband transmission with a peak at the center frequency of 3 2 ×10 rad/s, and equiripple response in the stopbands, sketch the shape of its |T |.
4
T (s) =
2π × 10 s + 2π × 104
What must Amax and Amin be? 17.7 A low-pass filter is specified to have Amax = 2 dB and Amin = 12 dB. It is found that these specifications can be just met with a single-time-constant RC circuit having a time constant of 1 s and a dc transmission of unity. What must ωp and ωs of this filter be? What is the selectivity factor? 17.8 Sketch transmission specifications for a high-pass filter having a passband defined by f ≥ 3 kHz and a stopband defined by f ≤ 2 kHz. Amax = 0.4 dB, and Amin = 60 dB. 17.9 Sketch transmission specifications for a bandstop filter that is required to pass signals over the bands 0 ≤ f ≤ 10 kHz and 20 kHz ≤ f ≤ ∞ with Amax of 0.5 dB. The stopband extends from f = 12 kHz to f = 18 kHz, with a minimum required attenuation of 50 dB.
Section 17.2: The Filter Transfer Function 17.10 Consider a fifth-order filter whose poles are all at 4 a radial distance from the origin of 10 rad/s. One pair of
*17.14 Analyze the RLC network of Fig. P17.14 to determine its transfer function Vo (s)/Vi (s) and hence its poles and zeros. (Hint: Begin the analysis at the output and work your way back to the input.)
10013
2H
0003 Vi(s)
0003 1F
1F
10013
0002
Vo (s) 0002
Figure P17.14
Section 17.3: Butterworth and Chebyshev Filters D 17.15 Determine the order N of the Butterworth filter for which Amax = 0.5 dB, Amin ≥ 20 dB, and the selectivity ratio ωs /ωp = 1.7. What is the actual value of minimum stopband attenuation realized? If Amin is to be exactly 20 dB, to what value can Amax be reduced?
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 1371
17.18 Find the natural modes of a Butterworth filter having 3 a 0.5-dB bandwidth of 10 rad/s and N = 5. D 17.19 Design a Butterworth filter that meets the following low-pass specifications: fp = 10 kHz, Amax = 3 dB, fs = 20 kHz, and Amin = 20 dB. Find N, the natural modes, and T(s). What is the attenuation provided at 30 kHz? 17.20 Sketch the transfer function magnitude for a low-pass Chebyshev filter of (a) sixth order and (b) seventh order. 17.21 On the same diagram, sketch the magnitude of the transfer function of a Butterworth and a Chebyshev low-pass filter of fifth order and having the same ωp and Amax . At the stopband edge, ωs , which filter gives greater attenuation? *17.22 Sketch |T | for a seventh-order low-pass Chebyshev filter with ωp = 1 rad/s and Amax = 0.5 dB. Use Eq. (17.18) to determine the values of ω at which |T | = 1 and the values √ of ω at which |T | = 1/ 1 + 0004 2 . Indicate these values on your sketch. Use Eq. (17.19) to determine |T | at ω = 2 rad/s, and indicate this point on your sketch. For large values of ω, at what rate (in dB/octave) does the transmission decrease? 17.23 Contrast the attenuation provided by a sixth-order Chebyshev filter at ωs = 2ωp to that provided by a Butterworth filter of equal order. For both, Amax = 1 dB. Sketch |T | for both filters on the same axes. D *17.24 It is required to design a low-pass filter to meet the following specifications: fp = 3.4 kHz, Amax = 1 dB, fs = 4 kHz, Amin = 35 dB. (a) Find the required order of Chebyshev filter. What is the excess (above 35 dB) stopband attenuation obtained? (b) Find the poles and the transfer function.
Section 17.4: First-Order and Second-Order Filter Functions D 17.25 Use the information displayed in Fig. 17.13 to design a first-order op amp–RC low-pass filter having a 3-dB
17.27 Derive an expression for the transfer function of the op amp–RC circuit that is shown in Fig. 17.13(c). Give expressions for the frequency of the transmission zero ωZ , the frequency of the pole ωP , the dc gain, and the high-frequency gain.
PROBLEMS
17.17 Calculate the value of attenuation obtained at a frequency 1.8 times the 3-dB frequency of a seventh-order Butterworth filter.
D 17.26 Use the information given in Fig. 17.13 to design a first-order op amp–RC high-pass filter with a 3-dB frequency of 200 Hz, a high-frequency input resistance of 120 k0006, and a high-frequency gain magnitude of unity.
CHAPTER 17
17.16 Show that the order N of a Butterworth filter can be obtained from the approximate expression A − 20 log 0004 N ≥ min 20 log(ωs /ωp ) Hint: Use Eq. (17.15) and neglect the unity term.
frequency of 5 kHz, a dc gain magnitude of 10, and an input resistance of 12 k0006.
D *17.28 Use the information given in Fig. 17.13 to design a first-order op amp–RC spectrum-shaping network with a transmission zero frequency of 100 Hz, a pole frequency of 10 kHz, and a dc gain magnitude of unity. The low-frequency input resistance is to be 10 k0006. What is the high-frequency gain that results? Sketch the magnitude of the transfer function versus frequency. D *17.29 By cascading a first-order op amp–RC low-pass circuit with a first-order op amp–RC high-pass circuit, one can design a wideband bandpass filter. Provide such a design for the case in which the midband gain is 12 dB and the 3-dB bandwidth extends from 50 Hz to 50 kHz. Select appropriate component values under the constraints that no resistors higher than 100 k0006 are to be used and that the input resistance is to be as high as possible. D 17.30 Derive T(s) for the op amp–RC circuit in Fig. 17.14. Find |T (jω)| and φ(ω) We wish to use this circuit as a variable phase shifter by adjusting R. If the input signal frequency 3 is 5 × 10 rad/s and if C = 10 nF, find the values of R required to obtain phase shifts of –30°, –60°, –90°, –120°, and –150°. 17.31 Show that by interchanging R and C in the op amp–RC circuit of Fig. 17.14, the resulting phase shift covers the range 0 to 180° (with 0° at high frequencies and 180° at low frequencies). D *17.32 Use two first-order op amp–RC all-pass circuits in cascade to design a circuit that provides a set of three-phase 60-Hz voltages, each separated by 120° and equal in magnitude, as shown in the phasor diagram of Fig. P17.32. These voltages simulate those used in three-phase power transmission systems. Use 1-μF capacitors.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 17
PROBLEMS
1372 Chapter 17 Filters and Tuned Amplifiers a bothersome interference of 60-Hz frequency. Since the frequency of the interference is not stable, the filter should be designed to provide attenuation ≥20 dB over a 6-Hz band centered around 60 Hz. The dc transmission of the filter is to be unity.
Figure P17.32
17.40 Consider a second-order all-pass circuit in which errors in the component values result in the frequency of the zeros being slightly lower than that of the poles. Roughly sketch the expected |T |. Repeat for the case of the frequency of the zeros slightly higher than the frequency of the poles.
17.33 Use the information in Fig. 17.16(a) to obtain the transfer function of a second-order low-pass filter with ω0 = 4 10 rad/s, Q = 2, and dc gain = 1. At what frequency does |T | peak? What is the peak transmission?
17.41 Consider a second-order all-pass filter in which errors in the component values result in the Q factor of the zeros being greater than the Q factor of the poles. Roughly sketch the expected |T |. Repeat for the case of the Q factor of the zeros lower than the Q factor of the poles.
D *17.34 Use the information in Fig. 17.16(a) to obtain the transfer function of a second-order low-pass filter that just meets the specifications defined in Fig. 17.3 with ωp = 1 rad/s and Amax = 3 dB. Note that there are two possible solutions. For each, find ω0 and Q. Also, if ωs = 2 rad/s, find the value of Amin obtained in each case. 17.35 Find the transfer function of a second-order high-pass filter with a maximally flat passband response, a 3-dB frequency at ω = 1 rad/s, and a high-frequency gain of unity. Give the location of the poles and zeros. 17.36 Use the information given in Fig. 17.16(b) to find the transfer function of a second-order high-pass filter with √ natural modes at −0.5 ± j 3/2 and a high-frequency gain of unity. What are ω0 and Q of the poles? 17.37 Find the transfer function of a second-order bandpass filter for which the center frequency f0 = 10 kHz, the 3-dB bandwidth is 500 Hz, and the center-frequency gain is 10. Also, give the locations of the poles and zeros. D **17.38 (a) Show that |T | of a second-order bandpass function is geometrically symmetrical around the center frequency ω0 . That is, the members of each pair of frequencies ω1 and ω2 for which T ( jω1 ) = T ( jω2 ) are related by 2 ω1 ω2 = ω0 . (b) Find the transfer function of the second-order bandpass filter that meets specifications of the form in Fig. 17.4 where ωp1 = 8100 rad/s, ωp2 = 10, 000 rad/s, and Amax = 3 dB. If ωs1 = 3000 rad/s find Amin and ωs2 . D *17.39 Use the result of Exercise 17.15 to find the transfer function of a notch filter that is required to eliminate
Section 17.5: The Second-Order LCR Resonator 17.42 Analyze the circuit in Fig. 17.17(c) to determine its transfer function T (s) ≡ Vo (s)/Vi (s), and hence show that its poles are characterized by ω0 and Q of Eqs. (17.34) and (17.35), respectively. D 17.43 Design the LCR resonator of Fig. 17.17(a) to obtain 5 natural modes with ω0 = 10 rad/s and Q = 5. Use R = 10 k0006. 17.44 For the LCR resonator of Fig. 17.17(a), find the change in ω0 that results from (a) increasing L by 1% (b) increasing C by 1% (c) decreasing R by 1% 17.45 For each of the circuits in Fig. P17.45, find the transmission as ω approaches zero and as ω approaches ∞, and hence find the transmission zeros. 17.46 Derive an expression for Vo (s)/Vi (s) of the high-pass circuit in Fig. 17.18(c). D 17.47 Use the circuit of Fig. 17.18(b) √ to design a low-pass 6 filter with ω0 = 10 rad/s and Q = 1/ 2. Utilize a 1-nF capacitor. D 17.48 Modify the bandpass circuit of Fig. 17.18(d) to change its center-frequency gain from 1 to 0.5 without changing ω0 or Q. 17.49 Consider the LCR resonator of Fig. 17.17(a) with node x disconnected from ground and connected to an input signal
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 1373
C1
Vi
C2
–
0003
0003
Vo
Vi
–
0003
R
–
–
PROBLEMS
(b)
L1
L1
0003 L2
–
Vo
C2
(a)
Vi
CHAPTER 17
C1 0003
0003
0003
Vo
Vi
–
–
R 0003 Vo
L2
–
(c)
(d)
Figure P17.45
source Vx , node y disconnected from ground and connected to another input signal source Vy , and node z disconnected from ground and connected to a third input signal source Vz . Use superposition to find the voltage that develops across the resonator, Vo , in terms of Vx , Vy , and Vz . 17.50 Consider the notch circuit shown in Fig. 17.18(g). For what ratio of C2 to C1 does the notch occur at 1.1 ω0 ? For this case, what is the magnitude of the transmission at frequencies ω0 ? At frequencies ω0 ?
A1 0002 0003 Z1
Z2
Z3
1
Z4 2
0003
0002 A2
Section 17.6: Second-Order Active Filters Based on Inductor Replacement D 17.51 Design the circuit of Fig. 17.20 (utilizing suitable component values) to realize an inductance of (a) 15 H, (b) 1.5 H, and (c) 0.15 H. 17.52 Figure P17.52 shows a generalized form of the Antoniou circuit of Fig. 17.20(a). Here, R5 is eliminated and the other four components are replaced by general impedances Z1 , Z2 , Z3 , and Z4 . (a) With an impedance Z5 connected between node 2 and ground, show that the input impedance looking into port 1 (i.e., between node 1 and ground) is 0007 Z1 Z3 Z11 = Z Z2 Z4 5
Figure P17.52
(b) From the symmetry of the circuit, show that if an impedance Z6 is connected between terminal 1 and ground, the input impedance looking into port 2, which is between terminal 2 and ground, is given by 0007 Z22 =
Z2 Z4 Z Z1 Z3 6
(c) From the expressions above, observe that the two-port network in Fig. P17.52 acts as an “impedance transformer.” Since by the appropriate choice of Z1 , Z2 , Z3 , and Z4 , the transformation ratio can be a general function
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
CHAPTER 17
PROBLEMS
1374 Chapter 17 Filters and Tuned Amplifiers of the complex frequency variable s, the circuit is known as a generalized impedance converter, or GIC. 17.53 Consider the Antoniou circuit of Fig. 17.20(a) with R5 eliminated, a capacitor C6 connected between node 1 and ground, and a voltage source V2 connected to node 2. Show 2 that the input impedance seen by V2 is R2 /s C4 C6 R1 R3 . How does this impedance behave for physical frequencies (s = jω)? (This impedance is known as a frequency-dependent negative resistance, or FDNR.) *17.54 Starting from first principles and assuming ideal op amps, derive the transfer function of the circuit in Fig. 17.22(a). D *17.55 It is required to design a fifth-order Butterworth 5 filter having a 3-dB bandwidth of 10 rad/s and a unity dc gain. Use a cascade of two circuits of the type shown in Fig. 17.22(a) and a first-order op amp–RC circuit of the type shown in Fig. 17.13(a). Select appropriate component values. D 17.56 Design the circuit of Fig. 17.22(e) to realize an LPN function with f0 = 10 kHz, fn = 12 kHz, Q = 10, and a unity dc gain. Select C4 = 10 nF. D 17.57 Design the all-pass circuit of Fig. 17.22(g) to provide a phase shift of 180° at f = 2 kHz and to have Q = 2. Use 1-nF capacitors. D 17.58 Using the transfer function of the LPN filter, given in Table 17.1, derive the design equations also given. D 17.59 Using the transfer function of the HPN filter, given in Table 17.1, derive the design equations also given. D **17.60 It is required to design a third-order low-pass filter whose |T | is equiripple in both the passband and the stopband (in the manner shown in Fig. 17.3, except that the response shown is for N = 5). The filter passband extends from ω = 0 to ω = 1 rad/s, and the passband transmission varies between 1 and 0.9. The stopband edge is at ω = 1.2 rad/s. The following transfer function was obtained using filter-design tables: 0004 0005 2 0.4508 s + 1.6996 T (s) = (s + 0.7294)(s2 + s0.2786 + 1.0504) 5
The actual filter realized is to have ωp = 10 rad/s. (a) Obtain the transfer function of the actual filter by 5 replacing s by s/10 . (b) Realize this filter as the cascade connection of a first-order LP op amp–RC circuit of the type shown in Fig. 17.13(a)
and a second-order LPN circuit of the type shown in Fig. 17.22(e). Each section is to have a dc gain of unity. Select appropriate component values. (Note: A filter with an equiripple response in both the passband and the stopband is known as an elliptic filter.)
Section 17.7: Second-Order Active Filters Based on the Two-Integrator-Loop Topology D 17.61 Design the KHN circuit of Fig. 17.24(a) to realize a bandpass filter with a center frequency of 2 kHz and a 3-dB bandwidth of 50 Hz. Use 10-nF capacitors. Give the complete circuit and specify all component values. What value of center-frequency gain is obtained? D 17.62 (a) Using the KHN biquad with the output summing amplifier of Fig. 17.24(b), show that an all-pass function is realized by selecting RL = RH = RB /Q. Also show that the flat gain obtained is KRF /RH . 5 (b) Design the all-pass circuit to obtain ω0 = 10 rad/s, Q = 4, and flat gain = 10. Select appropriate component values. 17.63 Consider the case of the KHN circuit used together with the summing amplifier in Fig. 17.24(b) to realize a notch filter with a notch frequency ωn and a high-frequency gain of G. Find expressions for the values required of the resistances associated with the summing amplifier. D 17.64 Consider a notch filter with ωn = ω0 realized by using the KHN biquad with an output summing amplifier. If the summing resistors used have 1% tolerances, what is the worst-case percentage deviation between ωn and ω0 ? D 17.65 Design the circuit of Fig. 17.26 to realize a low-pass 5 notch filter with ω0 = 10 rad/s, Q = 10, dc gain = 1, and 5 ωn = 1.3 × 10 rad/s. Use C = 10 nF and r = 20 k0006. D 17.66 In the all-pass realization using the circuit of Fig. 17.26, which component(s) does one need to trim to adjust (a) only ωz and (b) only Qz ? D **17.67 Repeat Problem 17.60 using the Tow–Thomas biquad of Fig. 17.26 to realize the second-order section in the cascade.
Section 17.8: Single-Amplifier Biquadratic Active Filters D 17.68 Design the circuit of Fig. 17.29 to realize a pair of √ 5 poles with ω0 = 10 rad/s and Q = 1/ 2. Use C1 = C2 = 1 nF.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 1375
17.71 Consider the bridged-T network of Fig. 17.28(b) with R1 = R2 = R, C4 = C, and C3 = C/36. Let the network be placed in the negative-feedback path of an infinite-gain op amp and let C4 be disconnected from ground and connected to the input signal source Vi . Analyze the resulting circuit to determine its transfer function Vo (s)/Vi (s), where Vo (s) is the voltage at the op-amp output. Show that the circuit obtained is a bandpass filter and find its ω0 , Q, and the center-frequency gain. D 17.72 Use the circuit in Fig. 17.30(b) with α = 1 to realize a bandpass filter with a center frequency of 10 kHz and a 3-dB bandwidth of 2 kHz. Give the values of all components and specify the center-frequency gain obtained. D **17.73 Consider the bandpass circuit shown in 2 Fig. 17.30(a). Let C1 = C2 = C, R3 = R, R4 = R/4Q , CR = 2Q/ω0 , and α = 1. Disconnect the positive input terminal of the op amp from ground and apply Vi through a voltage divider R1 , R2 to the positive input terminal as well as through R4 /α as before. Analyze the circuit to find its transfer function Vo /Vi . Find the ratio R2 /R1 so that the circuit realizes (a) an all-pass function and (b) a notch function. Assume the op amp to be ideal. D *17.74 Derive the transfer function of the circuit in Fig. 17.33(b) assuming the op amp to be ideal. Thus show that the circuit realizes a high-pass function. What is the high-frequency gain of the circuit? Design the circuit for a 4 maximally flat response with a 3-dB frequency of 10 rad/s. Use C1√= C2 = 10 nF. (Hint: For a maximally flat response, Q = 1/ 2 and ω3dB = ω0 .) D *17.75 Design a fifth-order Butterworth low-pass filter that has a 3-dB bandwidth of 10 kHz and a dc gain of unity. Use the cascade connection of two Sallen-and-Key circuits [Fig. 17.34(c)] and a first-order section [Fig. 17.13(a)]. Use a 10-k0006 value for all resistors.
Section 17.9: Sensitivity 17.77 Evaluate the sensitivities of ω0 and Q relative to R, L, and C of the low-pass circuit in Fig. 17.18(b). *17.78 Verify the following sensitivity identities: (a) (b) (c) (d) (e)
If y = uv , then Sx = Sx + Sx . y u v If y = u/v , then Sx = Sx − Sx . y u If y = ku, where k is a constant, then Sx = Sx . n y u If y = u , where n is a constant, then Sx = nSx . y y u If y = f1 (u) and u = f2 (x), then Sx = Su · Sx . y
u
v
*17.79 For the high-pass filter of Fig. 17.33(b), what are the sensitivities of ω0 and Q to amplifier gain A? *17.80 For the feedback loop of Fig. 17.34(a), use the expressions in Eqs. (17.77) and (17.78) to determine the sensitivities of ω0 and Q relative to all passive components for the design in which R1 = R2 . 17.81 For the op amp–RC resonator of Fig. 17.21(b), use the expressions for ω0 and Q given in the top row of Table 17.1 to determine the sensitivities of ω0 and Q to all resistors and capacitors.
Section 17.10: Transconductance-C Filters 17.82 For the fully differential transconductor of Fig. 17.35(f), find an expression for Gm in terms of I and the MOSFET’s transconductance parameter kn . For kn = 0.5 mA/V, find the bias current I that results in Gm = 0.25 mA/V. If for tuning purposes it is required to adjust Gm in a ±5% range, what is the required range for adjusting I? D 17.83 Using the circuit of Fig. 17.36(a) to realize a 1-k0006 resistance, what Gm is needed? If the output resistance of the transconductor is 100 k0006, what is the resistance actually realized? D 17.84 Using four transconductors, give the circuit for obtaining an output voltage Vo related to three input voltages
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
17.70 Consider the bridged-T network of Fig. 17.28(a) with R3 = R4 = R and C1 = C2 = C, and denote CR = τ . Find the zeros and poles of the bridged-T network. If the network is placed in the negative-feedback path of an ideal infinite-gain op amp, as in Fig. 17.29, find the poles of the closed-loop amplifier.
D 17.76 The process of obtaining the complement of a transfer function by interchanging input and ground, as illustrated in Fig. 17.31, applies to any general network (not just RC networks as shown). Show that if the network n is a bandpass with a center-frequency gain of unity, then the complement obtained is a notch. Verify this by using the RLC circuits of Fig. 17.18(d) and (e).
CHAPTER 17
*17.69 Derive the transfer function t(s) of the bridged-T network in Fig. 17.28(a), and thus verify the expression given in the figure.
CHAPTER 17
PROBLEMS
1376 Chapter 17 Filters and Tuned Amplifiers V1 , V2 , and V3 by Vo = V1 − 2V2 + 3V3 . Give the values of the four transconductances as ratios of Gm of the transconductor that delivers the output voltage. D 17.85 For the integrator in Fig. 17.36(b), what value of Gm is needed to obtain an integrator with a unity-gain frequency of 10 MHz utilizing a 5-pF capacitor? D 17.86 If the transconductor in the integrator of Fig. 17.36(b) has an output resistance Ro and an output capacitance Co , what is the transfer function realized? If the error in the integrator time constant must be less than 1%, what is the smallest value of C that can be used? If the low-frequency pole introduced by Ro is to be at least two decades lower than the unity-gain frequency of the integrator, what is the smallest Gm that this transconductor must have? D 17.87 Design the first-order low-pass filter in Fig. 17.36(c) to have a pole frequency of 20 MHz and a dc gain of 10. Use C = 2 pF. D 17.88 If a capacitor C1 is connected between the input node and node X in the circuit of Fig. 17.36(c), what transfer function Vo /Vi is realized? D *17.89 For the circuit in Fig. P17.89:
(c) Use a fourth inverting transconductor Gm4 with its input connected to an input voltage Vi and its output connected to node 1. Compare the circuit thus created to the two-integrator-loop Gm –C filter of Fig. 17.37(b). (d) What filter function is (i) V1 /Vi , (ii) V2 /Vi ? D 17.90 Consider the Gm –C second-order bandpass filter of Fig. 17.37(b) and its associated expressions in Eqs. (17.95) and (17.96). Generate an alternative design based on selecting Gm1 = Gm2 = Gm3 = Gm and C2 = C. Find expressions for C1 and Gm in terms of ω0 , Q, and C. D 17.91 To enable the second-order Gm –C circuit in Fig. 17.37(b) to realize filter functions other than bandpass and lowpass, implement the following modifications: (a) Connect a capacitor C3 between the positive input terminal and the output terminal of transconductor Gm4 and (b) Add a fifth negative transconductor Gm5 with Vi applied to its input, and its output connected to the node at which V2 is taken. Derive an expression for the transfer function V1 /Vi .
+
D 17.92 Design the circuit of Fig. 17.37(c) to realize a bandpass function having a center frequency of 25 MHz, Q = 5, and a center-frequency gain of 5. Select Gm1 = Gm2 and C1 = C2 = 5 pF.
–
Section 17.11: Switched-Capacitor Filters
– Gm1
I1 1
+
0003
Gm2 +
V1 – Zin ≡
2
– C V1 I1
Figure P17.89
(a) Show that the input impedance Zin is that of an inductance L and find an expression for L. (b) Use the inductance generated at the input to form an LCR resonator. To realize the resistance R, use a third transconductor Gm3 .
17.93 For the switched-capacitor input circuit of Fig. 17.38(b), in which a clock frequency of 200 kHz is used, what input resistances correspond to capacitance C1 values of 1 pF, 5 pF, and 10 pF? 17.94 For a dc voltage of 1 V applied to the input of the circuit of Fig. 17.38(b), in which C1 is 1 pF, what charge is transferred for each cycle of the two-phase clock? For a 100-kHz clock, what is the average current drawn from the input source? For a feedback capacitance of 10 pF, what change would you expect in the output for each cycle of the clock? For an amplifier that saturates at ±10 V and the feedback capacitor initially discharged, how many clock cycles would it take to saturate the amplifier? What is the average slope of the staircase output voltage produced? D 17.95 Repeat Exercise 17.32 for a clock frequency of 500 kHz.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 1377
0002 0003 T jω0 |T ( jω)| 0007 0002 00032 1 + 4Q2 δω/ω0
Section 17.12: Tuned Amplifiers *17.98 A voltage signal source with a resistance Rs = 10 k0006 is connected to the input of a common-emitter BJT amplifier. Between base and emitter is connected a tuned circuit with L = 0.5 μH and C = 200 pF. The transistor is biased at 1 mA and has β = 200, Cπ = 10 pF, and Cμ = 0.5 pF. The transistor load is a resistance of 5 k0006. Find ω0 , Q, the 3-dB bandwidth, and the center-frequency gain of this single-tuned amplifier. 17.99 A coil having an inductance of 10 μH is intended for applications around 1-MHz frequency. Its Q is specified to be 250. Find the equivalent parallel resistance Rp . What is the value of the capacitor required to produce resonance at 1 MHz? What additional parallel resistance is required to produce a 3-dB bandwidth of 12 kHz? 17.100 An inductance of 36 μH is resonated with a 1000-pF capacitor. If the inductor is tapped at one-third of its turns and a 1-k0006 resistor is connected across the one-third part, find f0 and Q of the resonator. *17.101 Consider a common-emitter transistor amplifier loaded with an inductance L. Ignoring ro , show that for ωCμ 1/ωL, the amplifier input admittance is given by 0007 0003 0002 1 2 Yin 0007 − ω Cμ Lgm + jω Cπ + Cμ rπ (Note: The real part of the input admittance can be negative. This can lead to oscillations.)
(b) Use the result obtained in (a) to show that the 3-dB bandwidth B, of N synchronously tuned sections connected in cascade, is 0002 0003√ B = ω0 /Q 21/N − 1 **17.103 (a) Using the fact that for Q 1 the second-order bandpass response in the neighborhood of ω0 is the same as the response of a first-order low-pass with 3-dB frequency of (ω0 /2Q), show that the bandpass response at ω = ω0 + δω, for δω ω0 , is given by 0002 0003 T jω0 |T ( jω)| 0007 0002 00032 1 + 4Q2 δω/ω0 (b) Use the relationship derived in (a) together with Eq. (17.123) to show that a bandpass amplifier with a 3-dB bandwidth B, designed using N synchronously tuned stages, has an overall transfer function given by T ( jω)
overall
=0011
0002 0003 T jω0
overall
1 + 4(21/N − 1)(δω/B)2
0012N/2
(c) Use the relationship derived in (b) to find the attenuation (in decibels) obtained at a bandwidth 2B for N = 1 to 5. Also find the ratio of the 30-dB bandwidth to the 3-dB bandwidth for N = 1 to 5.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
D 17.97 Design the circuit of Fig. 17.40(b) to realize, at the output of the second (noninverting) integrator, a maximally 3 flat low-pass function with ω3dB = 10 rad/s and unity dc gain. Use a clock frequency fc = 100 kHz and select C1 = C2 = 5 pF. Give the values of C3√ , C4 , C5 , and C6 . (Hint: For a maximally flat response, Q = 1/ 2 and ω3dB = ω0 .)
*17.102 (a) Substituting s = jω in the transfer function T(s) of a second-order bandpass filter [see Fig. 17.16(c)], find |T ( jω)|. For ω in the vicinity of ω0 [i.e., ω = ω0 + 0002 0003 2 δω = ω0 1 + δω/ω0 , where δω/ω0 1 so that ω 0007 0002 0003 2 ω0 1 + 2δω/ω0 ], show that, for Q 1,
CHAPTER 17
D 17.96 Repeat Exercise 17.32 for Q = 50.
1428 Chapter 18 Signal Generators and Waveform-Shaping Circuits
Summary 0002
0002
There are two distinctly different types of signal generator: the linear oscillator, which utilizes some form of resonance, and the nonlinear oscillator or function generator, which employs a switching mechanism implemented with a multivibrator circuit. A linear oscillator can be realized by placing a frequency-selective network in the feedback path of an amplifier (an op amp or a transistor). The circuit will oscillate at the frequency at which the total phase shift around the loop is zero or 360°, provided the magnitude of loop gain at this frequency is equal to, or greater than, unity.
0002
If in an oscillator the magnitude of loop gain is greater than unity, the amplitude will increase until a nonlinear amplitude-control mechanism is activated.
0002
The Wien-bridge oscillator, the phase-shift oscillator, the quadrature oscillator, and the active-filter-tuned oscillator are popular configurations for frequencies up to about 1 MHz. These circuits employ RC networks together with op amps or transistors. For higher frequencies, LC-tuned or crystal-tuned oscillators are utilized. Popular configurations include the Colpitts circuit for discrete-circuit implementation and the cross-coupled circuit for IC implementation at frequencies as high as hundreds of gigahertz.
0002
Crystal oscillators provide the highest possible frequency accuracy and stability.
0002
There are three types of multivibrator: bistable, monostable, and astable. Op-amp circuit implementations
of multivibrators are useful in analog-circuit applications that require high precision. 0002
The bistable multivibrator has two stable states and can remain in either state indefinitely. It changes state when triggered. A comparator with hysteresis is bistable.
0002
A monostable multivibrator, also known as a one-shot, has one stable state, in which it can remain indefinitely. When triggered, it goes into a quasi-stable state in which it remains for a predetermined interval, thus generating, at its output, a pulse of known width.
0002
An astable multivibrator has no stable state. It oscillates between two quasi-stable states, remaining in each for a predetermined interval. It thus generates a periodic waveform at the output.
0002
A feedback loop consisting of an integrator and a bistable multivibrator can be used to generate triangular and square waveforms.
0002
The 555 timer, a commercially available IC, can be used with external resistors and a capacitor to implement high-quality monostable and astable multivibrators.
0002
A sine waveform can be generated by feeding a triangular waveform to a sine-wave shaper. A sine-wave shaper can be implemented either by using diodes (or transistors) and resistors, or by using an amplifier having a nonlinear transfer characteristic that approximates the sine function.
PROBLEMS Section 18.1: Basic Principles of Sinusoidal Oscillators 18.1 Consider a sinusoidal oscillator consisting of an amplifier having a frequency-independent gain A (where A is positive) and a second-order bandpass filter with a pole frequency ω0 , a pole Q denoted Q, and a positive center-frequency gain K. Find the frequency of oscillation, and the condition that A and K must satisfy for sustained oscillation. 18.2 For the oscillator circuit described in Problem 18.1: (a) Derive an expression for dφ/dω, evaluated at ω = ω0 .
(b) Use the result of (a) to find an expression for the per-unit change in frequency of oscillation resulting from a phase-angle change of 0005φ, in the amplifier transfer function.
Hint:
d 0012 −1 0013 1 dy tan y = dx 1 + y2 dx
18.3 For the oscillator described in Problem 18.1, show that, independent of the value of A and K, the poles of the circuit
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 1429
C R
Figure P18.7
18.5 An oscillator is formed by loading a transconductance amplifier having a positive gain with a parallel RLC circuit and connecting the output directly to the input (thus applying positive feedback with a factor β = 1). Let the transconductance amplifier have an input resistance of 5 k0007 and an output resistance of 5 k0007. The LC resonator has L = 1 μH, C = 100 pF, and Q = 50. For what value of transconductance Gm will the circuit oscillate? At what frequency?
D 18.8 Consider the circuit of Fig. 18.4(a) with Rf removed to realize the comparator function. Find suitable values for all resistors so that the comparator output levels are ±3 V and the slope of the limiting characteristic is 0.05. Use power-supply voltages of ±5 V and assume the voltage drop of a conducting diode to be 0.7 V.
18.6 In a particular oscillator characterized by the structure of Fig. 18.1, the frequency-selective network exhibits a loss of 12 dB and a phase shift of 180° at ω0 . Give the phase shift and the minimum gain that the amplifier must have for oscillation to begin. 18.7 An oscillator is designed by connecting in a loop three identical common-source amplifier stages of the type shown in Fig. P18.7. Note that the bias circuits are not shown, and assume that R and C include the transistor output resistance and capacitance, respectively. For the circuit to oscillate at a frequency ω0 , what must the phase angle provided by each amplifier stage be? Give an expression for ω0 . For sustained oscillations, what is the minimum gm required of each transistor?
(a)
D 18.9 Consider the circuit of Fig. 18.4(a) with Rf removed to realize the comparator function. Sketch the transfer characteristic. Show that by connecting a dc source VB to the virtual ground of the op amp through a resistor RB , the transfer characteristic is shifted along the v I axis to the point 0006 0005 v I = − R1 /RB VB . Utilizing available ±5-V dc supplies for ±V and for VB , find suitable component values so that the limiting levels are ±3 V and the comparator threshold is at v I = +2 V. Neglect the diode voltage drop (i.e., assume that VD = 0). The input resistance of the comparator is to be 100 k0007, and the slope in the limiting regions is to be ≤ 0.05 V/V. Use standard 5% resistors (see Appendix J). 18.10 Denoting the zener voltages of Z1 and Z2 by VZ1 and VZ2 and assuming that in the forward direction the voltage drop
(b)
Figure P18.10
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
D 18.4 For the oscillator circuit in Fig. 18.3(a) find the percentage change in the oscillation frequency resulting from a change of +1% in the value of (a) L, (b) C, and (c) R.
CHAPTER 18
lie at a radial distance of ω0 . Find the value of AK that results in poles appearing (a) on the jω axis, and (b) in the right half of the s plane, at a horizontal distance from the jω axis of ω0 /(2Q).
CHAPTER 18
PROBLEMS
1430 Chapter 18 Signal Generators and Waveform-Shaping Circuits is approximately 0.7 V, sketch and clearly label the transfer characteristics v O –v I of the circuits in Fig. P18.10. Assume the op amps to be ideal.
18.16 Repeat Problem 18.15 for the circuit in Fig. P18.16.
Section 18.2: Op Amp–RC Oscillator Circuits 18.11 For the Wien-bridge oscillator circuit in Fig. 18.5, show that the transfer function of the feedback network 000f 0010 Va (s)/Vo (s) is that of a bandpass filter. Find ω0 and Q of the poles, and find the center-frequency gain. 18.12 For the Wien-bridge oscillator of Fig. 18.5, let the closed-loop amplifier (formed by the op amp and the resistors R1 and R2 ) exhibit a phase shift of −3° in the neighborhood of ω = 1/CR. Find the frequency at which oscillations can occur in this case in terms of CR. (Hint: Use Eq. 18.11.) 18.13 For the Wien-bridge oscillator of Fig. 18.5, use the expression for loop gain in Eq. (18.10) to find the poles of the closed-loop system. Give the expression for the pole Q, and use it to show that to locate the poles in the right half of the s plane, R2 /R1 must be selected to be greater than 2. D 18.14 Reconsider Exercise 18.5 with R3 and R6 increased to reduce the output voltage. What values are required for a peak-to-peak output of 8 V? What results if R3 and R6 are open-circuited? 18.15 For the circuit in Fig. P18.15, find L(s), L(jω), the frequency for zero loop phase, and R2 /R1 for oscillation. Assume the op amp to be ideal.
R1
R2
0004 0003 C
R C
Figure P18.15
R
Figure P18.16
*18.17 Consider the circuit of Fig. 18.7 with the 50-k0007 potentiometer replaced by two fixed resistors: 10 k0007 between the op amp’s negative input and ground, and 15 k0007. Modeling each diode as a 0.65-V battery in series with a 100-0007 resistance, find the peak-to-peak amplitude of the output sinusoid. D **18.18 Design the circuit of Fig. 18.7 for operation at 10 kHz using R = 10 k0007. If at 10 kHz the op amp provides an excess phase shift (lag) of 5.7°, what will be the frequency of oscillation? (Assume that the phase shift introduced by the op amp remains constant for frequencies around 10 kHz.) To restore operation to 10 kHz, what change must be made in the shunt resistor of the Wien bridge? Also, to what value must R2 /R1 be changed? *18.19 For the circuit of Fig. 18.9, connect an additional resistor (R = 10 k0007) in series with the rightmost capacitor C. For this modification (and ignoring the amplitude stabilization circuitry), find the loop gain Aβ by breaking the circuit at node X. Find Rf for oscillation to begin, and find f0 . D 18.20 For the circuit in Fig. P18.19, break the loop at node X and find the loop gain (working backward for simplicity to
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 1431
CHAPTER 18 PROBLEMS
Figure P18.20
find Vx in terms of Vo ). For R = 10 k0007, find C and Rf to obtain sinusoidal oscillations at 15 kHz. *18.21 Consider the quadrature-oscillator circuit of Fig. 18.10 without the limiter. Let the resistance Rf be equal to 2R/(1 + 0005), where 0005 1. Show that the poles of the characteristic equation are in the right-half s plane and given by s 0007 (1/CR)[(0005/4) ± j]. D 18.22 Using C = 1.6 nF, find the value of R such that the circuit of Fig. 18.12 produces 10-kHz sine waves. If the diode drop is 0.7 V, find the peak-to-peak amplitude of the output sine wave. How do you modify the circuit to double the output amplitude? (Hint: A square wave with peak-to-peak amplitude of V volts has a fundamental component with 4V /π volts peak-to-peak amplitude.) *18.23 Assuming that the diode-clipped waveform in Exercise 18.9 is nearly an ideal square wave and that the resonator Q is 20, provide an estimate of the distortion in the output sine wave by calculating the magnitude (relative to the fundamental) of (a) (b) (c) (d)
the second harmonic the third harmonic the fifth harmonic the rms of harmonics to the tenth
Section 18.3: LC and Crystal Oscillators 18.24 For the Colpitts oscillator circuit in Fig. P18.24, derive an equation governing circuit operation and hence find the frequency of oscillation and the condition on the gain gm RL that ensures that oscillations will start. Assume that RL includes ro of Q1 . Simplify your final expressions by assuming rπ is large. Observe that this circuit is based on the configuration in Fig. 18.13(a) except that here the biasing circuit is included and the collector is placed at signal ground.
L
Q1 C2
C1 I
RL
Figure P18.24
Note that a square wave of amplitude V and frequency ω is represented by the series 0002 0003 4V 1 1 1 sin ωt + sin 3 ωt + sin 5 ωt + sin 7 ωt + . . . π 3 5 7
18.25 For the Colpitts oscillator circuit in Fig. P18.25, derive an equation governing circuit operation and hence find the frequency of oscillation and the condition the gain gm RL must
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
1432 Chapter 18 Signal Generators and Waveform-Shaping Circuits satisfy for oscillations to start. Assume that RL includes the MOSFET’s ro .
of the BJT is included in RL and neglect Rf (i.e., assume Rf ω0 L). Simplify your final expressions by assuming rπ is large. Observe that this circuit is similar to that in Fig. 18.15 except for utilizing a different biasing scheme.
CHAPTER 18
L Q1 C2
I C2
C1 RL
I
L
C1
Figure P18.25
18.26 For the Colpitts oscillator circuit in Fig. P18.26, derive an equation governing circuit operation and hence find the frequency of oscillation and the condition the gain gm RL must satisfy to ensure that oscillations will start. Neglect ro of the BJT. Simplify your final expressions by assuming that rπ is large. Note that this circuit is based on the configuration of Fig. 18.13(a) but with the bias circuit included and the base grounded.
Rf
Q1
RL Figure P18.27
*18.28 The LC oscillator in Fig. P18.28 is based on connecting a positive-gain amplifier (formed by Q1 , Q2 , and RC ) with a bandpass RLC circuit in a feedback loop.
L
Q1
C1
I
C2
RL
Figure P18.26
18.27 For the Colpitts oscillator circuit in Fig. P18.27, derive an equation governing circuit operation and hence find the frequency of oscillation and the condition the gain gm RL must satisfy to ensure that oscillations will start. Assume that ro
Figure P18.28
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 1433 (b) Let L+ = − L− = V and R1 = 10 k0007. Find R2 and VR that result in threshold voltages of 0 and V/10.
D 18.29 Design the cross-coupled LC oscillator of Fig. 18.16(a) to operate at ω0 = 20 Grad/s. The IC inductors available have L = 5 nH and Q = 10. If the transistor ro = 5 k0007, find the required value of C and the minimum required value of gm at which Q1 and Q2 are to be operated. 18.30 Consider the Pierce crystal oscillator of Fig. 18.18 with the crystal as specified in Exercise 18.13. Let C1 be variable in the range 1 pF to 10 pF, and let C2 be fixed at 10 pF. Find the range over which the oscillation frequency can be tuned. (Hint: Use the result in the statement leading to the expression in Eq. 18.29.)
Section 18.4: Bistable Multivibrators D 18.31 Design the bistable circuit in Fig. 18.21(a) to obtain a hysteresis of 2-V width. The op amp saturates at ±5 V. Select R1 = 10 k0007 and determine R2 . 18.32 Consider the bistable circuit of Fig. 18.21(a) with the op amp’s positive input terminal connected to a positive-voltage source V through a resistor R3 . (a) Derive expressions for the threshold voltages VTL and VTH in terms of the op amp’s saturation levels L+ and L− , R1 , R2 , R3 , and V. (b) Let L+ = − L− = 10 V, V = 15 V, and R1 = 10 k0007. Find the values of R2 and R3 that result in VTL = +4.9 V and VTH = +5.1 V. 18.33 Consider the bistable circuit of Fig. 18.22(a) with the op amp’s negative-input terminal disconnected from ground and connected to a reference voltage VR . (a) Derive expressions for the threshold voltages VTL and VTH in terms of the op amp’s saturation levels L+ and L− , R1 , R2 , and VR .
Figure P18.34
18.35 Consider the circuit of Fig. P18.34 with R1 eliminated and R2 short-circuited. Sketch and label the transfer characteristic v O−v I . Assume that the diodes have a constant 0.7-V drop when conducting and that the op amp saturates at ±12 V. *18.36 Consider a bistable circuit having a noninverting transfer characteristic with L+ = −L− = 12 V, VTL = −1 V, and VTH = +1 V. (a) For a 0.5-V-amplitude sine-wave input having zero average, what is the output? (b) Describe the output if a sinusoid of frequency f and amplitude of 1.1 V is applied at the input. By how much can the average of this sinusoidal input shift before the output becomes a constant value? D 18.37 Design the circuit of Fig. 18.25(a) to realize a transfer characteristic with ±7.5-V output levels and ±7.5-V threshold values. Design so that when v I = 0 V a current of 0.5 mA flows in the feedback resistor and a current of 1 mA flows through the zener diodes. Assume that the output saturation levels of the op amp are ±10 V. Specify the voltages of the zener diodes and give the values of all resistors.
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
18.34 For the circuit in Fig. P18.34, sketch and label the transfer characteristic v O−v I . The diodes are assumed to have a constant 0.7-V drop when conducting, and the op amp saturates at ±12 V. What is the maximum diode current?
CHAPTER 18
(a) Replace the BJTs with their small-signal models while neglecting rπ and ro (to simplify matters). (b) By inspection of the circuit found in (a), find the frequency of oscillation and the condition required for oscillations to start. Express the latter as the minimum required value of (IRC ). (c) If IRC is selected equal to 1 V, show that oscillations will start. If oscillations grow to the point that Vo is large enough to turn the BJTs on and off, show that the signal at the collector of Q2 will be a square wave of 1 V peak-to-peak. Estimate the peak-to-peak amplitude of the output sine wave Vo .
R4 R3
R2 R1
CHAPTER 18
PROBLEMS
1434 Chapter 18 Signal Generators and Waveform-Shaping Circuits
0004 0003
0003 0004
R7
R5 Z1
R6
C
Z2
Figure P18.41
Section 18.5: Generation of Square and Triangular Waveforms Using Astable Multivibrators 18.38 Find the frequency of oscillation of the circuit in Fig. 18.26(b) for the case R1 = 10 k0007, R2 = 16 k0007, C = 5 nF, and R = 62 k0007. D 18.39 Augment the astable multivibrator circuit of Fig. 18.26(b) with an output limiter of the type shown in Fig. 18.25(b). Design the circuit to obtain an output square wave with 5-V amplitude and 1-kHz frequency using a 10-nF capacitor C. Use β = 0.462, and design for a current in the resistive divider approximately equal to the average current in the RC network over a half-cycle. Assuming ±13-V op-amp saturation voltages, arrange for the zener to operate at a minimum current of 1 mA. Specify the values of all resistors and the zenor voltage. D 18.40 Using the scheme of Fig. 18.27, design a circuit that provides square waves of 10 V peak to peak and triangular waves of 10 V peak to peak. The frequency is to be 1 kHz. Implement the bistable circuit with the circuit of Fig. 18.25(b). Use a 0.01-μF capacitor and specify the values of all resistors and the required zener voltage. Design for a minimum zener current of 1 mA and for a maximum current in the resistive divider of 0.2 mA. Assume that the output saturation levels of the op amps are ±12 V. D *18.41 The circuit of Fig. P18.41 consists of an inverting bistable multivibrator with an output limiter and a
noninverting integrator. Using equal values for all resistors except R7 and a 0.5-nF capacitor, design the circuit to obtain a square wave at the output of the bistable multivibrator of 15-V peak-to-peak amplitude and 10-kHz frequency. Sketch and label the waveform at the integrator output. Assuming ±13-V op-amp saturation levels, design for a minimum zener current of 1 mA. Specify the zener voltage required, and give the values of all resistors.
Section 18.6: Generation of a Standardized Pulse—The Monostable Multivibrator D 18.42 For the monostable circuit considered in Exercise 18.22, calculate the recovery time. *18.43 Figure P18.43 shows a monostable multivibrator circuit. In the stable state, v O = L+ , v A = 0, and v B = −Vref . The circuit can be triggered by applying a positive input pulse of height greater than Vref . For normal operation, C1 R1 CR. Show the resulting waveforms of v O and v A . Also, show that the pulse generated at the output will have a width T given by 0002 T = CR ln
L + − L− Vref
0003
Note that this circuit has the interesting property that the pulse width can be controlled by changing Vref .
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
Problems 1435
D *18.44 Using the circuit of Fig. 18.28, with a nearly ideal op amp for which the saturation levels are ±13 V, design a monostable multivibrator to provide a negative output pulse of 100-μs duration. Use capacitors of 0.1 nF and 1 nF. Wherever possible, choose resistors of 100 k0007 in your design. Diodes have a drop of 0.7 V. What is the minimum input step size that will ensure triggering? How long does the circuit take to recover to a state in which retriggering is possible with a normal output?
Section 18.7: Integrated-Circuit Timers 18.45 Consider the 555 circuit of Fig. 18.29 when the Threshold and the Trigger input terminals are joined together and connected to an input voltage v I . Verify that the transfer characteristic v O –v I is that of an inverting bistable circuit with thresholds VTL = 13 VCC and VTH = 23 VCC and output levels of 0 and VCC . D 18.46 (a) Using a 0.5-nF capacitor C in the circuit of Fig. 18.30(a), find the value of R that results in an output pulse of 10-μs duration. (b) If the 555 timer used in (a) is powered with VCC = 12 V, and assuming that VTH can be varied externally (i.e., it need not remain equal to 23 VCC ), find its required value so that the pulse width is increased to 20 μs, with other conditions the same as in (a).
Section 18.8: Nonlinear Waveform-Shaping Circuits D *18.49 The two-diode circuit shown in Fig. P18.49 can provide a crude approximation to a sine-wave output when driven by a triangular waveform. To obtain a good approximation, we select the peak of the triangular waveform, V, so that the slope of the desired sine wave at the zero crossings is equal to that of the triangular wave. Also, the value of R is selected so that when v I is at its peak, the output voltage is equal to the desired peak of the sine wave. If the diodes exhibit a voltage drop of 0.7 V at 1-mA current, changing at the rate of 0.1 V per decade, find the values of V and R that will yield an approximation to a sine waveform of 0.7-V peak amplitude. Then find the angles θ (where θ = 90° when v I is at its peak) at which the output of the circuit, in volts, is 0.7, 0.65, 0.6, 0.55, 0.5, 0.4, 0.3, 0.2, 0.1, and 0. Use the
D 18.47 Using a 680-pF capacitor, design the astable circuit of Fig. 18.31(a) to obtain a square wave with a 20-kHz frequency and an 80% duty cycle. Specify the values of RA and RB . *18.48 The node in the 555 timer at which the voltage is VTH (i.e., the inverting input terminal of comparator 1) is usually
Figure P18.49
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
PROBLEMS
Figure P18.43
(a) For the astable circuit of Fig. 18.31, rederive the expressions for TH and TL , expressing them in terms of VTH and VTL . (b) For the case C = 1 nF, RA = 7.2 k0007, RB = 3.6 k0007, and VCC = 5 V, find the frequency of oscillation and the duty cycle of the resulting square wave when no external voltage is applied to the terminal VTH . (c) For the design in (b), let a sine-wave signal of a much lower frequency than that found in (b) and of 1-V peak amplitude be capacitively coupled to the circuit node VTH . This signal will cause VTH to change around its quiescent value of 23 VCC , and thus TH will change correspondingly—a modulation process. Find TH , and find the frequency of oscillation and the duty cycle at the two extreme values of VTH .
CHAPTER 18
connected to an external terminal. This allows the user to change VTH externally (i.e., VTH no longer remains at 23 VCC ). Note, however, that whatever the value of VTH becomes, VTL always remains 21 VTH .
CHAPTER 18
PROBLEMS
1436 Chapter 18 Signal Generators and Waveform-Shaping Circuits angle values obtained to determine the values of the exact sine wave (i.e., 0.7 sin θ ), and thus find the percentage error of this circuit as a sine shaper. Provide your results in tabular form. D 18.50 Design a two-segment sine-wave shaper using a 6.8-k0007-input resistor, two diodes, and two clamping voltages. The circuit, fed by an 8-V peak-to-peak triangular wave, should limit the amplitude of the output signal via a 0.7-V diode to a value corresponding to that of a sine wave whose zero-crossing slope matches that of the triangle. What are the clamping voltages you have chosen? 18.51 Show that the output voltage of the circuit in Fig. P18.51 is given by 0002 0003 vI v O = −VT ln , vI > 0 IS R
where IS is the saturation current of the diode and VT is the thermal voltage. Since the output voltage is proportional to the logarithm of the input voltage, the circuit is known as a logarithmic amplifier. Such amplifiers find application in situations where it is desired to compress the signal range. 18.52 Verify that the circuit in Fig. P18.52 implements the transfer characteristic v O = −v 1 v 2 for v 1 , v 2 > 0. Such a circuit is known as an analog multiplier. Check the circuit’s performance for various combinations of input voltage of values, say, 0.5 V, 1 V, 2 V, and 3 V. Assume all diodes to be identical, with 700-mV drop at 1-mA current. Note that a squarer can easily be produced using a single input (e.g., v 1 ) connected via a 0.5-k0007 resistor (rather than the 1-k0007 resistor shown). **18.53 Detailed analysis of the circuit in Fig. 18.34 shows that optimum performance (as a sine shaper) occurs when the values of I and R are selected so that RI = 2.5VT , where VT is the thermal voltage, and the peak amplitude of the input triangular wave is 6.6VT . If the output is taken across R (i.e., between the two emitters), find v I corresponding to v O = 0.25VT , 0.5VT , VT , 1.5VT , 2VT , 2.4VT , and 2.42VT . Plot v O –v I and compare to the ideal curve given by
v O = 2.42VT sin
Figure P18.51
0002
vI 6.6VT
D1 0004 A
0003 D2
D4
0004
0004 B
0003
0003
D
0004 0003
D3 0004 0003
C
Figure P18.52
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem
0003
× 90°